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Added ROL, ROR and NOP uops to ARM and ARM64 backends.

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This commit is contained in:
SarahW 2019-03-31 18:21:56 +01:00
commit 584e67845b
6 changed files with 504 additions and 2 deletions
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11
src/codegen_backend_arm64_ops.c
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@ -91,6 +91,7 @@
#define OPCODE_ORR_ASR (0x154 << 21)
#define OPCODE_ORR_LSL (0x150 << 21)
#define OPCODE_ORR_LSR (0x152 << 21)
#define OPCODE_ORR_ROR (0x156 << 21)
#define OPCODE_ORRX_LSL (0x550 << 21)
#define OPCODE_SUB_LSL (0x258 << 21)
#define OPCODE_SUB_LSR (0x25a << 21)
@ -164,6 +165,7 @@
#define OPCODE_NOP (0xd503201f)
#define OPCODE_ORR_V (0x0ea01c00)
#define OPCODE_RET (0xd65f0000)
#define OPCODE_ROR (0x1ac02c00)
#define OPCODE_SADDLP_V2S_4H (0x0e602800)
#define OPCODE_SCVTF_D_Q (0x9e620000)
#define OPCODE_SCVTF_D_W (0x1e620000)
@ -994,6 +996,10 @@ void host_arm64_MOV_REG_LSR(codeblock_t *block, int dst_reg, int src_m_reg, int
{
codegen_addlong(block, OPCODE_ORR_LSR | Rd(dst_reg) | Rn(REG_WZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void host_arm64_MOV_REG_ROR(codeblock_t *block, int dst_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ORR_ROR | Rd(dst_reg) | Rn(REG_WZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void host_arm64_MOVX_IMM(codeblock_t *block, int reg, uint64_t imm_data)
{
@ -1092,6 +1098,11 @@ void host_arm64_RET(codeblock_t *block, int reg)
codegen_addlong(block, OPCODE_RET | Rn(reg));
}
void host_arm64_ROR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg)
{
codegen_addlong(block, OPCODE_ROR | Rd(dst_reg) | Rn(src_n_reg) | Rm(shift_reg));
}
void host_arm64_SADDLP_V2S_4H(codeblock_t *block, int dst_reg, int src_n_reg)
{
codegen_addlong(block, OPCODE_SADDLP_V2S_4H | Rd(dst_reg) | Rn(src_n_reg));