Retro/pcem
Watch
1
0
Fork
You've already forked pcem
 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Pack decoded ModR/M data into a single word - minor recompiler speedup.

Browse source
This commit is contained in:
SarahW 2016-08-14 16:29:54 +01:00
commit 535604b760
34 changed files with 1263 additions and 1270 deletions
Download patch file Download diff file Expand all files Collapse all files

84
src/x86_ops_mov_seg.h
View file

@ -24,7 +24,7 @@ static int opMOV_w_seg_a16(uint32_t fetchdat)
break;
}
CLOCK_CYCLES((mod == 3) ? 2 : 3);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
return abrt;
}
static int opMOV_w_seg_a32(uint32_t fetchdat)
@ -53,7 +53,7 @@ static int opMOV_w_seg_a32(uint32_t fetchdat)
break;
}
CLOCK_CYCLES((mod == 3) ? 2 : 3);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
return abrt;
}
@ -64,32 +64,32 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x00: /*ES*/
if (mod == 3) cpu_state.regs[rm].l = ES;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = ES;
else seteaw(ES);
break;
case 0x08: /*CS*/
if (mod == 3) cpu_state.regs[rm].l = CS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = CS;
else seteaw(CS);
break;
case 0x18: /*DS*/
if (mod == 3) cpu_state.regs[rm].l = DS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = DS;
else seteaw(DS);
break;
case 0x10: /*SS*/
if (mod == 3) cpu_state.regs[rm].l = SS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = SS;
else seteaw(SS);
break;
case 0x20: /*FS*/
if (mod == 3) cpu_state.regs[rm].l = FS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = FS;
else seteaw(FS);
break;
case 0x28: /*GS*/
if (mod == 3) cpu_state.regs[rm].l = GS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = GS;
else seteaw(GS);
break;
}
CLOCK_CYCLES((mod == 3) ? 2 : 3);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
return abrt;
}
static int opMOV_l_seg_a32(uint32_t fetchdat)
@ -99,32 +99,32 @@ static int opMOV_l_seg_a32(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x00: /*ES*/
if (mod == 3) cpu_state.regs[rm].l = ES;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = ES;
else seteaw(ES);
break;
case 0x08: /*CS*/
if (mod == 3) cpu_state.regs[rm].l = CS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = CS;
else seteaw(CS);
break;
case 0x18: /*DS*/
if (mod == 3) cpu_state.regs[rm].l = DS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = DS;
else seteaw(DS);
break;
case 0x10: /*SS*/
if (mod == 3) cpu_state.regs[rm].l = SS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = SS;
else seteaw(SS);
break;
case 0x20: /*FS*/
if (mod == 3) cpu_state.regs[rm].l = FS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = FS;
else seteaw(FS);
break;
case 0x28: /*GS*/
if (mod == 3) cpu_state.regs[rm].l = GS;
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = GS;
else seteaw(GS);
break;
}
CLOCK_CYCLES((mod == 3) ? 2 : 3);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
return abrt;
}
@ -164,7 +164,7 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
break;
}
CLOCK_CYCLES((mod == 3) ? 2 : 5);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
return abrt;
}
static int opMOV_seg_w_a32(uint32_t fetchdat)
@ -203,7 +203,7 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
break;
}
CLOCK_CYCLES((mod == 3) ? 2 : 5);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
return abrt;
}
@ -213,11 +213,11 @@ static int opLDS_w_a16(uint32_t fetchdat)
uint16_t addr, seg;
fetch_ea_16(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
cpu_state.regs[reg].w = addr;
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
return 0;
@ -227,11 +227,11 @@ static int opLDS_w_a32(uint32_t fetchdat)
uint16_t addr, seg;
fetch_ea_32(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
cpu_state.regs[reg].w = addr;
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
return 0;
@ -242,11 +242,11 @@ static int opLDS_l_a16(uint32_t fetchdat)
uint16_t seg;
fetch_ea_16(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
cpu_state.regs[reg].l = addr;
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
return 0;
@ -257,11 +257,11 @@ static int opLDS_l_a32(uint32_t fetchdat)
uint16_t seg;
fetch_ea_32(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
cpu_state.regs[reg].l = addr;
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
return 0;
@ -272,11 +272,11 @@ static int opLSS_w_a16(uint32_t fetchdat)
uint16_t addr, seg;
fetch_ea_16(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
cpu_state.regs[reg].w = addr;
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
return 1;
@ -286,11 +286,11 @@ static int opLSS_w_a32(uint32_t fetchdat)
uint16_t addr, seg;
fetch_ea_32(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
cpu_state.regs[reg].w = addr;
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
return 1;
@ -301,11 +301,11 @@ static int opLSS_l_a16(uint32_t fetchdat)
uint16_t seg;
fetch_ea_16(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
cpu_state.regs[reg].l = addr;
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
return 1;
@ -316,11 +316,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
uint16_t seg;
fetch_ea_32(fetchdat);
ILLEGAL_ON(mod == 3);
ILLEGAL_ON(cpu_mod == 3);
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
cpu_state.regs[reg].l = addr;
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
return 1;
@ -332,11 +332,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
uint16_t addr, seg; \
\
fetch_ea_16(fetchdat); \
ILLEGAL_ON(mod == 3); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmemw(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
cpu_state.regs[reg].w = addr; \
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
return 0; \
@ -347,11 +347,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
uint16_t addr, seg; \
\
fetch_ea_32(fetchdat); \
ILLEGAL_ON(mod == 3); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmemw(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
cpu_state.regs[reg].w = addr; \
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
return 0; \
@ -363,11 +363,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
uint16_t seg; \
\
fetch_ea_16(fetchdat); \
ILLEGAL_ON(mod == 3); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmeml(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
cpu_state.regs[reg].l = addr; \
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
return 0; \
@ -379,11 +379,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
uint16_t seg; \
\
fetch_ea_32(fetchdat); \
ILLEGAL_ON(mod == 3); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmeml(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
cpu_state.regs[reg].l = addr; \
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
return 0; \