From 52f5f43d82d85fc5f44d36c8bb47eec2e811b3d7 Mon Sep 17 00:00:00 2001 From: SarahW Date: Fri, 22 Mar 2019 20:31:29 +0000 Subject: [PATCH] Fix PC value following FSTCW/FSTSW. --- src/codegen_ops_fpu_misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/codegen_ops_fpu_misc.c b/src/codegen_ops_fpu_misc.c index 58902ac..2848ba9 100644 --- a/src/codegen_ops_fpu_misc.c +++ b/src/codegen_ops_fpu_misc.c @@ -69,7 +69,7 @@ uint32_t ropFSTCW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe codegen_check_seg_write(block, ir, target_seg); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_NPXC); - return op_pc; + return op_pc+1; } uint32_t ropFSTSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) { @@ -82,7 +82,7 @@ uint32_t ropFSTSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe codegen_check_seg_write(block, ir, target_seg); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_NPXS); - return op_pc; + return op_pc+1; } uint32_t ropFSTSW_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) {