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Video timing improvements :

Browse source 
- Separated read and write timings
- Added timings for onboard video chips
- Updated timings based on VIDSPEED testing
This commit is contained in:
SarahW 2018-01-31 21:09:11 +00:00
commit 475f51ba0f
5 changed files with 178 additions and 81 deletions
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48
src/vid_svga.c
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@ -773,8 +773,8 @@ void svga_write(uint32_t addr, uint8_t val, void *p)
egawrites++;
cycles -= video_timing_b;
cycles_lost += video_timing_b;
cycles -= video_timing_write_b;
cycles_lost += video_timing_write_b;
if (svga_output) pclog("Writeega %06X ",addr);
addr &= svga->banked_mask;
@ -959,8 +959,8 @@ uint8_t svga_read(uint32_t addr, void *p)
uint32_t latch_addr;
int readplane = svga->readplane;
cycles -= video_timing_b;
cycles_lost += video_timing_b;
cycles -= video_timing_read_b;
cycles_lost += video_timing_read_b;
egareads++;
// pclog("Readega %06X ",addr);
@ -1035,8 +1035,8 @@ void svga_write_linear(uint32_t addr, uint8_t val, void *p)
uint8_t vala, valb, valc, vald, wm = svga->writemask;
int writemask2 = svga->writemask;
cycles -= video_timing_b;
cycles_lost += video_timing_b;
cycles -= video_timing_write_b;
cycles_lost += video_timing_write_b;
egawrites++;
@ -1217,8 +1217,8 @@ uint8_t svga_read_linear(uint32_t addr, void *p)
uint8_t temp, temp2, temp3, temp4;
int readplane = svga->readplane;
cycles -= video_timing_b;
cycles_lost += video_timing_b;
cycles -= video_timing_read_b;
cycles_lost += video_timing_read_b;
egareads++;
@ -1311,8 +1311,8 @@ void svga_writew(uint32_t addr, uint16_t val, void *p)
egawrites += 2;
cycles -= video_timing_w;
cycles_lost += video_timing_w;
cycles -= video_timing_write_w;
cycles_lost += video_timing_write_w;
if (svga_output) pclog("svga_writew: %05X ", addr);
addr = (addr & svga->banked_mask) + svga->write_bank;
@ -1340,8 +1340,8 @@ void svga_writel(uint32_t addr, uint32_t val, void *p)
egawrites += 4;
cycles -= video_timing_l;
cycles_lost += video_timing_l;
cycles -= video_timing_write_l;
cycles_lost += video_timing_write_l;
if (svga_output) pclog("svga_writel: %05X ", addr);
addr = (addr & svga->banked_mask) + svga->write_bank;
@ -1364,8 +1364,8 @@ uint16_t svga_readw(uint32_t addr, void *p)
egareads += 2;
cycles -= video_timing_w;
cycles_lost += video_timing_w;
cycles -= video_timing_read_w;
cycles_lost += video_timing_read_w;
// pclog("Readw %05X ", addr);
addr = (addr & svga->banked_mask) + svga->read_bank;
@ -1386,8 +1386,8 @@ uint32_t svga_readl(uint32_t addr, void *p)
egareads += 4;
cycles -= video_timing_l;
cycles_lost += video_timing_l;
cycles -= video_timing_read_l;
cycles_lost += video_timing_read_l;
// pclog("Readl %05X ", addr);
addr = (addr & svga->banked_mask) + svga->read_bank;
@ -1412,8 +1412,8 @@ void svga_writew_linear(uint32_t addr, uint16_t val, void *p)
egawrites += 2;
cycles -= video_timing_w;
cycles_lost += video_timing_w;
cycles -= video_timing_write_w;
cycles_lost += video_timing_write_w;
if (svga_output) pclog("Write LFBw %08X %04X\n", addr, val);
addr &= svga->decode_mask;
@ -1439,8 +1439,8 @@ void svga_writel_linear(uint32_t addr, uint32_t val, void *p)
egawrites += 4;
cycles -= video_timing_l;
cycles_lost += video_timing_l;
cycles -= video_timing_write_l;
cycles_lost += video_timing_write_l;
if (svga_output) pclog("Write LFBl %08X %08X\n", addr, val);
addr &= svga->decode_mask;
@ -1460,8 +1460,8 @@ uint16_t svga_readw_linear(uint32_t addr, void *p)
egareads += 2;
cycles -= video_timing_w;
cycles_lost += video_timing_w;
cycles -= video_timing_read_w;
cycles_lost += video_timing_read_w;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
@ -1479,8 +1479,8 @@ uint32_t svga_readl_linear(uint32_t addr, void *p)
egareads += 4;
cycles -= video_timing_l;
cycles_lost += video_timing_l;
cycles -= video_timing_read_l;
cycles_lost += video_timing_read_l;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)