Remove unused and superfluous variables from mem.c.

src/808x.c

@@ -97,8 +97,6 @@ int noint=0;
 
 int output=0;
 
-int shadowbios=0;
-
 int ins=0;
 //#define readmemb(a) (((a)<0xA0000)?ram[a]:readmembl(a))
 

src/ali1429.c

@@ -55,8 +55,6 @@ void ali1429_write(uint16_t port, uint8_t val, void *priv)
                         ali1429_recalc();
                         break;
                         case 0x14:
-                        shadowbios = val & 1;
-                        shadowbios_write = val & 2;
                         ali1429_recalc();
                         break;
                 }

src/headland.c

@@ -20,9 +20,7 @@ void headland_write(uint16_t addr, uint8_t val, void *priv)
                 pclog("Headland write %02X %02X\n",headland_index,val);
                 if (headland_index == 0x82)
                 {
-                        shadowbios = val & 0x10;
+                        if (val & 0x10)
-                        shadowbios_write = !(val & 0x10);
-                        if (shadowbios)
                                 mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
                         else
                                 mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);

src/i430fx.c

@@ -65,7 +65,6 @@ void i430fx_write(int func, int addr, uint8_t val, void *priv)
                 if ((card_i430fx[0x59] ^ val) & 0xf0)
                 {
                         i430fx_map(0xf0000, 0x10000, val >> 4);
-                        shadowbios = (val & 0x10);
                 }
                 pclog("i430fx_write : PAM0 write %02X\n", val);
                 break;

src/i430lx.c

@@ -65,7 +65,6 @@ void i430lx_write(int func, int addr, uint8_t val, void *priv)
                 if ((card_i430lx[0x59] ^ val) & 0xf0)
                 {
                         i430lx_map(0xf0000, 0x10000, val >> 4);
-                        shadowbios = (val & 0x10);
                 }
                 pclog("i430lx_write : PAM0 write %02X\n", val);
                 break;

src/i430vx.c

@@ -64,7 +64,6 @@ void i430vx_write(int func, int addr, uint8_t val, void *priv)
                 if ((card_i430vx[0x59] ^ val) & 0xf0)
                 {
                         i430vx_map(0xf0000, 0x10000, val >> 4);
-                        shadowbios = (val & 0x10);
                 }
                 pclog("i430vx_write : PAM0 write %02X\n", val);
                 break;

src/ibm.h

@@ -36,13 +36,6 @@ extern int mmu_perm;
 #define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1))?readmemwl((s)+(a)):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
 #define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3))?readmemll((s)+(a)):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
 
-//#define writememb(a,v) if (writelookup2[(a)>>12]==0xFFFFFFFF) writemembl(a,v); else ram[writelookup2[(a)>>12]+((a)&0xFFF)]=v
-//#define writememw(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememwl(s,a,v); else *((uint16_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v
-//#define writememl(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememll(s,a,v); else *((uint32_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v
-//#define readmemb(a) ((isram[((a)>>16)&255] && !(cr0>>31))?ram[a&0xFFFFFF]:readmembl(a))
-//#define writememb(a,v) if (isram[((a)>>16)&255] && !(cr0>>31)) ram[a&0xFFFFFF]=v; else writemembl(a,v)
-
-//void writememb(uint32_t addr, uint8_t val);
 uint8_t readmembl(uint32_t addr);
 void writemembl(uint32_t addr, uint8_t val);
 uint16_t readmemwl(uint32_t addr);
@@ -69,7 +62,6 @@ uint32_t inl(uint16_t port);
 void outl(uint16_t port, uint32_t val);
 
 FILE *romfopen(char *fn, char *mode);
-extern int shadowbios,shadowbios_write;
 extern int mem_size;
 extern int readlnum,writelnum;
 

src/mcr.c

@@ -10,7 +10,6 @@ void resetmcr()
 {
         mcrlock=0;
         mcrfirst=1;
-        shadowbios=0;
 }
 
 void writemcr(uint16_t addr, uint8_t val)
@@ -29,7 +28,7 @@ void writemcr(uint16_t addr, uint8_t val)
 //                exit(-1);
                 break;
                 case 0x23:
-                if (nextreg6) shadowbios=!val;
+//                if (nextreg6) shadowbios=!val;
                 break;
         }
         mcr22=val;

src/mem.c

@@ -36,10 +36,6 @@ mem_mapping_t bios_mapping[8];
 mem_mapping_t bios_high_mapping[8];
 static mem_mapping_t romext_mapping;
 
-int shadowbios,shadowbios_write;
-
-unsigned char isram[0x10000];
-
 static uint8_t ff_array[0x1000];
 
 int mem_size;
@@ -50,7 +46,10 @@ int cachesize=256;
 uint8_t *ram, *rom = NULL;
 uint8_t romext[32768];
 
-//int abrt=0;
+uint32_t mem_logical_addr;
+
+int mmuflush=0;
+int mmu_perm=4;
 
 void resetreadlookup()
 {
@@ -68,9 +67,6 @@ void resetreadlookup()
 
 }
 
-int mmuflush=0;
-int mmu_perm=4;
-
 void flushmmucache()
 {
         int c;
@@ -202,15 +198,9 @@ void mem_flush_write_page(uint32_t addr, uint32_t virt)
         }
 }
 
-extern int output;
-
 #define mmutranslate_read(addr) mmutranslatereal(addr,0)
 #define mmutranslate_write(addr) mmutranslatereal(addr,1)
 
-int pctrans=0;
-
-extern uint32_t testr[9];
-
 static inline uint32_t mmu_readl(uint32_t addr)
 {
         return *(uint32_t *)&_mem_exec[addr >> 14][addr & 0x3fff];
@@ -423,16 +413,13 @@ void addwritelookup(uint32_t virt, uint32_t phys)
         cycles -= 9;
 }
 
-#undef printf
 uint8_t *getpccache(uint32_t a)
 {
         uint32_t a2=a;
 
         if (cr0>>31)
         {
-		pctrans=1;
                 a = mmutranslate_read(a);
-                pctrans=0;
 
                 if (a==0xFFFFFFFF) return ram;
         }
@@ -451,9 +438,7 @@ uint8_t *getpccache(uint32_t a)
         pclog("Bad getpccache %08X\n", a);
         return &ff_array[0-(uintptr_t)(a2 & ~0xFFF)];
 }
-#define printf pclog
 
-uint32_t mem_logical_addr;
 uint8_t readmembl(uint32_t addr)
 {
         mem_mapping_t *map;

src/mem.h

@@ -222,7 +222,5 @@ void mmu_invalidate(uint32_t addr);
 
 int loadbios();
 
-extern unsigned char isram[0x10000];
-
 extern int purgeable_page_count;
 #endif

src/opti495.c

@@ -27,15 +27,10 @@ static void opti495_write(uint16_t addr, uint8_t val, void *p)
                         }
                         if (optireg == 0x22)
                         {
-                                shadowbios = !(val & 0x80);
+                                if (!(val & 0x80))
-                                shadowbios_write = val & 0x80;
-                                //pclog("shadowbios %i %02x\n", shadowbios, val);
-                                if (shadowbios)
                                         mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
                                 else
                                         mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
-//                                if (shadowbios)
-//                                        fatal("Here\n");
                         }
                 }
                 break;

src/pc.c

@@ -360,7 +360,6 @@ void initpc(int argc, char *argv[])
         ali1429_reset();
 //        CPUID=(is486 && (cpuspeed==7 || cpuspeed>=9));
 //        pclog("Init - CPUID %i %i\n",CPUID,cpuspeed);
-        shadowbios=0;
 
 #if __unix
 	if (cdrom_drive == -1)
@@ -387,7 +386,6 @@ void resetpc()
 //        cpuspeed2=(AT)?2:1;
 //        atfullspeed=0;
 ///*        if (romset==ROM_AMI386 || romset==ROM_AMI486) */fullspeed();
-        shadowbios=0;
 }
 
 void resetpc_cad()
@@ -449,7 +447,6 @@ void resetpchard()
 //        atfullspeed = 0;
 //        setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
 
-        shadowbios = 0;
         ali1429_reset();
         
         keyboard_at_reset();

src/ps2_mca.c

@@ -404,10 +404,8 @@ static void model_55sx_write(uint16_t port, uint8_t val)
                 case 0x105:
                 pclog("Write POS3 %02x\n", val);
                 ps2.option[3] = val;
-                shadowbios = !(val & 0x10);
-                shadowbios_write = val & 0x10;
 
-                if (shadowbios)
+                if (!(val & 0x10))
                 {
                         mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
                         mem_mapping_disable(&ps2.shadow_mapping);

src/scat.c

@@ -564,8 +564,6 @@ void scat_init()
                 mem_mapping_disable(&scat_mapping[i]);
         }
 
-        for(i=4;i<10;i++) isram[i] = 0;
-
         // TODO - Only normal CPU accessing address FF0000 to FFFFFF mapped to ROM. Normal CPU accessing address FC0000 to FEFFFF map to ROM should be implemented later.
         for (i = 12; i < 16; i++)
         {

src/sis496.c

@@ -43,7 +43,6 @@ void sis496_recalcmapping(sis496_t *sis496)
         }
 
         flushmmucache();
-        shadowbios = (sis496->pci_conf[0x44] & 0xf0);
 }
 
 void sis496_write(int func, int addr, uint8_t val, void *p)

src/um8881f.c

@@ -33,8 +33,7 @@ void um8881f_write(int func, int addr, uint8_t val, void *priv)
                                 case 0x80: mem_bios_set_state(0xf0000, 0x10000, 1, 1); break;
                                 case 0xc0: mem_bios_set_state(0xf0000, 0x10000, 1, 0); break;
                         }*/
-                        shadowbios = val & 0x80;
+//                        shadowbios = val & 0x80;
-                        shadowbios_write = !(val & 0x40);
                         flushmmucache_nopc();
                 }
         }