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Cleaned up exec386_dynarec() a bit.

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This commit is contained in:
SarahW 2019-02-01 20:11:08 +00:00
commit 2ccf771cf3
1 changed files with 282 additions and 312 deletions
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42
src/386_dynarec.c
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@ -506,7 +506,7 @@ int dontprint=0;
#include "386_ops.h" #include "386_ops.h"
#define CACHE_ON() (!(cr0 & (1 << 30)) /*&& (cr0 & 1)*/ && !(cpu_state.flags & T_FLAG)) #define CACHE_ON() (!(cr0 & (1 << 30)) && !(cpu_state.flags & T_FLAG))
//#define CACHE_ON() 0 //#define CACHE_ON() 0
static int cycles_main = 0; static int cycles_main = 0;
@ -518,7 +518,7 @@ void exec386_dynarec(int cycs)
int cycdiff; int cycdiff;
int oldcyc; int oldcyc;
int cyc_period = cycs / 2000; /*5us*/ int cyc_period = cycs / 2000; /*5us*/
//output = 3;
cycles_main += cycs; cycles_main += cycs;
while (cycles_main > 0) while (cycles_main > 0)
{ {
@ -527,7 +527,6 @@ void exec386_dynarec(int cycs)
cycles += cyc_period; cycles += cyc_period;
cycles_start = cycles; cycles_start = cycles;
// output=3;
while (cycles>0) while (cycles>0)
{ {
oldcyc=cycles; oldcyc=cycles;
@ -546,8 +545,7 @@ void exec386_dynarec(int cycs)
cpu_state.ssegs = 0; cpu_state.ssegs = 0;
fetchdat = fastreadl(cs + cpu_state.pc); fetchdat = fastreadl(cs + cpu_state.pc);
// if (!fetchdat)
// fatal("Dead with cache off\n");
if (!cpu_state.abrt) if (!cpu_state.abrt)
{ {
trap = cpu_state.flags & T_FLAG; trap = cpu_state.flags & T_FLAG;
@ -564,12 +562,6 @@ void exec386_dynarec(int cycs)
if (((cs + cpu_state.pc) >> 12) != pccache) if (((cs + cpu_state.pc) >> 12) != pccache)
CPU_BLOCK_END(); CPU_BLOCK_END();
/* if (ssegs)
{
ds=oldds;
ss=oldss;
ssegs=0;
}*/
if (cpu_state.abrt) if (cpu_state.abrt)
CPU_BLOCK_END(); CPU_BLOCK_END();
if (trap) if (trap)
@ -579,11 +571,6 @@ void exec386_dynarec(int cycs)
ins++; ins++;
insc++; insc++;
/* if ((cs + pc) == 4)
fatal("4\n");*/
/* if (ins >= 141400000)
output = 3;*/
} }
} }
else else
@ -670,17 +657,13 @@ void exec386_dynarec(int cycs)
inrecomp=1; inrecomp=1;
code(); code();
inrecomp=0; inrecomp=0;
// cpu_recomp_ins += block->ins;
cpu_recomp_blocks++; cpu_recomp_blocks++;
/* ins += codeblock_ins[index];
insc += codeblock_ins[index];*/
/* pclog("Exit block now %04X:%04X\n", CS, pc);*/
} }
else if (valid_block && !cpu_state.abrt) else if (valid_block && !cpu_state.abrt)
{ {
uint32_t start_pc = cpu_state.pc; uint32_t start_pc = cpu_state.pc;
// pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]);
cpu_block_end = 0; cpu_block_end = 0;
x86_was_reset = 0; x86_was_reset = 0;
@ -699,10 +682,7 @@ inrecomp=0;
cpu_state.ssegs = 0; cpu_state.ssegs = 0;
fetchdat = fastreadl(cs + cpu_state.pc); fetchdat = fastreadl(cs + cpu_state.pc);
// if (fetchdat == 0xffffffff)
// fatal("Dead ffffffff\n");
// if (!fetchdat)
// fatal("Dead\n");
if (!cpu_state.abrt) if (!cpu_state.abrt)
{ {
trap = cpu_state.flags & T_FLAG; trap = cpu_state.flags & T_FLAG;
@ -752,19 +732,15 @@ inrecomp=0;
codegen_reset(); codegen_reset();
codegen_in_recompile = 0; codegen_in_recompile = 0;
// output &= ~2;
} }
else if (!cpu_state.abrt) else if (!cpu_state.abrt)
{ {
/*Mark block but do not recompile*/ /*Mark block but do not recompile*/
uint32_t start_pc = cpu_state.pc; uint32_t start_pc = cpu_state.pc;
// pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]);
cpu_block_end = 0; cpu_block_end = 0;
x86_was_reset = 0; x86_was_reset = 0;
// cpu_new_blocks++;
codegen_block_init(phys_addr); codegen_block_init(phys_addr);
// if (output) pclog("Recompile block at %04x:%04x %04x %04x %04x %04x %04x %04x ESP=%04x %04x %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]); // if (output) pclog("Recompile block at %04x:%04x %04x %04x %04x %04x %04x %04x ESP=%04x %04x %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]);
@ -824,21 +800,15 @@ inrecomp=0;
if (x86_was_reset) if (x86_was_reset)
codegen_reset(); codegen_reset();
// output &= ~2;
} }
else else
cpu_state.oldpc = cpu_state.pc; cpu_state.oldpc = cpu_state.pc;
// if (output && (SP & 1))
// fatal("odd SP\n");
} }
cycdiff=oldcyc-cycles; cycdiff=oldcyc-cycles;
tsc += cycdiff; tsc += cycdiff;
// timer_end_period(cycles);
if (cpu_state.abrt) if (cpu_state.abrt)
{ {
flags_rebuild(); flags_rebuild();
@ -865,7 +835,6 @@ inrecomp=0;
{ {
trap = 0; trap = 0;
flags_rebuild(); flags_rebuild();
// oldpc=pc;
if (msw&1) if (msw&1)
{ {
pmodeint(1,0); pmodeint(1,0);
@ -923,6 +892,7 @@ inrecomp=0;
} }
} }
} }
if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t)tsc)) if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t)tsc))
timer_process(); timer_process();
cycles_main -= (cycles_start - cycles); cycles_main -= (cycles_start - cycles);