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Implemented preliminary S3 ViRGE 2D blitter emulation.

Browse source 
Misc ViRGE fixes.
Changes to memory mapping.
Changes to PCI handling.
Disabled 'AMI WinBIOS 486 PCI' due to incomplete chipset emulation.
Invalid GUS register reads no longer kill the emulator.
This commit is contained in:
TomW 2014-03-20 14:03:55 +00:00
commit 2ca4ead570
49 changed files with 2078 additions and 700 deletions
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2
src/386.c
View file

@ -64,7 +64,7 @@ int cgate32;
uint32_t mmucache[0x100000];
uint8_t romext[32768];
uint8_t *ram,*rom,*vram,*vrom;
uint8_t *ram,*rom;
uint16_t biosmask;
uint32_t rmdat32;

6
src/808x.c
View file

@ -561,14 +561,8 @@ chdir(pcempath);
f=fopen("ram8.bin","wb");
fwrite(ram+0x3D210,0x200,1,f);
fclose(f); */
f=fopen("vram.dmp","wb");
fwrite(vram,0x400000,1,f);
fclose(f);
/* f=fopen("bios.dmp","wb");
fwrite(rom,0x20000,1,f);
fclose(f);
f=fopen("vbios.dmp","wb");
fwrite(vrom,0x8000,1,f);
fclose(f);*/
/* f=fopen("kernel.dmp","wb");
for (c=0;c<0x200000;c++) putc(readmemb(c+0xC0000000),f);

2
src/Makefile.mingw
View file

@ -4,7 +4,7 @@ CC = gcc.exe
WINDRES = windres.exe
CFLAGS = -O3 -march=i686 -fomit-frame-pointer
OBJ = 386.o 808x.o acer386sx.o ali1429.o amstrad.o cdrom-ioctl.o \
config.o cpu.o dac.o device.o dma.o ega.o fdc.o \
config.o cpu.o dac.o device.o dma.o fdc.o \
headland.o i430vx.o ide.o io.o jim.o keyboard.o keyboard_amstrad.o keyboard_at.o \
keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o lpt.o mcr.o mem.o model.o \
mouse.o mouse_ps2.o mouse_serial.o neat.o nvr.o olivetti_m24.o \

62
src/ali1429.c
View file

@ -9,9 +9,42 @@
static int ali1429_index;
static uint8_t ali1429_regs[256];
static void ali1429_recalc()
{
int c;
for (c = 0; c < 8; c++)
{
uint32_t base = 0xc0000 + (c << 15);
if (ali1429_regs[0x13] & (1 << c))
{
switch (ali1429_regs[0x14] & 3)
{
case 0:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
flushmmucache();
}
void ali1429_write(uint16_t port, uint8_t val, void *priv)
{
// return;
int c;
if (!(port & 1))
ali1429_index = val;
else
@ -21,35 +54,12 @@ void ali1429_write(uint16_t port, uint8_t val, void *priv)
switch (ali1429_index)
{
case 0x13:
if (!(val & 0xc0))
{
shadowbios = 0;
if (!shadowbios_write)
mem_bios_set_state(0xf0000, 0x10000, 0, 0);
else
mem_bios_set_state(0xf0000, 0x10000, 0, 1);
flushmmucache();
}
ali1429_recalc();
break;
case 0x14:
shadowbios = val & 1;
shadowbios_write = val & 2;
switch (val & 3)
{
case 0:
mem_bios_set_state(0xf0000, 0x10000, 0, 0);
break;
case 1:
mem_bios_set_state(0xf0000, 0x10000, 1, 0);
break;
case 2:
mem_bios_set_state(0xf0000, 0x10000, 0, 1);
break;
case 3:
mem_bios_set_state(0xf0000, 0x10000, 1, 1);
break;
}
flushmmucache();
ali1429_recalc();
break;
}
}

32
src/ega.c
View file

@ -1,32 +0,0 @@
#include "ibm.h"
#include "video.h"
void dumpegaregs()
{
/* int c;
printf("CRTC :");
for (c=0;c<0x20;c++) printf(" %02X",crtc[c]);
printf("\n");
printf(" EXT :");
for (c=0;c<0x20;c++) printf(" %02X",crtc[c+32]);
printf("\n");
printf(" EXT2:");
for (c=0;c<0x20;c++) printf(" %02X",crtc[c+64]);
printf("\n");
printf("SEQ :");
for (c=0;c<0x10;c++) printf(" %02X",seqregs[c]);
printf("\n");
printf(" EXT :");
for (c=0;c<0x10;c++) printf(" %02X",seqregs[c + 0x10]);
printf("\n");
printf("ATTR :");
for (c=0;c<0x20;c++) printf(" %02X",attrregs[c]);
printf("\n");
printf("GDC :");
for (c=0;c<0x10;c++) printf(" %02X",gdcreg[c]);
printf("\n");
// printf("OLD CTRL2 = %02X NEW CTRL2 = %02X DAC = %02X 3C2 = %02X\n",tridentoldctrl2,tridentnewctrl2,tridentdac,ega3c2);
printf("BPP = %02X\n",bpp);*/
}

4
src/headland.c
View file

@ -20,9 +20,9 @@ void headland_write(uint16_t addr, uint8_t val, void *priv)
shadowbios = val & 0x10;
shadowbios_write = !(val & 0x10);
if (shadowbios)
mem_bios_set_state(0xf0000, 0x10000, 1, 0);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_bios_set_state(0xf0000, 0x10000, 0, 1);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
}
}
else

52
src/i430vx.c
View file

@ -13,16 +13,22 @@ static void i430vx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3)
{
case 0x0: mem_bios_set_state(addr, size, 0, 0); break; /*DRAM disabled, accesses directed to PCI bus*/
case 0x1: mem_bios_set_state(addr, size, 1, 0); break; /*Read only, DRAM write protected, non-cacheable*/
case 0x2: mem_bios_set_state(addr, size, 0, 1); break; /*Write only*/
case 0x3: mem_bios_set_state(addr, size, 1, 1); break; /*Read/write, non-cacheable*/
/*Below are redundant*/
// case 0x5: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL ); break; /*Read only, DRAM write protected, cacheable*/
// case 0x7: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml); break; /*Read/write, non-cacheable*/
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
void i430vx_write(int func, int addr, uint8_t val, void *priv)
{
if (func)
@ -43,18 +49,42 @@ void i430vx_write(int func, int addr, uint8_t val, void *priv)
}
pclog("i430vx_write : PAM0 write %02X\n", val);
break;
case 0x5a: /*PAM1*/
if ((card_i430vx[0x5a] ^ val) & 0x0f)
i430vx_map(0xc0000, 0x04000, val & 0xf);
if ((card_i430vx[0x5a] ^ val) & 0xf0)
i430vx_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((card_i430vx[0x5b] ^ val) & 0x0f)
i430vx_map(0xc8000, 0x04000, val & 0xf);
if ((card_i430vx[0x5b] ^ val) & 0xf0)
i430vx_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((card_i430vx[0x5c] ^ val) & 0x0f)
i430vx_map(0xd0000, 0x04000, val & 0xf);
if ((card_i430vx[0x5c] ^ val) & 0xf0)
i430vx_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((card_i430vx[0x5d] ^ val) & 0x0f)
i430vx_map(0xd8000, 0x04000, val & 0xf);
if ((card_i430vx[0x5d] ^ val) & 0xf0)
i430vx_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((card_i430vx[0x5e] ^ val) & 0x0f)
i430vx_map(0xe0000, 0x04000, val & 0xf);
i430vx_map(0xe0000, 0x04000, val & 0xf);
if ((card_i430vx[0x5e] ^ val) & 0xf0)
i430vx_map(0xe4000, 0x04000, val >> 4);
i430vx_map(0xe4000, 0x04000, val >> 4);
pclog("i430vx_write : PAM5 write %02X\n", val);
break;
case 0x5f: /*PAM6*/
if ((card_i430vx[0x5f] ^ val) & 0x0f)
i430vx_map(0xe8000, 0x04000, val & 0xf);
i430vx_map(0xe8000, 0x04000, val & 0xf);
if ((card_i430vx[0x5f] ^ val) & 0xf0)
i430vx_map(0xec000, 0x04000, val >> 4);
i430vx_map(0xec000, 0x04000, val >> 4);
pclog("i430vx_write : PAM6 write %02X\n", val);
break;
}

510
src/mem.c
View file

@ -16,20 +16,25 @@
#include "cpu.h"
#include "rom.h"
static uint8_t (*_mem_read_b[0x40000])(uint32_t addr, void *priv);
static uint16_t (*_mem_read_w[0x40000])(uint32_t addr, void *priv);
static uint32_t (*_mem_read_l[0x40000])(uint32_t addr, void *priv);
static void (*_mem_write_b[0x40000])(uint32_t addr, uint8_t val, void *priv);
static void (*_mem_write_w[0x40000])(uint32_t addr, uint16_t val, void *priv);
static void (*_mem_write_l[0x40000])(uint32_t addr, uint32_t val, void *priv);
static void *_mem_priv[0x40000];
static mem_mapping_t *_mem_mapping[0x40000];
static uint8_t (*_mem_read_b[0x40000])(uint32_t addr, void *priv);
static uint16_t (*_mem_read_w[0x40000])(uint32_t addr, void *priv);
static uint32_t (*_mem_read_l[0x40000])(uint32_t addr, void *priv);
static void (*_mem_write_b[0x40000])(uint32_t addr, uint8_t val, void *priv);
static void (*_mem_write_w[0x40000])(uint32_t addr, uint16_t val, void *priv);
static void (*_mem_write_l[0x40000])(uint32_t addr, uint32_t val, void *priv);
static uint8_t *_mem_exec[0x40000];
static void *_mem_priv_r[0x40000];
static void *_mem_priv_w[0x40000];
static mem_mapping_t *_mem_mapping_r[0x40000];
static mem_mapping_t *_mem_mapping_w[0x40000];
static int _mem_state[0x40000];
static mem_mapping_t base_mapping;
static mem_mapping_t ram_low_mapping;
static mem_mapping_t ram_high_mapping;
static mem_mapping_t ram_mid_mapping;
static mem_mapping_t bios_mapping[8];
static mem_mapping_t vrom_mapping;
static mem_mapping_t bios_high_mapping[8];
static mem_mapping_t romext_mapping;
int shadowbios,shadowbios_write;
@ -42,7 +47,7 @@ uint32_t biosmask;
int readlnum=0,writelnum=0;
int cachesize=256;
uint8_t *ram,*rom,*vram,*vrom;
uint8_t *ram,*rom,*vram;
uint8_t romext[32768];
static void mem_load_xtide_bios()
@ -71,179 +76,6 @@ static void mem_load_atide_bios()
}
}
int mem_load_video_bios()
{
FILE *f = NULL;
int c;
switch (gfxcard)
{
case GFX_EGA:
f=romfopen("roms/ibm_6277356_ega_card_u44_27128.bin","rb");
if (f)
{
pclog("Read EGA ROM!\n");
fread(vrom,16384,1,f);
if (vrom[0x3FFE]==0xAA && vrom[0x3FFF]==0x55)
{
pclog("Read EGA ROM in reverse\n");
fseek(f,0,SEEK_SET);
for (c=0x3FFF;c>=0;c--)
vrom[c]=getc(f);
}
fclose(f);
return 1;
}
break;
case GFX_TVGA:
f=romfopen("roms/trident.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_ET4000:
f=romfopen("roms/et4000.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_ET4000W32:
f=romfopen("roms/et4000w32.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_BAHAMAS64:
f=romfopen("roms/bahamas64.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_N9_9FX:
f=romfopen("roms/s3_764.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_STEALTH64:
f=romfopen("roms/TRIO64 (Ver. 1.5-07) [VGA] (S3 Incorporated).bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_VIRGE:
f=romfopen("roms/s3virge.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_TGUI9440:
f=romfopen("roms/9440.vbi","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_VGA:
f=romfopen("roms/ibm_vga.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_VGAEDGE16:
f=romfopen("roms/vgaedge16.vbi","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_VGACHARGER:
f=romfopen("roms/bios.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_OTI067:
f=romfopen("roms/oti067/bios.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_MACH64GX:
f=romfopen("roms/mach64gx/bios.bin","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
case GFX_CL_GD5429:
f=romfopen("roms/5429.vbi","rb");
if (f)
{
fread(vrom,32768,1,f);
fclose(f);
return 1;
}
break;
default:
memset(vrom,0x63,0x8000);
return 1;
}
pclog("mem_load_video_bios : failed to load video BIOS for gfxcard %i\n", gfxcard);
memset(vrom,0x63,0x8000);
return 0;
}
int loadbios()
{
FILE *f=NULL,*ff=NULL;
@ -270,7 +102,6 @@ int loadbios()
}
fclose(ff);
fclose(f);
memset(vrom,0x63,0x8000);
mem_load_xtide_bios();
loadfont("roms/pc1512/40078.ic127", 2);
return 1;
@ -287,7 +118,6 @@ int loadbios()
fclose(f);
f=romfopen("roms/pc1640/40100","rb");
if (!f) break;
fread(vrom,0x8000,1,f);
fclose(f);
mem_load_xtide_bios();
return 1;
@ -302,7 +132,6 @@ int loadbios()
}
fclose(ff);
fclose(f);
memset(vrom,0x63,0x8000);
mem_load_xtide_bios();
loadfont("roms/pc200/40109.bin", 1);
return 1;
@ -311,7 +140,6 @@ int loadbios()
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
memset(vrom,0x63,0x8000);
mem_load_xtide_bios();
return 1;
/* case ROM_IBMPCJR:
@ -350,7 +178,6 @@ int loadbios()
if (!f) break;
fread(rom, 0x10000, 1, f);
fclose(f);
memset(vrom,0x63,0x8000);
return 1;
case ROM_GENXT:
@ -396,11 +223,8 @@ int loadbios()
fclose(f);
f = romfopen("roms/pc2086/40186.ic171", "rb");
if (!f) break;
pclog("Loading VBIOS\n");
fread(vrom, 32768, 1, f);
fclose(f);
mem_load_xtide_bios();
pclog("%02X %02X %02X\n", rom[0xfff0], rom[0xfff1], rom[0xfff2]);
biosmask = 0x3fff;
return 1;
@ -411,11 +235,8 @@ int loadbios()
fclose(f);
f = romfopen("roms/pc3086/c000.bin", "rb");
if (!f) break;
pclog("Loading VBIOS\n");
fread(vrom, 32768, 1, f);
fclose(f);
mem_load_xtide_bios();
pclog("%02X %02X %02X\n", rom[0xfff0], rom[0xfff1], rom[0xfff2]);
biosmask = 0x3fff;
return 1;
@ -488,9 +309,7 @@ int loadbios()
rom[0x40d4]=0x51; /*PUSH CX*/
f=romfopen("roms/acer386/oti067.bin","rb");
if (!f) break;
fread(vrom,0x8000,1,f);
fclose(f);
vrom[0x5D]=0x74;
return 1;
case ROM_AMI286:
@ -536,15 +355,9 @@ int loadbios()
return 1;
case ROM_MEGAPC:
pclog("Loading MegaPC\n");
f = romfopen("roms/megapc/41651-bios lo.u18", "rb");
ff = romfopen("roms/megapc/211253-bios hi.u19", "rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x8000; c+=2)
{
vrom[c]=getc(f);
vrom[c+1]=getc(ff);
}
fseek(f, 0x8000, SEEK_SET);
fseek(ff, 0x8000, SEEK_SET);
for (c = 0x0000; c < 0x10000; c+=2)
@ -567,7 +380,6 @@ int loadbios()
case ROM_WIN486:
// f=romfopen("roms/win486/win486.bin","rb");
f=romfopen("roms/win486/ALI1429G.AMW","rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
@ -589,6 +401,7 @@ int loadbios()
fread(rom, 0x20000, 1, f);
fclose(f);
biosmask = 0x1ffff;
pclog("Load SIS496 %x %x\n", rom[0x1fff0], rom[0xfff0]);
return 1;
case ROM_430VX:
@ -970,10 +783,17 @@ pctrans=1;
addreadlookup(a2,a);
// if (a > 0xc0000000)
// printf("%016X %016X %016X\n", ((long)a&0xFFFFF000), ((long)a2&~0xFFF), (uint8_t *)(a&0xFFFFF000) - (uint8_t *)(a2&~0xFFF));
// pclog("getpccache: virt=%08x phys=%08x RAM\n", a2, a);
return &ram[(uint8_t *)(a&0xFFFFF000) - (uint8_t *)(a2&~0xFFF)];
}
// if (logit) printf("PCCACHE - %08X -> %08X\n",a2,a);
switch (a>>16)
if (_mem_exec[a >> 14])
{
// pclog("getpccache: %p %p %p\n", ram, rom, &_mem_exec[a >> 14][(a & 0x3000) - (a2 & ~0xFFF)]);
// pclog("getpccache: virt=%08x phys=%08x %08x %08x %08x %08x\n", a2, a, _mem_exec[a >> 14], &_mem_exec[a >> 14][(a & 0x3000) - (a2 & ~0xFFF)], &_mem_exec[a >> 14][(a & 0x3000) - (a2 & ~0xFFF)] + 0xf0000, rom);
return &_mem_exec[a >> 14][(a & 0x3000) - (a2 & ~0xFFF)];
}
/* switch (a>>16)
{
case 0xC: if (a&0x8000) return &romext[(uint8_t *)(a&0x7000) - (uint8_t *)(a2&~0xFFF)];
return &vrom[(uint8_t *)(a&0x7000) - (uint8_t *)(a2&~0xFFF)];
@ -982,7 +802,8 @@ pctrans=1;
case 0xF: if (shadowbios) return &ram[(uint8_t *)(a&0xFFF000) - (uint8_t *)(a2&~0xFFF)];
return &rom[(uint8_t *)((a & biosmask) & ~ 0xfff) - (uint8_t *)(a2 & ~0xFFF)];
}
return &rom[(long)(a&0xF000) - (long)(a2&~0xFFF)];
return &rom[(long)(a&0xF000) - (long)(a2&~0xFFF)];*/
fatal("Bad getpccache %08X\n", a);
/*printf("Bad getpccache %08X\n",a);
dumpregs();
exit(-1);*/
@ -1000,7 +821,7 @@ uint8_t readmembl(uint32_t addr)
}
addr &= rammask;
if (_mem_read_b[addr >> 14]) return _mem_read_b[addr >> 14](addr, _mem_priv[addr >> 14]);
if (_mem_read_b[addr >> 14]) return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]);
// pclog("Bad readmembl %08X %04X:%08X\n", addr, CS, pc);
return 0xFF;
}
@ -1016,8 +837,8 @@ void writemembl(uint32_t addr, uint8_t val)
}
addr &= rammask;
if (_mem_write_b[addr >> 14]) _mem_write_b[addr >> 14](addr, val, _mem_priv[addr >> 14]);
// else pclog("Bad write %08X %02X %04X:%08X\n", addr, val, CS, pc);
if (_mem_write_b[addr >> 14]) _mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
// else pclog("Bad writemembl %08X %02X %04X:%08X\n", addr, val, CS, pc);
}
uint8_t readmemb386l(uint32_t seg, uint32_t addr)
@ -1042,7 +863,7 @@ uint8_t readmemb386l(uint32_t seg, uint32_t addr)
addr &= rammask;
if (_mem_read_b[addr >> 14]) return _mem_read_b[addr >> 14](addr, _mem_priv[addr >> 14]);
if (_mem_read_b[addr >> 14]) return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]);
// pclog("Bad readmemb386l %08X %04X:%08X\n", addr, CS, pc);
return 0xFF;
}
@ -1068,8 +889,8 @@ void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
/* if (addr >= 0xa0000 && addr < 0xc0000)
pclog("writemembl %08X %02X\n", addr, val);*/
if (_mem_write_b[addr >> 14]) _mem_write_b[addr >> 14](addr, val, _mem_priv[addr >> 14]);
// else pclog("Bad write %08X %02X %04X:%08X\n", addr, val, CS, pc);
if (_mem_write_b[addr >> 14]) _mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
// else pclog("Bad writememb386l %08X %02X %04X:%08X\n", addr, val, CS, pc);
}
uint16_t readmemwl(uint32_t seg, uint32_t addr)
@ -1099,13 +920,14 @@ uint16_t readmemwl(uint32_t seg, uint32_t addr)
addr2 &= rammask;
if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv[addr2 >> 14]);
if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]);
if (_mem_read_b[addr2 >> 14])
{
if (AT) return _mem_read_b[addr2 >> 14](addr2, _mem_priv[addr2 >> 14]) | (_mem_read_b[(addr2 + 1) >> 14](addr2 + 1, _mem_priv[addr2 >> 14]) << 8);
else return _mem_read_b[addr2 >> 14](addr2, _mem_priv[addr2 >> 14]) | (_mem_read_b[(seg + ((addr + 1) & 0xffff)) >> 14](seg + ((addr + 1) & 0xffff), _mem_priv[addr2 >> 14]) << 8);
if (AT) return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[(addr2 + 1) >> 14](addr2 + 1, _mem_priv_r[addr2 >> 14]) << 8);
else return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[(seg + ((addr + 1) & 0xffff)) >> 14](seg + ((addr + 1) & 0xffff), _mem_priv_r[addr2 >> 14]) << 8);
}
// pclog("Bad readmemwl %08X\n", addr2);
return 0xffff;
}
@ -1151,17 +973,17 @@ void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
if (_mem_write_w[addr2 >> 14])
{
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv[addr2 >> 14]);
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
return;
}
if (_mem_write_b[addr2 >> 14])
{
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv[addr2 >> 14]);
_mem_write_b[(addr2 + 1) >> 14](addr2 + 1, val >> 8, _mem_priv[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
_mem_write_b[(addr2 + 1) >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
return;
}
// pclog("Bad write %08X %04X\n", addr2, val);
// pclog("Bad writememwl %08X %04X\n", addr2, val);
}
uint32_t readmemll(uint32_t seg, uint32_t addr)
@ -1192,12 +1014,13 @@ uint32_t readmemll(uint32_t seg, uint32_t addr)
addr2&=rammask;
if (_mem_read_l[addr2 >> 14]) return _mem_read_l[addr2 >> 14](addr2, _mem_priv[addr2 >> 14]);
if (_mem_read_l[addr2 >> 14]) return _mem_read_l[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]);
if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv[addr2 >> 14]) | (_mem_read_w[addr2 >> 14](addr2 + 2, _mem_priv[addr2 >> 14]) << 16);
if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_w[addr2 >> 14](addr2 + 2, _mem_priv_r[addr2 >> 14]) << 16);
if (_mem_read_b[addr2 >> 14]) return _mem_read_b[addr2 >> 14](addr2, _mem_priv[addr2 >> 14]) | (_mem_read_b[addr2 >> 14](addr2 + 1, _mem_priv[addr2 >> 14]) << 8) | (_mem_read_b[addr2 >> 14](addr2 + 2, _mem_priv[addr2 >> 14]) << 16) | (_mem_read_b[addr2 >> 14](addr2 + 3, _mem_priv[addr2 >> 14]) << 24);
if (_mem_read_b[addr2 >> 14]) return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[addr2 >> 14](addr2 + 1, _mem_priv_r[addr2 >> 14]) << 8) | (_mem_read_b[addr2 >> 14](addr2 + 2, _mem_priv_r[addr2 >> 14]) << 16) | (_mem_read_b[addr2 >> 14](addr2 + 3, _mem_priv_r[addr2 >> 14]) << 24);
// pclog("Bad readmemll %08X\n", addr2);
return 0xffffffff;
}
@ -1235,24 +1058,24 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val)
if (_mem_write_l[addr2 >> 14])
{
_mem_write_l[addr2 >> 14](addr2, val, _mem_priv[addr2 >> 14]);
_mem_write_l[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
return;
}
if (_mem_write_w[addr2 >> 14])
{
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv[addr2 >> 14]);
_mem_write_w[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv[addr2 >> 14]);
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
_mem_write_w[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
return;
}
if (_mem_write_b[addr2 >> 14])
{
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2 + 1, val >> 8, _mem_priv[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2 + 3, val >> 24, _mem_priv[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
_mem_write_b[addr2 >> 14](addr2 + 3, val >> 24, _mem_priv_w[addr2 >> 14]);
return;
}
// pclog("Bad write %08X %08X\n", addr2, val);
// pclog("Bad writememll %08X %08X\n", addr2, val);
}
uint8_t mem_readb_phys(uint32_t addr)
@ -1260,7 +1083,7 @@ uint8_t mem_readb_phys(uint32_t addr)
mem_logical_addr = 0xffffffff;
if (_mem_read_b[addr >> 14])
return _mem_read_b[addr >> 14](addr, _mem_priv[addr >> 14]);
return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]);
return 0xff;
}
@ -1270,24 +1093,24 @@ void mem_writeb_phys(uint32_t addr, uint8_t val)
mem_logical_addr = 0xffffffff;
if (_mem_write_b[addr >> 14])
_mem_write_b[addr >> 14](addr, val, _mem_priv[addr >> 14]);
_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
}
uint8_t mem_read_ram(uint32_t addr, void *priv)
{
// if (addr >= 0xe0000 && addr < 0x100000) pclog("Read RAMb %08X\n", addr);
// if (addr >= 0xc0000 && addr < 0x0c8000) pclog("Read RAMb %08X\n", addr);
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
uint16_t mem_read_ramw(uint32_t addr, void *priv)
{
// if (addr >= 0xe0000 && addr < 0x100000) pclog("Read RAMw %08X\n", addr);
// if (addr >= 0xc0000 && addr < 0x0c8000) pclog("Read RAMw %08X\n", addr);
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *)&ram[addr];
}
uint32_t mem_read_raml(uint32_t addr, void *priv)
{
// if (addr >= 0xe0000 && addr < 0x100000) pclog("Read RAMl %08X\n", addr);
// if (addr >= 0xc0000 && addr < 0x0c8000) pclog("Read RAMl %08X\n", addr);
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *)&ram[addr];
}
@ -1296,19 +1119,19 @@ void mem_write_ram(uint32_t addr, uint8_t val, void *priv)
{
addwritelookup(mem_logical_addr, addr);
ram[addr] = val;
// if (addr >= 0xe0000 && addr < 0x100000) pclog("Write RAMb %08X\n", addr);
// if (addr >= 0xc0000 && addr < 0x0c8000) pclog("Write RAMb %08X\n", addr);
}
void mem_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
addwritelookup(mem_logical_addr, addr);
*(uint16_t *)&ram[addr] = val;
// if (addr >= 0xe0000 && addr < 0x100000) pclog("Write RAMw %08X %04X:%04X %i %04X %04X:%04X %04X:%04X\n", addr, CS, pc, ins, val, DS,SI, ES,DI);
// if (addr >= 0xc0000 && addr < 0x0c8000) pclog("Write RAMw %08X %04X:%04X %i %04X %04X:%04X %04X:%04X\n", addr, CS, pc, ins, val, DS,SI, ES,DI);
}
void mem_write_raml(uint32_t addr, uint32_t val, void *priv)
{
addwritelookup(mem_logical_addr, addr);
*(uint32_t *)&ram[addr] = val;
// if (addr >= 0xe0000 && addr < 0x100000) pclog("Write RAMl %08X %04X:%04X %04X:%04X %04X:%04X\n", addr, CS, pc, DS,SI, ES,DI);
// if (addr >= 0xc0000 && addr < 0x0c8000) pclog("Write RAMl %08X %04X:%04X %04X:%04X %04X:%04X\n", addr, CS, pc, DS,SI, ES,DI);
}
uint8_t mem_read_bios(uint32_t addr, void *priv)
@ -1333,19 +1156,6 @@ uint32_t mem_read_biosl(uint32_t addr, void *priv)
return *(uint32_t *)&rom[addr & biosmask];
}
uint8_t mem_read_vrom(uint32_t addr, void *priv)
{
return vrom[addr & 0x7fff];
}
uint16_t mem_read_vromw(uint32_t addr, void *priv)
{
return *(uint16_t *)&vrom[addr & 0x7fff];
}
uint32_t mem_read_vroml(uint32_t addr, void *priv)
{
return *(uint32_t *)&vrom[addr & 0x7fff];
}
uint8_t mem_read_romext(uint32_t addr, void *priv)
{
return romext[addr & 0x7fff];
@ -1359,6 +1169,15 @@ uint32_t mem_read_romextl(uint32_t addr, void *priv)
return *(uint32_t *)&romext[addr & 0x7fff];
}
void mem_write_null(uint32_t addr, uint8_t val, void *p)
{
}
void mem_write_nullw(uint32_t addr, uint16_t val, void *p)
{
}
void mem_write_nulll(uint32_t addr, uint32_t val, void *p)
{
}
void mem_updatecache()
{
@ -1383,50 +1202,88 @@ void mem_updatecache()
}
}
static void mem_mapping_recalc(uint32_t base, uint32_t size)
static inline int mem_mapping_read_allowed(uint32_t flags, int state)
{
uint32_t c;
// pclog("mem_mapping_read_allowed: flags=%x state=%x\n", flags, state);
switch (state & MEM_READ_MASK)
{
case MEM_READ_ANY:
return 1;
case MEM_READ_EXTERNAL:
return !(flags & MEM_MAPPING_INTERNAL);
case MEM_READ_INTERNAL:
return !(flags & MEM_MAPPING_EXTERNAL);
default:
fatal("mem_mapping_read_allowed : bad state %x\n", state);
}
}
static inline int mem_mapping_write_allowed(uint32_t flags, int state)
{
switch (state & MEM_WRITE_MASK)
{
case MEM_WRITE_DISABLED:
return 0;
case MEM_WRITE_ANY:
return 1;
case MEM_WRITE_EXTERNAL:
return !(flags & MEM_MAPPING_INTERNAL);
case MEM_WRITE_INTERNAL:
return !(flags & MEM_MAPPING_EXTERNAL);
default:
fatal("mem_mapping_write_allowed : bad state %x\n", state);
}
}
static void mem_mapping_recalc(uint64_t base, uint64_t size)
{
uint64_t c;
mem_mapping_t *mapping = base_mapping.next;
if ((base + size) > 0xffff8000)
size = 0xffff0000 - base;
/*Clear out old mappings*/
for (c = base; c < base + size; c += 0x4000)
{
_mem_read_b[c >> 14] = NULL;
_mem_read_w[c >> 14] = NULL;
_mem_read_l[c >> 14] = NULL;
_mem_priv_r[c >> 14] = NULL;
_mem_mapping_r[c >> 14] = NULL;
_mem_write_b[c >> 14] = NULL;
_mem_write_w[c >> 14] = NULL;
_mem_write_l[c >> 14] = NULL;
_mem_priv[c >> 14] = NULL;
_mem_mapping[c >> 14] = NULL;
_mem_priv_w[c >> 14] = NULL;
_mem_mapping_w[c >> 14] = NULL;
}
// pclog("mem_mapping_recalc %08X %08X\n", base, size);
/*Walk mapping list*/
while (mapping != NULL)
{
// pclog("mapping=%p next=%p base=%08X size=%08X enable=%i\n", mapping, mapping->next, mapping->base, mapping->size, mapping->enable);
/*In range?*/
if (mapping->enable && mapping->base < (base + size) && (mapping->base + mapping->size) >= base)
if (mapping->enable && (uint64_t)mapping->base < ((uint64_t)base + (uint64_t)size) && ((uint64_t)mapping->base + (uint64_t)mapping->size) > (uint64_t)base)
{
uint32_t start = (mapping->base < base) ? mapping->base : base;
uint32_t end = ((mapping->base + mapping->size) < (base + size)) ? (mapping->base + mapping->size) : (base + size);
uint64_t start = (mapping->base < base) ? mapping->base : base;
uint64_t end = (((uint64_t)mapping->base + (uint64_t)mapping->size) < (base + size)) ? ((uint64_t)mapping->base + (uint64_t)mapping->size) : (base + size);
for (c = start; c < end; c += 0x4000)
{
if (_mem_mapping[c >> 14] == NULL)
if ((mapping->read_b || mapping->read_w || mapping->read_l) &&
mem_mapping_read_allowed(mapping->flags, _mem_state[c >> 14]))
{
// pclog(" Add %08X\n", c);
_mem_read_b[c >> 14] = mapping->read_b;
_mem_read_w[c >> 14] = mapping->read_w;
_mem_read_l[c >> 14] = mapping->read_l;
_mem_exec[c >> 14] = mapping->exec + (c - mapping->base);
_mem_priv_r[c >> 14] = mapping->p;
_mem_mapping_r[c >> 14] = mapping;
}
if ((mapping->write_b || mapping->write_w || mapping->write_l) &&
mem_mapping_write_allowed(mapping->flags, _mem_state[c >> 14]))
{
_mem_write_b[c >> 14] = mapping->write_b;
_mem_write_w[c >> 14] = mapping->write_w;
_mem_write_l[c >> 14] = mapping->write_l;
_mem_priv[c >> 14] = mapping->p;
_mem_mapping[c >> 14] = mapping;
_mem_priv_w[c >> 14] = mapping->p;
_mem_mapping_w[c >> 14] = mapping;
}
}
}
@ -1443,6 +1300,8 @@ void mem_mapping_add(mem_mapping_t *mapping,
void (*write_b)(uint32_t addr, uint8_t val, void *p),
void (*write_w)(uint32_t addr, uint16_t val, void *p),
void (*write_l)(uint32_t addr, uint32_t val, void *p),
uint8_t *exec,
uint32_t flags,
void *p)
{
mem_mapping_t *dest = &base_mapping;
@ -1464,6 +1323,8 @@ void mem_mapping_add(mem_mapping_t *mapping,
mapping->write_b = write_b;
mapping->write_w = write_w;
mapping->write_l = write_l;
mapping->exec = exec;
mapping->flags = flags;
mapping->p = p;
mapping->next = NULL;
@ -1502,6 +1363,13 @@ void mem_mapping_set_addr(mem_mapping_t *mapping, uint32_t base, uint32_t size)
mem_mapping_recalc(mapping->base, mapping->size);
}
void mem_mapping_set_exec(mem_mapping_t *mapping, uint8_t *exec)
{
mapping->exec = exec;
mem_mapping_recalc(mapping->base, mapping->size);
}
void mem_mapping_set_p(mem_mapping_t *mapping, void *p)
{
mapping->p = p;
@ -1521,6 +1389,38 @@ void mem_mapping_enable(mem_mapping_t *mapping)
mem_mapping_recalc(mapping->base, mapping->size);
}
void mem_set_mem_state(uint32_t base, uint32_t size, int state)
{
uint32_t c;
// pclog("mem_set_pci_enable: base=%08x size=%08x\n", base, size);
for (c = 0; c < size; c += 0x4000)
_mem_state[(c + base) >> 14] = state;
mem_mapping_recalc(base, size);
}
void mem_add_bios()
{
mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom, MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x4000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x8000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0xc000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x10000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x14000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x18000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x1c000 & biosmask), MEM_MAPPING_EXTERNAL, 0);
mem_mapping_add(&bios_high_mapping[0], 0xfffe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom, 0, 0);
mem_mapping_add(&bios_high_mapping[1], 0xfffe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x4000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[2], 0xfffe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x8000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[3], 0xfffec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0xc000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[4], 0xffff0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x10000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[5], 0xffff4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x14000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[6], 0xffff8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x18000 & biosmask), 0, 0);
mem_mapping_add(&bios_high_mapping[7], 0xffffc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (0x1c000 & biosmask), 0, 0);
}
void mem_init()
{
int c;
@ -1528,7 +1428,6 @@ void mem_init()
ram = malloc(mem_size * 1024 * 1024);
rom = malloc(0x20000);
vram = malloc(0x800000);
vrom = malloc(0x8000);
readlookup2 = malloc(1024 * 1024 * 4);
writelookup2 = malloc(1024 * 1024 * 4);
cachelookup2 = malloc(1024 * 1024);
@ -1553,21 +1452,16 @@ void mem_init()
memset(&base_mapping, 0, sizeof(base_mapping));
mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
memset(_mem_state, 0, sizeof(_mem_state));
mem_set_mem_state(0xc0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram, 0, NULL);
if (mem_size > 1)
mem_mapping_add(&ram_low_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&ram_high_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0x100000, 0, NULL);
mem_mapping_add(&ram_mid_mapping, 0xc0000, 0x40000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0xc0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&vrom_mapping, 0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL);
mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL);
mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, romext, 0, NULL);
// pclog("Mem resize %i %i\n",mem_size,c);
}
@ -1595,57 +1489,23 @@ void mem_resize()
memset(_mem_write_l, 0, sizeof(_mem_write_l));
memset(&base_mapping, 0, sizeof(base_mapping));
memset(_mem_state, 0, sizeof(_mem_state));
mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_set_mem_state(0xc0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram, 0, NULL);
if (mem_size > 1)
mem_mapping_add(&ram_low_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL);
mem_mapping_add(&ram_high_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0x100000, 0, NULL);
mem_mapping_add(&ram_mid_mapping, 0xc0000, 0x40000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0xc0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_add(&vrom_mapping, 0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL);
mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL);
mem_add_bios();
mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, romext, 0, NULL);
// pclog("Mem resize %i %i\n",mem_size,c);
}
void mem_bios_set_state(uint32_t base, uint32_t size, int read_ram, int write_ram)
{
uint32_t c;
int state = (read_ram ? 1 : 0) | (write_ram ? 2: 0);
if (base < 0xe0000 || base > 0xfffff)
return;
if ((base + size) > 0x100000)
size = 0x100000 - base;
for (c = base; c < (base + size); c+= 0x4000)
{
// pclog("mem_bios_set_state: c=%08X base=%08X size=%08X bios=%i\n", c, base, size, (c - 0xe0000) >> 14);
switch (state)
{
case 0:
mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL);
break;
case 1:
mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL);
break;
case 2:
mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml);
break;
case 3:
mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml);
break;
}
}
}
int mem_a20_key = 0, mem_a20_alt = 0;
static int mem_a20_state = 0;

33
src/mem.h
View file

@ -14,10 +14,19 @@ typedef struct mem_mapping_t
void (*write_w)(uint32_t addr, uint16_t val, void *priv);
void (*write_l)(uint32_t addr, uint32_t val, void *priv);
uint8_t *exec;
uint32_t flags;
void *p;
} mem_mapping_t;
extern uint8_t *ram,*rom,*vram,*vrom;
/*Only present on external bus (ISA/PCI)*/
#define MEM_MAPPING_EXTERNAL 1
/*Only present on internal bus (RAM)*/
#define MEM_MAPPING_INTERNAL 2
extern uint8_t *ram,*rom;
extern uint8_t romext[32768];
extern int readlnum,writelnum;
extern int memspeed[11];
@ -34,6 +43,8 @@ void mem_mapping_add(mem_mapping_t *mapping,
void (*write_b)(uint32_t addr, uint8_t val, void *p),
void (*write_w)(uint32_t addr, uint16_t val, void *p),
void (*write_l)(uint32_t addr, uint32_t val, void *p),
uint8_t *exec,
uint32_t flags,
void *p);
void mem_mapping_set_handler(mem_mapping_t *mapping,
uint8_t (*read_b)(uint32_t addr, void *p),
@ -44,10 +55,22 @@ void mem_mapping_set_handler(mem_mapping_t *mapping,
void (*write_l)(uint32_t addr, uint32_t val, void *p));
void mem_mapping_set_p(mem_mapping_t *mapping, void *p);
void mem_mapping_set_addr(mem_mapping_t *mapping, uint32_t base, uint32_t size);
void mem_mapping_set_exec(mem_mapping_t *mapping, uint8_t *exec);
void mem_mapping_disable(mem_mapping_t *mapping);
void mem_mapping_enable(mem_mapping_t *mapping);
void mem_bios_set_state(uint32_t base, uint32_t size, int read_ram, int write_ram);
void mem_set_mem_state(uint32_t base, uint32_t size, int state);
#define MEM_READ_ANY 0x00
#define MEM_READ_INTERNAL 0x10
#define MEM_READ_EXTERNAL 0x20
#define MEM_READ_MASK 0xf0
#define MEM_WRITE_ANY 0x00
#define MEM_WRITE_INTERNAL 0x01
#define MEM_WRITE_EXTERNAL 0x02
#define MEM_WRITE_DISABLED 0x03
#define MEM_WRITE_MASK 0x0f
extern int mem_a20_alt;
extern int mem_a20_key;
@ -68,6 +91,8 @@ uint8_t mem_read_bios(uint32_t addr, void *priv);
uint16_t mem_read_biosw(uint32_t addr, void *priv);
uint32_t mem_read_biosl(uint32_t addr, void *priv);
FILE *romfopen(char *fn, char *mode);
void mem_write_null(uint32_t addr, uint8_t val, void *p);
void mem_write_nullw(uint32_t addr, uint16_t val, void *p);
void mem_write_nulll(uint32_t addr, uint32_t val, void *p);
int mem_load_video_bios();
FILE *romfopen(char *fn, char *mode);

7
src/model.c
View file

@ -78,12 +78,17 @@ MODEL models[] =
{"AMI 386 clone", ROM_AMI386, { "Intel", cpus_i386, "AMD", cpus_Am386, "Cyrix", cpus_486SDLC}, 0, at_headland_init},
{"AMI 486 clone", ROM_AMI486, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, at_ali1429_init},
{"AMI WinBIOS 486", ROM_WIN486, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, at_ali1429_init},
{"AMI WinBIOS 486 PCI", ROM_PCI486, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, at_um8881f_init},
/* {"AMI WinBIOS 486 PCI", ROM_PCI486, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, at_um8881f_init},*/
{"Award SiS 496/497", ROM_SIS496, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, at_sis496_init},
{"Award 430VX PCI", ROM_430VX, { "IDT", cpus_WinChip, "", NULL, "", NULL}, 0, at_i430vx_init},
{"", -1, {"", 0, "", 0, "", 0}, 0}
};
int model_count()
{
return (sizeof(models) / sizeof(MODEL)) - 1;
}
int model_getromset()
{
return models[model].id;

1
src/model.h
View file

@ -15,6 +15,7 @@ extern MODEL models[];
extern int model;
int model_count();
int model_getromset();
int model_getmodel(int romset);
char *model_getname();

8
src/pc.c
View file

@ -85,6 +85,7 @@ void fatal(const char *format, ...)
va_end(ap);
fputs(buf,pclogf);
fflush(pclogf);
dumppic();
dumpregs();
exit(-1);
}
@ -206,9 +207,9 @@ void initpc()
initvideo();
mem_init();
mem_load_video_bios();
loadbios();
mem_add_bios();
loaddisc(0,discfns[0]);
loaddisc(1,discfns[1]);
@ -436,6 +437,9 @@ void loadconfig()
model = get_config_int(NULL, "model", 14);
if (model >= model_count())
model = model_count() - 1;
romset = model_getromset();
cpu_manufacturer = get_config_int(NULL, "cpu_manufacturer", 0);
cpu = get_config_int(NULL, "cpu", 0);

20
src/pc.rc
View file

@ -47,20 +47,20 @@ BEGIN
END
END
ConfigureDlg DIALOGEX 0, 0, 182, 240
ConfigureDlg DIALOGEX 0, 0, 232, 240
STYLE DS_SETFONT | DS_MODALFRAME | DS_FIXEDSYS | WS_POPUP | WS_CAPTION | WS_SYSMENU
CAPTION "Configure PCem"
FONT 8, "MS Sans Serif"
BEGIN
DEFPUSHBUTTON "OK",IDOK,17,216,50,14, WS_TABSTOP
PUSHBUTTON "Cancel",IDCANCEL,71,216,50,14, WS_TABSTOP
COMBOBOX IDC_COMBO1,62,16,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOVID,62,36,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOCPUM,62,56,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBO3,62,76,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOCHC,62,96,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSPD,62,116,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSND,62,136,107,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
DEFPUSHBUTTON "OK",IDOK,64,216,50,14, WS_TABSTOP
PUSHBUTTON "Cancel",IDCANCEL,128,216,50,14, WS_TABSTOP
COMBOBOX IDC_COMBO1,62,16,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOVID,62,36,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOCPUM,62,56,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBO3,62,76,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOCHC,62,96,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSPD,62,116,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSND,62,136,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
EDITTEXT IDC_MEMTEXT, 62, 152, 36, 14, ES_AUTOHSCROLL | ES_NUMBER
CONTROL "", IDC_MEMSPIN, UPDOWN_CLASS, UDS_ALIGNRIGHT | UDS_ARROWKEYS | UDS_NOTHOUSANDS | UDS_SETBUDDYINT, 98, 152, 12, 14
LTEXT "MB", IDC_STATIC, 98, 152, 40, 10

5
src/pci.h
View file

@ -1,3 +1,8 @@
void pci_init();
void pci_add_specific(int card, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
void pci_add(uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
#define PCI_REG_COMMAND 0x04
#define PCI_COMMAND_IO 0x01
#define PCI_COMMAND_MEM 0x02

96
src/rom.c
View file

@ -1,5 +1,7 @@
#include <stdlib.h>
#include <stdio.h>
#include "ibm.h"
#include "mem.h"
#include "rom.h"
FILE *romfopen(char *fn, char *mode)
@ -27,3 +29,97 @@ int rom_present(char *fn)
}
return 0;
}
static uint8_t rom_read(uint32_t addr, void *p)
{
rom_t *rom = (rom_t *)p;
// pclog("rom_read : %08x %08x %02x\n", addr, rom->mask, rom->rom[addr & rom->mask]);
return rom->rom[addr & rom->mask];
}
uint16_t rom_readw(uint32_t addr, void *p)
{
rom_t *rom = (rom_t *)p;
// pclog("rom_readw: %08x %08x %04x\n", addr, rom->mask, *(uint16_t *)&rom->rom[addr & rom->mask]);
return *(uint16_t *)&rom->rom[addr & rom->mask];
}
uint32_t rom_readl(uint32_t addr, void *p)
{
rom_t *rom = (rom_t *)p;
// pclog("rom_readl: %08x %08x %08x\n", addr, rom->mask, *(uint32_t *)&rom->rom[addr & rom->mask]);
return *(uint32_t *)&rom->rom[addr & rom->mask];
}
int rom_init(rom_t *rom, char *fn, uint32_t address, int size, int mask, int file_offset, uint32_t flags)
{
FILE *f = romfopen(fn, "rb");
if (!f)
{
pclog("ROM image not found : %s\n", fn);
return -1;
}
rom->rom = malloc(size);
fseek(f, file_offset, SEEK_SET);
fread(rom->rom, size, 1, f);
fclose(f);
rom->mask = mask;
mem_mapping_add(&rom->mapping, address, size, rom_read,
rom_readw,
rom_readl,
mem_write_null,
mem_write_nullw,
mem_write_nulll,
rom->rom,
flags,
rom);
return 0;
}
int rom_init_interleaved(rom_t *rom, char *fn_low, char *fn_high, uint32_t address, int size, int mask, int file_offset, uint32_t flags)
{
FILE *f_low = romfopen(fn_low, "rb");
FILE *f_high = romfopen(fn_high, "rb");
int c;
if (!f_low || !f_high)
{
if (!f_low)
pclog("ROM image not found : %s\n", fn_low);
else
fclose(f_low);
if (!f_high)
pclog("ROM image not found : %s\n", fn_high);
else
fclose(f_high);
return -1;
}
rom->rom = malloc(size);
fseek(f_low, file_offset, SEEK_SET);
fseek(f_high, file_offset, SEEK_SET);
for (c = 0; c < size; c += 2)
{
rom->rom[c] = getc(f_low);
rom->rom[c + 1] = getc(f_high);
}
fclose(f_high);
fclose(f_low);
rom->mask = mask;
mem_mapping_add(&rom->mapping, address, size, rom_read,
rom_readw,
rom_readl,
mem_write_null,
mem_write_nullw,
mem_write_nulll,
rom->rom,
flags,
rom);
return 0;
}

10
src/rom.h
View file

@ -1,2 +1,12 @@
FILE *romfopen(char *fn, char *mode);
int rom_present(char *fn);
typedef struct rom_t
{
uint8_t *rom;
uint32_t mask;
mem_mapping_t mapping;
} rom_t;
int rom_init(rom_t *rom, char *fn, uint32_t address, int size, int mask, int file_offset, uint32_t flags);
int rom_init_interleaved(rom_t *rom, char *fn_low, char *fn_high, uint32_t address, int size, int mask, int file_offset, uint32_t flags);

63
src/sis496.c
View file

@ -14,45 +14,32 @@ typedef struct sis496_t
void sis496_recalcmapping(sis496_t *sis496)
{
if (sis496->pci_conf[0x44] & 0x10)
int c;
for (c = 0; c < 8; c++)
{
if (sis496->pci_conf[0x45] & 0x01)
mem_bios_set_state(0xe0000, 0x08000, 1, 0);
uint32_t base = 0xc0000 + (c << 15);
if (sis496->pci_conf[0x44] & (1 << c))
{
switch (sis496->pci_conf[0x45] & 3)
{
case 0:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 1:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
}
else
mem_bios_set_state(0xe0000, 0x08000, 1, 1);
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
else
mem_bios_set_state(0xe0000, 0x08000, 0, 1);
if (sis496->pci_conf[0x44] & 0x20)
{
if (sis496->pci_conf[0x45] & 0x01)
mem_bios_set_state(0xe8000, 0x08000, 1, 0);
else
mem_bios_set_state(0xe8000, 0x08000, 1, 1);
}
else
mem_bios_set_state(0xe8000, 0x08000, 0, 1);
if (sis496->pci_conf[0x44] & 0x40)
{
if (sis496->pci_conf[0x45] & 0x01)
mem_bios_set_state(0xf0000, 0x08000, 1, 0);
else
mem_bios_set_state(0xf0000, 0x08000, 1, 1);
}
else
mem_bios_set_state(0xf0000, 0x08000, 0, 1);
if (sis496->pci_conf[0x44] & 0x80)
{
if (sis496->pci_conf[0x45] & 0x01)
mem_bios_set_state(0xf8000, 0x08000, 1, 0);
else
mem_bios_set_state(0xf8000, 0x08000, 1, 1);
}
else
mem_bios_set_state(0xf8000, 0x08000, 0, 1);
flushmmucache();
shadowbios = (sis496->pci_conf[0x44] & 0xf0);
@ -61,7 +48,7 @@ void sis496_recalcmapping(sis496_t *sis496)
void sis496_write(int func, int addr, uint8_t val, void *p)
{
sis496_t *sis496 = (sis496_t *)p;
//pclog("sis496_write : addr=%02x val=%02x\n", addr, val);
//pclog("sis496_write : addr=%02x val=%02x\n", addr, val);
switch (addr)
{
case 0x44: /*Shadow configure*/
@ -72,8 +59,6 @@ void sis496_write(int func, int addr, uint8_t val, void *p)
}
break;
case 0x45: /*Shadow configure*/
//if (val == 3)
// output = 3;
if ((sis496->pci_conf[0x45] & val) ^ 0x01)
{
sis496->pci_conf[0x45] = val;

8
src/sound_gus.c
View file

@ -638,8 +638,8 @@ uint8_t readgus(uint16_t addr, void *p)
val = 0xff;
break;
default:
fatal("Bad GUS global low read %02X\n",gus->global);
// default:
// fatal("Bad GUS global low read %02X\n",gus->global);
}
break;
case 0x345: /*Global high*/
@ -693,8 +693,8 @@ uint8_t readgus(uint16_t addr, void *p)
val = 0xff;
break;
default:
fatal("Bad GUS global high read %02X\n",gus->global);
// default:
// fatal("Bad GUS global high read %02X\n",gus->global);
}
break;
case 0x346: return 0xff;

9
src/um8881f.c
View file

@ -10,28 +10,29 @@ static uint8_t card_18[256];
void um8881f_write(int func, int addr, uint8_t val, void *priv)
{
// pclog("um8881f_write : addr=%02x val=%02x %04x:%04x\n", addr, val, CS, pc);
if (addr == 0x54)
{
if ((card_16[0x54] ^ val) & 0x01)
/* if ((card_16[0x54] ^ val) & 0x01)
{
if (val & 1)
mem_bios_set_state(0xe0000, 0x10000, 1, 1);
else
mem_bios_set_state(0xe0000, 0x10000, 0, 0);
}
}*/
flushmmucache_nopc();
}
if (addr == 0x55)
{
if ((card_16[0x55] ^ val) & 0xc0)
{
switch (val & 0xc0)
/* switch (val & 0xc0)
{
case 0x00: mem_bios_set_state(0xf0000, 0x10000, 0, 1); break;
case 0x40: mem_bios_set_state(0xf0000, 0x10000, 0, 0); break;
case 0x80: mem_bios_set_state(0xf0000, 0x10000, 1, 1); break;
case 0xc0: mem_bios_set_state(0xf0000, 0x10000, 1, 0); break;
}
}*/
shadowbios = val & 0x80;
shadowbios_write = !(val & 0x40);
flushmmucache_nopc();

12
src/vid_ati18800.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_ati18800.h"
#include "vid_ati_eeprom.h"
@ -13,6 +14,8 @@ typedef struct ati18800_t
{
svga_t svga;
ati_eeprom_t eeprom;
rom_t bios_rom;
uint8_t regs[256];
int index;
@ -122,6 +125,8 @@ void *ati18800_init()
ati18800_t *ati18800 = malloc(sizeof(ati18800_t));
memset(ati18800, 0, sizeof(ati18800_t));
rom_init(&ati18800->bios_rom, "roms/vgaedge16.vbi", 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&ati18800->svga, ati18800, 1 << 19, /*512kb*/
NULL,
ati18800_in, ati18800_out,
@ -137,6 +142,11 @@ void *ati18800_init()
return ati18800;
}
static int ati18800_available()
{
return rom_present("roms/vgaedge16.vbi");
}
void ati18800_close(void *p)
{
ati18800_t *ati18800 = (ati18800_t *)p;
@ -173,7 +183,7 @@ device_t ati18800_device =
0,
ati18800_init,
ati18800_close,
NULL,
ati18800_available,
ati18800_speed_changed,
ati18800_force_redraw,
ati18800_add_status_info

12
src/vid_ati28800.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_ati28800.h"
#include "vid_ati_eeprom.h"
@ -15,6 +16,8 @@ typedef struct ati28800_t
svga_t svga;
ati_eeprom_t eeprom;
rom_t bios_rom;
uint8_t regs[256];
int index;
} ati28800_t;
@ -143,6 +146,8 @@ void *ati28800_init()
ati28800_t *ati28800 = malloc(sizeof(ati28800_t));
memset(ati28800, 0, sizeof(ati28800_t));
rom_init(&ati28800->bios_rom, "roms/bios.bin", 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&ati28800->svga, ati28800, 1 << 19, /*512kb*/
ati28800_recalctimings,
ati28800_in, ati28800_out,
@ -158,6 +163,11 @@ void *ati28800_init()
return ati28800;
}
static int ati28800_available()
{
return rom_present("roms/bios.bin");
}
void ati28800_close(void *p)
{
ati28800_t *ati28800 = (ati28800_t *)p;
@ -194,7 +204,7 @@ device_t ati28800_device =
0,
ati28800_init,
ati28800_close,
NULL,
ati28800_available,
ati28800_speed_changed,
ati28800_force_redraw,
ati28800_add_status_info

126
src/vid_ati_mach64.c
View file

@ -5,6 +5,7 @@
#include "io.h"
#include "mem.h"
#include "pci.h"
#include "rom.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_ati68860_ramdac.h"
@ -25,8 +26,12 @@ typedef struct mach64_t
ics2595_t ics2595;
svga_t svga;
rom_t bios_rom;
uint8_t regs[256];
int index;
uint8_t pci_regs[256];
int bank_r[2];
int bank_w[2];
@ -338,6 +343,16 @@ void mach64_updatemapping(mach64_t *mach64)
{
svga_t *svga = &mach64->svga;
if (!(mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
{
pclog("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
return;
}
mem_mapping_disable(&mach64->mmio_mapping);
// pclog("Write mapping %02X\n", val);
switch (svga->gdcreg[6] & 0xc)
@ -1835,9 +1850,13 @@ uint16_t mach64_ext_inw(uint16_t port, void *p)
switch (port)
{
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret = mach64_ext_inb(port, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret |= (mach64_ext_inb(port + 1, p) << 8);
break;
}
@ -1860,9 +1879,13 @@ uint32_t mach64_ext_inl(uint16_t port, void *p)
break;
default:
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret = mach64_ext_inw(port, p);
#ifdef MACH64_DEBUG
pclog(" ");
#endif
ret |= (mach64_ext_inw(port + 2, p) << 16);
break;
}
@ -2053,6 +2076,42 @@ void mach64_hwcursor_draw(svga_t *svga, int displine)
svga->hwcursor_latch.addr += 16;
}
static void mach64_io_remove(mach64_t *mach64)
{
int c;
io_removehandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
for (c = 0; c < 8; c++)
{
io_removehandler((c * 0x1000) + 0x2ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_removehandler((c * 0x1000) + 0x6ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_removehandler((c * 0x1000) + 0xaec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_removehandler((c * 0x1000) + 0xeec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
}
io_removehandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
}
static void mach64_io_set(mach64_t *mach64)
{
int c;
mach64_io_remove(mach64);
io_sethandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
for (c = 0; c < 8; c++)
{
io_sethandler((c * 0x1000) + 0x2ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x6ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xaec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xeec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
}
io_sethandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
}
uint8_t mach64_pci_read(int func, int addr, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
@ -2068,7 +2127,8 @@ uint8_t mach64_pci_read(int func, int addr, void *p)
case 0x02: return 'X'; /*88800GX*/
case 0x03: return 'G';
case 0x04: return 0x03; /*Respond to IO and memory accesses*/
case PCI_REG_COMMAND:
return mach64->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
case 0x07: return 1 << 1; /*Medium DEVSEL timing*/
@ -2083,10 +2143,10 @@ uint8_t mach64_pci_read(int func, int addr, void *p)
case 0x12: return mach64->linear_base >> 16;
case 0x13: return mach64->linear_base >> 24;
case 0x30: return 0x01; /*BIOS ROM address*/
case 0x30: return mach64->pci_regs[0x30] & 0x01; /*BIOS ROM address*/
case 0x31: return 0x00;
case 0x32: return 0x0C;
case 0x33: return 0x00;
case 0x32: return mach64->pci_regs[0x32];
case 0x33: return mach64->pci_regs[0x33];
}
return 0;
}
@ -2099,6 +2159,15 @@ void mach64_pci_write(int func, int addr, uint8_t val, void *p)
switch (addr)
{
case PCI_REG_COMMAND:
mach64->pci_regs[PCI_REG_COMMAND] = val & 0x27;
if (val & PCI_COMMAND_IO)
mach64_io_set(mach64);
else
mach64_io_remove(mach64);
mach64_updatemapping(mach64);
break;
case 0x12:
mach64->linear_base = (mach64->linear_base & 0xff000000) | ((val & 0x80) << 16);
mach64_updatemapping(mach64);
@ -2107,6 +2176,21 @@ void mach64_pci_write(int func, int addr, uint8_t val, void *p)
mach64->linear_base = (mach64->linear_base & 0x800000) | (val << 24);
mach64_updatemapping(mach64);
break;
case 0x30: case 0x32: case 0x33:
mach64->pci_regs[addr] = val;
if (mach64->pci_regs[0x30] & 0x01)
{
uint32_t addr = (mach64->pci_regs[0x32] << 16) | (mach64->pci_regs[0x33] << 24);
pclog("Mach64 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&mach64->bios_rom.mapping, addr, 0x8000);
}
else
{
pclog("Mach64 bios_rom disabled\n");
mem_mapping_disable(&mach64->bios_rom.mapping);
}
return;
}
}
@ -2121,24 +2205,23 @@ void *mach64gx_init()
mach64_in, mach64_out,
mach64_hwcursor_draw);
mem_mapping_add(&mach64->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &mach64->svga);
mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64);
mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64);
rom_init(&mach64->bios_rom, "roms/mach64gx/bios.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&mach64->bios_rom.mapping);
mem_mapping_add(&mach64->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, 0, &mach64->svga);
mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, 0, mach64);
mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, 0, mach64);
mem_mapping_disable(&mach64->mmio_mapping);
io_sethandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
for (c = 0; c < 8; c++)
{
io_sethandler((c * 0x1000) + 0x2ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x6ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xaec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xeec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
}
io_sethandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
mach64_io_set(mach64);
pci_add(mach64_pci_read, mach64_pci_write, mach64);
mach64->pci_regs[PCI_REG_COMMAND] = 3;
mach64->pci_regs[0x30] = 0x00;
mach64->pci_regs[0x32] = 0x0c;
mach64->pci_regs[0x33] = 0x00;
ati_eeprom_load(&mach64->eeprom, "mach64.nvr", 1);
@ -2149,6 +2232,11 @@ void *mach64gx_init()
return mach64;
}
int mach64gx_available()
{
return rom_present("roms/mach64gx/bios.bin");
}
void mach64_close(void *p)
{
mach64_t *mach64 = (mach64_t *)p;
@ -2225,7 +2313,7 @@ device_t mach64gx_device =
0,
mach64gx_init,
mach64_close,
NULL,
mach64gx_available,
mach64_speed_changed,
mach64_force_redraw,
mach64_add_status_info

2
src/vid_cga.c
View file

@ -499,7 +499,7 @@ void *cga_standalone_init()
q_filt[c] = 512.0 * sin((3.14 * (cga_tint + c * 4) / 16.0) - 33.0 / 180.0);
}
timer_add(cga_poll, &cga->vidtime, TIMER_ALWAYS_ENABLED, cga);
mem_mapping_add(&cga->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga);
mem_mapping_add(&cga->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, NULL, 0, cga);
io_sethandler(0x03d0, 0x0010, cga_in, NULL, NULL, cga_out, NULL, NULL, cga);
return cga;
}

14
src/vid_cl5429.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_cl5429.h"
#include "vid_svga.h"
@ -16,6 +17,8 @@ typedef struct gd5429_t
svga_t svga;
rom_t bios_rom;
uint32_t bank[2];
uint32_t mask;
@ -816,6 +819,8 @@ void *gd5429_init()
svga_t *svga = &gd5429->svga;
memset(gd5429, 0, sizeof(gd5429_t));
rom_init(&gd5429->bios_rom, "roms/5429.vbi", 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&gd5429->svga, gd5429, 1 << 21, /*2mb*/
gd5429_recalctimings,
gd5429_in, gd5429_out,
@ -824,7 +829,7 @@ void *gd5429_init()
mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL);
mem_mapping_set_p(&gd5429->svga.mapping, gd5429);
mem_mapping_add(&gd5429->mmio_mapping, 0, 0, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429);
mem_mapping_add(&gd5429->mmio_mapping, 0, 0, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, NULL, 0, gd5429);
io_sethandler(0x03c0, 0x0020, gd5429_in, NULL, NULL, gd5429_out, NULL, NULL, gd5429);
@ -836,6 +841,11 @@ void *gd5429_init()
return gd5429;
}
static int gd5429_available()
{
return rom_present("roms/5429.vbi");
}
void gd5429_close(void *p)
{
gd5429_t *gd5429 = (gd5429_t *)p;
@ -872,7 +882,7 @@ device_t gd5429_device =
DEVICE_NOT_WORKING,
gd5429_init,
gd5429_close,
NULL,
gd5429_available,
gd5429_speed_changed,
gd5429_force_redraw,
gd5429_add_status_info

25
src/vid_ega.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "timer.h"
#include "video.h"
#include "vid_ega.h"
@ -810,15 +811,35 @@ void *ega_standalone_init()
int c, d, e;
ega_t *ega = malloc(sizeof(ega_t));
memset(ega, 0, sizeof(ega_t));
rom_init(&ega->bios_rom, "roms/ibm_6277356_ega_card_u44_27128.bin", 0xc0000, 0x8000, 0x7fff, 0, 0);
if (ega->bios_rom.rom[0x3ffe] == 0xaa && ega->bios_rom.rom[0x3fff] == 0x55)
{
int c;
pclog("Read EGA ROM in reverse\n");
for (c = 0; c < 0x2000; c++)
{
uint8_t temp = ega->bios_rom.rom[c];
ega->bios_rom.rom[c] = ega->bios_rom.rom[0x3fff - c];
ega->bios_rom.rom[0x3fff - c] = temp;
}
}
ega_init(ega);
mem_mapping_add(&ega->mapping, 0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega);
mem_mapping_add(&ega->mapping, 0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, NULL, 0, ega);
timer_add(ega_poll, &ega->vidtime, TIMER_ALWAYS_ENABLED, ega);
io_sethandler(0x03a0, 0x0040, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
return ega;
}
static int ega_standalone_available()
{
return rom_present("roms/ibm_6277356_ega_card_u44_27128.bin");
}
void ega_close(void *p)
{
ega_t *ega = (ega_t *)p;
@ -840,7 +861,7 @@ device_t ega_device =
0,
ega_standalone_init,
ega_close,
NULL,
ega_standalone_available,
ega_speed_changed,
NULL,
NULL

2
src/vid_ega.h
View file

@ -2,6 +2,8 @@ typedef struct ega_t
{
mem_mapping_t mapping;
rom_t bios_rom;
uint8_t crtcreg;
uint8_t crtc[32];
uint8_t gdcreg[16];

12
src/vid_et4000.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_unk_ramdac.h"
@ -15,6 +16,8 @@ typedef struct et4000_t
svga_t svga;
unk_ramdac_t ramdac;
rom_t bios_rom;
uint8_t banking;
} et4000_t;
@ -129,7 +132,9 @@ void *et4000_init()
{
et4000_t *et4000 = malloc(sizeof(et4000_t));
memset(et4000, 0, sizeof(et4000_t));
rom_init(&et4000->bios_rom, "roms/et4000.bin", 0xc0000, 0x8000, 0x7fff, 0, 0);
io_sethandler(0x03c0, 0x0020, et4000_in, NULL, NULL, et4000_out, NULL, NULL, et4000);
svga_init(&et4000->svga, et4000, 1 << 20, /*1mb*/
@ -140,6 +145,11 @@ void *et4000_init()
return et4000;
}
static int et4000_available()
{
return rom_present("roms/et4000.bin");
}
void et4000_close(void *p)
{
et4000_t *et4000 = (et4000_t *)p;

109
src/vid_et4000w32.c
View file

@ -9,6 +9,7 @@
#include "io.h"
#include "mem.h"
#include "pci.h"
#include "rom.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_icd2061.h"
@ -19,6 +20,8 @@ typedef struct et4000w32p_t
mem_mapping_t linear_mapping;
mem_mapping_t mmu_mapping;
rom_t bios_rom;
svga_t svga;
stg_ramdac_t ramdac;
icd2061_t icd2061;
@ -28,7 +31,9 @@ typedef struct et4000w32p_t
uint32_t linearbase, linearbase_old;
uint8_t banking, banking2;
uint8_t pci_regs[256];
/*Accelerator*/
struct
{
@ -260,6 +265,15 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000)
{
svga_t *svga = &et4000->svga;
if (!(et4000->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
{
pclog("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&et4000->linear_mapping);
mem_mapping_disable(&et4000->mmu_mapping);
return;
}
pclog("recalcmapping %p\n", svga);
if (svga->crtc[0x36] & 0x10) /*Linear frame buffer*/
{
@ -887,6 +901,36 @@ void et4000w32p_hwcursor_draw(svga_t *svga, int displine)
svga->hwcursor_latch.addr += 16;
}
static void et4000w32p_io_remove(et4000w32p_t *et4000)
{
io_removehandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x211A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x212A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x213A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x214A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x215A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x216A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x217A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
}
static void et4000w32p_io_set(et4000w32p_t *et4000)
{
et4000w32p_io_remove(et4000);
io_sethandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x211A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x212A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x213A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x214A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x215A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x216A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x217A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
}
uint8_t et4000w32p_pci_read(int func, int addr, void *p)
{
et4000w32p_t *et4000 = (et4000w32p_t *)p;
@ -902,7 +946,8 @@ uint8_t et4000w32p_pci_read(int func, int addr, void *p)
case 0x02: return 0x06; /*ET4000W32p Rev D*/
case 0x03: return 0x32;
case 0x04: return 0x03; /*Respond to IO and memory accesses*/
case PCI_REG_COMMAND:
return et4000->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
case 0x07: return 1 << 1; /*Medium DEVSEL timing*/
@ -917,10 +962,10 @@ uint8_t et4000w32p_pci_read(int func, int addr, void *p)
case 0x12: return svga->crtc[0x5a] & 0x80;
case 0x13: return svga->crtc[0x59];
case 0x30: return 0x01; /*BIOS ROM address*/
case 0x30: return et4000->pci_regs[0x30] & 0x01; /*BIOS ROM address*/
case 0x31: return 0x00;
case 0x32: return 0x0C;
case 0x33: return 0x00;
case 0x32: return et4000->pci_regs[0x32];
case 0x33: return et4000->pci_regs[0x33];
}
return 0;
}
@ -931,10 +976,34 @@ void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p)
switch (addr)
{
case PCI_REG_COMMAND:
et4000->pci_regs[PCI_REG_COMMAND] = val & 0x27;
if (val & PCI_COMMAND_IO)
et4000w32p_io_set(et4000);
else
et4000w32p_io_remove(et4000);
et4000w32p_recalcmapping(et4000);
break;
case 0x13:
et4000->linearbase = val << 24;
et4000w32p_recalcmapping(et4000);
break;
case 0x30: case 0x32: case 0x33:
et4000->pci_regs[addr] = val;
if (et4000->pci_regs[0x30] & 0x01)
{
uint32_t addr = (et4000->pci_regs[0x32] << 16) | (et4000->pci_regs[0x33] << 24);
pclog("ET4000 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&et4000->bios_rom.mapping, addr, 0x8000);
}
else
{
pclog("ET4000 bios_rom disabled\n");
mem_mapping_disable(&et4000->bios_rom.mapping);
}
return;
}
}
@ -948,25 +1017,31 @@ void *et4000w32p_init()
et4000w32p_in, et4000w32p_out,
et4000w32p_hwcursor_draw);
mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &et4000->svga);
mem_mapping_add(&et4000->mmu_mapping, 0, 0, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000);
rom_init(&et4000->bios_rom, "roms/et4000w32.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&et4000->bios_rom.mapping);
io_sethandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, 0, &et4000->svga);
mem_mapping_add(&et4000->mmu_mapping, 0, 0, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL, 0, et4000);
io_sethandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x211A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x212A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x213A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x214A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x215A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x216A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x217A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
et4000w32p_io_set(et4000);
pci_add(et4000w32p_pci_read, et4000w32p_pci_write, et4000);
et4000->pci_regs[0x04] = 7;
et4000->pci_regs[0x30] = 0x00;
et4000->pci_regs[0x32] = 0x0c;
et4000->pci_regs[0x33] = 0x00;
return et4000;
}
int et4000w32p_available()
{
return rom_present("roms/et4000w32.bin");
}
void et4000w32p_close(void *p)
{
et4000w32p_t *et4000 = (et4000w32p_t *)p;
@ -1003,7 +1078,7 @@ device_t et4000w32p_device =
0,
et4000w32p_init,
et4000w32p_close,
NULL,
et4000w32p_available,
et4000w32p_speed_changed,
et4000w32p_force_redraw,
et4000w32p_add_status_info

2
src/vid_hercules.c
View file

@ -313,7 +313,7 @@ void *hercules_init()
hercules->vram = malloc(0x10000);
timer_add(hercules_poll, &hercules->vidtime, TIMER_ALWAYS_ENABLED, hercules);
mem_mapping_add(&hercules->mapping, 0xb0000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules);
mem_mapping_add(&hercules->mapping, 0xb0000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, NULL, 0, hercules);
io_sethandler(0x03b0, 0x0010, hercules_in, NULL, NULL, hercules_out, NULL, NULL, hercules);
for (c = 0; c < 256; c++)

2
src/vid_mda.c
View file

@ -270,7 +270,7 @@ void *mda_init()
mda->vram = malloc(0x1000);
timer_add(mda_poll, &mda->vidtime, TIMER_ALWAYS_ENABLED, mda);
mem_mapping_add(&mda->mapping, 0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, mda);
mem_mapping_add(&mda->mapping, 0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, NULL, 0, mda);
io_sethandler(0x03b0, 0x0010, mda_in, NULL, NULL, mda_out, NULL, NULL, mda);
for (c = 0; c < 256; c++)

2
src/vid_olivetti_m24.c
View file

@ -459,7 +459,7 @@ void *m24_init()
m24->vram = malloc(0x8000);
timer_add(m24_poll, &m24->vidtime, TIMER_ALWAYS_ENABLED, m24);
mem_mapping_add(&m24->mapping, 0xb8000, 0x08000, m24_read, NULL, NULL, m24_write, NULL, NULL, m24);
mem_mapping_add(&m24->mapping, 0xb8000, 0x08000, m24_read, NULL, NULL, m24_write, NULL, NULL, NULL, 0, m24);
io_sethandler(0x03d0, 0x0010, m24_in, NULL, NULL, m24_out, NULL, NULL, m24);
return m24;
}

40
src/vid_oti067.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_oti067.h"
#include "vid_svga.h"
@ -12,6 +13,8 @@ typedef struct oti067_t
{
svga_t svga;
rom_t bios_rom;
int index;
uint8_t regs[32];
} oti067_t;
@ -110,11 +113,13 @@ void oti067_recalctimings(svga_t *svga)
svga->interlace = oti067->regs[0x14] & 0x80;
}
void *oti067_init()
void *oti067_common_init(char *bios_fn)
{
oti067_t *oti067 = malloc(sizeof(oti067_t));
memset(oti067, 0, sizeof(oti067_t));
rom_init(&oti067->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&oti067->svga, oti067, 1 << 19, /*512kb*/
oti067_recalctimings,
oti067_in, oti067_out,
@ -126,6 +131,26 @@ void *oti067_init()
return oti067;
}
void *oti067_init()
{
return oti067_common_init("roms/oti067/bios.bin");
}
void *oti067_acer386_init()
{
oti067_t *oti067 = oti067_common_init("roms/acer386/oti067.bin");
if (oti067)
oti067->bios_rom.rom[0x5d] = 0x74;
return oti067;
}
static int oti067_available()
{
return rom_present("roms/oti067/bios.bin");
}
void oti067_close(void *p)
{
oti067_t *oti067 = (oti067_t *)p;
@ -162,7 +187,18 @@ device_t oti067_device =
0,
oti067_init,
oti067_close,
NULL,
oti067_available,
oti067_speed_changed,
oti067_force_redraw,
oti067_add_status_info
};
device_t oti067_acer386_device =
{
"Oak OTI-067 (Acermate 386SX/25N)",
0,
oti067_acer386_init,
oti067_close,
oti067_available,
oti067_speed_changed,
oti067_force_redraw,
oti067_add_status_info

1
src/vid_oti067.h
View file

@ -1 +1,2 @@
extern device_t oti067_device;
extern device_t oti067_acer386_device;

58
src/vid_paradise.c
View file

@ -7,6 +7,7 @@
#include "ibm.h"
#include "device.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_paradise.h"
#include "vid_svga.h"
@ -17,6 +18,8 @@ typedef struct paradise_t
{
svga_t svga;
rom_t bios_rom;
enum
{
PVGA1A = 0,
@ -312,6 +315,38 @@ void *paradise_wd90c11_init()
return paradise;
}
static void *paradise_pvga1a_pc2086_init()
{
paradise_t *paradise = paradise_pvga1a_init();
if (paradise)
rom_init(&paradise->bios_rom, "roms/pc2086/40186.ic171", 0xc0000, 0x8000, 0x7fff, 0, 0);
return paradise;
}
static void *paradise_pvga1a_pc3086_init()
{
paradise_t *paradise = paradise_pvga1a_init();
if (paradise)
rom_init(&paradise->bios_rom, "roms/pc3086/c000.bin", 0xc0000, 0x8000, 0x7fff, 0, 0);
return paradise;
}
static void *paradise_wd90c11_megapc_init()
{
paradise_t *paradise = paradise_wd90c11_init();
if (paradise)
rom_init_interleaved(&paradise->bios_rom,
"roms/megapc/41651-bios lo.u18",
"roms/megapc/211253-bios hi.u19",
0xc0000, 0x8000, 0x7fff, 0, 0);
return paradise;
}
void paradise_close(void *p)
{
paradise_t *paradise = (paradise_t *)p;
@ -342,22 +377,33 @@ int paradise_add_status_info(char *s, int max_len, void *p)
return svga_add_status_info(s, max_len, &paradise->svga);
}
device_t paradise_pvga1a_device =
device_t paradise_pvga1a_pc2086_device =
{
"Paradise PVGA1A",
"Paradise PVGA1A (Amstrad PC2086)",
0,
paradise_pvga1a_init,
paradise_pvga1a_pc2086_init,
paradise_close,
NULL,
paradise_speed_changed,
paradise_force_redraw,
paradise_add_status_info
};
device_t paradise_wd90c11_device =
device_t paradise_pvga1a_pc3086_device =
{
"Paradise WD90C11",
"Paradise PVGA1A (Amstrad PC3086)",
0,
paradise_wd90c11_init,
paradise_pvga1a_pc3086_init,
paradise_close,
NULL,
paradise_speed_changed,
paradise_force_redraw,
paradise_add_status_info
};
device_t paradise_wd90c11_megapc_device =
{
"Paradise WD90C11 (Amstrad MegaPC)",
0,
paradise_wd90c11_megapc_init,
paradise_close,
NULL,
paradise_speed_changed,

5
src/vid_paradise.h
View file

@ -1,2 +1,3 @@
extern device_t paradise_pvga1a_device;
extern device_t paradise_wd90c11_device;
extern device_t paradise_pvga1a_pc2086_device;
extern device_t paradise_pvga1a_pc3086_device;
extern device_t paradise_wd90c11_megapc_device;

2
src/vid_pc1512.c
View file

@ -460,7 +460,7 @@ static void *pc1512_init()
pc1512->cgamode = 0x12;
timer_add(pc1512_poll, &pc1512->vidtime, TIMER_ALWAYS_ENABLED, pc1512);
mem_mapping_add(&pc1512->mapping, 0xb8000, 0x08000, pc1512_read, NULL, NULL, pc1512_write, NULL, NULL, pc1512);
mem_mapping_add(&pc1512->mapping, 0xb8000, 0x08000, pc1512_read, NULL, NULL, pc1512_write, NULL, NULL, NULL, 0, pc1512);
io_sethandler(0x03d0, 0x0010, pc1512_in, NULL, NULL, pc1512_out, NULL, NULL, pc1512);
return pc1512;
}

9
src/vid_pc1640.c
View file

@ -5,6 +5,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "timer.h"
#include "video.h"
#include "vid_cga.h"
@ -19,6 +20,8 @@ typedef struct pc1640_t
cga_t cga;
ega_t ega;
rom_t bios_rom;
int cga_enabled;
int dispontime, dispofftime, vidtime;
} pc1640_t;
@ -114,14 +117,16 @@ void *pc1640_init()
ega_t *ega = &pc1640->ega;
memset(pc1640, 0, sizeof(pc1640_t));
rom_init(&pc1640->bios_rom, "roms/pc1640/40100", 0xc0000, 0x8000, 0x7fff, 0, 0);
ega_init(&pc1640->ega);
pc1640->cga.vram = pc1640->ega.vram;
pc1640->cga_enabled = 1;
cga_init(&pc1640->cga);
timer_add(pc1640_poll, &pc1640->vidtime, TIMER_ALWAYS_ENABLED, pc1640);
mem_mapping_add(&pc1640->cga_mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga);
mem_mapping_add(&pc1640->ega_mapping, 0, 0, ega_read, NULL, NULL, ega_write, NULL, NULL, ega);
mem_mapping_add(&pc1640->cga_mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, NULL, 0, cga);
mem_mapping_add(&pc1640->ega_mapping, 0, 0, ega_read, NULL, NULL, ega_write, NULL, NULL, NULL, 0, ega);
io_sethandler(0x03a0, 0x0040, pc1640_in, NULL, NULL, pc1640_out, NULL, NULL, pc1640);
return pc1640;
}

2
src/vid_pc200.c
View file

@ -111,7 +111,7 @@ void *pc200_init()
cga_init(&pc200->cga);
timer_add(cga_poll, &cga->vidtime, TIMER_ALWAYS_ENABLED, cga);
mem_mapping_add(&pc200->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga);
mem_mapping_add(&pc200->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, NULL, 0, cga);
io_sethandler(0x03d0, 0x0010, pc200_in, NULL, NULL, pc200_out, NULL, NULL, pc200);
return cga;
}

2
src/vid_pcjr.c
View file

@ -615,7 +615,7 @@ static void *pcjr_video_init()
q_filt[c] = 512.0 * sin((3.14 * (pcjr_tint + c * 4) / 16.0) - 33.0 / 180.0);
}
timer_add(pcjr_poll, &pcjr->vidtime, TIMER_ALWAYS_ENABLED, pcjr);
mem_mapping_add(&pcjr->mapping, 0xb8000, 0x08000, pcjr_read, NULL, NULL, pcjr_write, NULL, NULL, pcjr);
mem_mapping_add(&pcjr->mapping, 0xb8000, 0x08000, pcjr_read, NULL, NULL, pcjr_write, NULL, NULL, NULL, 0, pcjr);
io_sethandler(0x03d0, 0x0010, pcjr_in, NULL, NULL, pcjr_out, NULL, NULL, pcjr);
return pcjr;
}

372
src/vid_s3.c
View file

@ -5,6 +5,7 @@
#include "io.h"
#include "mem.h"
#include "pci.h"
#include "rom.h"
#include "video.h"
#include "vid_s3.h"
#include "vid_svga.h"
@ -16,6 +17,8 @@ typedef struct s3_t
mem_mapping_t linear_mapping;
mem_mapping_t mmio_mapping;
rom_t bios_rom;
svga_t svga;
sdac_ramdac_t ramdac;
@ -25,8 +28,12 @@ typedef struct s3_t
int bpp;
uint8_t id, id_ext;
int packed_mmio;
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
float (*getclock)(int clock, void *p);
void *getclock_p;
@ -238,7 +245,7 @@ uint8_t s3_in(uint16_t addr, void *p)
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
// pclog("Read CRTC R%02X %04X:%04X\n", crtcreg, CS, pc);
// pclog("Read CRTC R%02X %04X:%04X\n", svga->crtcreg, CS, pc);
switch (svga->crtcreg)
{
case 0x2d: return 0x88; /*Extended chip ID*/
@ -322,6 +329,14 @@ void s3_updatemapping(s3_t *s3)
// video_write_a000_w = video_write_a000_l = NULL;
if (!(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
{
// pclog("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&s3->linear_mapping);
mem_mapping_disable(&s3->mmio_mapping);
return;
}
// pclog("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc);
switch (svga->gdcreg[6] & 0xc) /*Banked framebuffer*/
@ -371,8 +386,11 @@ void s3_updatemapping(s3_t *s3)
if (s3->linear_base == 0xa0000)
{
mem_mapping_disable(&s3->linear_mapping);
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
if (!(svga->crtc[0x53] & 0x10))
{
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
}
// mem_mapping_set_addr(&s3->linear_mapping, 0xa0000, 0x10000);
}
else
@ -383,7 +401,10 @@ void s3_updatemapping(s3_t *s3)
// pclog("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x10);
if (svga->crtc[0x53] & 0x10) /*Memory mapped IO*/
{
mem_mapping_disable(&svga->mapping);
mem_mapping_enable(&s3->mmio_mapping);
}
else
mem_mapping_disable(&s3->mmio_mapping);
}
@ -412,6 +433,7 @@ void s3_accel_out(uint16_t port, uint8_t val, void *p)
{
s3_t *s3 = (s3_t *)p;
// pclog("Accel out %04X %02X\n", port, val);
switch (port)
{
case 0x42e8:
@ -795,12 +817,109 @@ uint8_t s3_accel_in(uint16_t port, void *p)
return 0;
}
#define WRITE8(addr, var, val) switch ((addr) & 3) \
{ \
case 0: var = (var & 0xffffff00) | (val); break; \
case 1: var = (var & 0xffff00ff) | ((val) << 8); break; \
case 2: var = (var & 0xff00ffff) | ((val) << 16); break; \
case 3: var = (var & 0x00ffffff) | ((val) << 24); break; \
}
void s3_accel_write(uint32_t addr, uint8_t val, void *p)
{
s3_t *s3 = (s3_t *)p;
// pclog("Write S3 accel %08X %02X\n", addr, val);
if (s3->packed_mmio)
{
int addr_lo = addr & 1;
switch (addr & 0xfffe)
{
case 0x8100: addr = 0x82e8; break; /*ALT_CURXY*/
case 0x8102: addr = 0x86e8; break;
case 0x8104: addr = 0x82ea; break; /*ALT_CURXY2*/
case 0x8106: addr = 0x86ea; break;
case 0x8108: addr = 0x8ae8; break; /*ALT_STEP*/
case 0x810a: addr = 0x8ee8; break;
case 0x810c: addr = 0x8aea; break; /*ALT_STEP2*/
case 0x810e: addr = 0x8eea; break;
case 0x8110: addr = 0x92e8; break; /*ALT_ERR*/
case 0x8112: addr = 0x92ee; break;
case 0x8118: addr = 0x9ae8; break; /*ALT_CMD*/
case 0x811a: addr = 0x9aea; break;
case 0x811c: addr = 0x9ee8; break; /*SHORT_STROKE*/
case 0x8120: case 0x8122: /*BKGD_COLOR*/
WRITE8(addr, s3->accel.bkgd_color, val);
return;
case 0x8124: case 0x8126: /*FRGD_COLOR*/
WRITE8(addr, s3->accel.frgd_color, val);
return;
case 0x8128: case 0x812a: /*WRT_MASK*/
WRITE8(addr, s3->accel.wrt_mask, val);
return;
case 0x812c: case 0x812e: /*RD_MASK*/
WRITE8(addr, s3->accel.rd_mask, val);
return;
case 0x8130: case 0x8132: /*COLOR_CMP*/
WRITE8(addr, s3->accel.color_cmp, val);
return;
case 0x8134: addr = 0xb6e8; break; /*ALT_MIX*/
case 0x8136: addr = 0xbae8; break;
case 0x8138: /*SCISSORS_T*/
WRITE8(addr & 1, s3->accel.multifunc[1], val);
return;
case 0x813a: /*SCISSORS_L*/
WRITE8(addr & 1, s3->accel.multifunc[2], val);
return;
case 0x813c: /*SCISSORS_B*/
WRITE8(addr & 1, s3->accel.multifunc[3], val);
return;
case 0x813e: /*SCISSORS_R*/
WRITE8(addr & 1, s3->accel.multifunc[4], val);
return;
case 0x8140: /*PIX_CNTL*/
WRITE8(addr & 1, s3->accel.multifunc[0xa], val);
return;
case 0x8142: /*MULT_MISC2*/
WRITE8(addr & 1, s3->accel.multifunc[0xd], val);
return;
case 0x8144: /*MULT_MISC*/
WRITE8(addr & 1, s3->accel.multifunc[0xe], val);
return;
case 0x8146: /*READ_SEL*/
WRITE8(addr & 1, s3->accel.multifunc[0xf], val);
return;
case 0x8148: /*ALT_PCNT*/
WRITE8(addr & 1, s3->accel.multifunc[0], val);
return;
case 0x814a: addr = 0x96e8; break;
case 0x814c: addr = 0x96ea; break;
case 0x8168: addr = 0xeae8; break;
case 0x816a: addr = 0xeaea; break;
}
addr |= addr_lo;
}
if (addr & 0x8000)
s3_accel_out(addr & 0xffff, val, p);
{
s3_accel_out(addr & 0xffff, val, p);
}
else
{
if (s3->accel.cmd & 0x100)
@ -819,8 +938,8 @@ void s3_accel_write_w(uint32_t addr, uint16_t val, void *p)
// pclog("Write S3 accel w %08X %04X\n", addr, val);
if (addr & 0x8000)
{
s3_accel_out( addr & 0xffff, val, p);
s3_accel_out((addr & 0xffff) + 1, val >> 8, p);
s3_accel_write(addr, val, p);
s3_accel_write(addr + 1, val >> 8, p);
}
else
{
@ -844,10 +963,10 @@ void s3_accel_write_l(uint32_t addr, uint32_t val, void *p)
// pclog("Write S3 accel l %08X %08X\n", addr, val);
if (addr & 0x8000)
{
s3_accel_out( addr & 0xffff, val, p);
s3_accel_out((addr & 0xffff) + 1, val >> 8, p);
s3_accel_out((addr & 0xffff) + 2, val >> 16, p);
s3_accel_out((addr & 0xffff) + 3, val >> 24, p);
s3_accel_write(addr, val, p);
s3_accel_write(addr + 1, val >> 8, p);
s3_accel_write(addr + 2, val >> 16, p);
s3_accel_write(addr + 3, val >> 24, p);
}
else
{
@ -1531,78 +1650,37 @@ void s3_hwcursor_draw(svga_t *svga, int displine)
}
uint8_t s3_pci_read(int func, int addr, void *p)
static void s3_io_remove(s3_t *s3)
{
s3_t *s3 = (s3_t *)p;
svga_t *svga = &s3->svga;
// pclog("S3 PCI read %08X\n", addr);
switch (addr)
{
case 0x00: return 0x33; /*'S3'*/
case 0x01: return 0x53;
case 0x02: return s3->id_ext;
case 0x03: return 0x88;
case 0x04: return 0x03; /*Respond to IO and memory accesses*/
case 0x07: return 1 << 1; /*Medium DEVSEL timing*/
case 0x08: return 0; /*Revision ID*/
case 0x09: return 0; /*Programming interface*/
case 0x0a: return 0x01; /*Supports VGA interface*/
case 0x0b: return 0x03;
case 0x10: return 0x00; /*Linear frame buffer address*/
case 0x11: return 0x00;
case 0x12: return svga->crtc[0x5a] & 0x80;
case 0x13: return svga->crtc[0x59];
case 0x30: return 0x01; /*BIOS ROM address*/
case 0x31: return 0x00;
case 0x32: return 0x0C;
case 0x33: return 0x00;
}
return 0;
}
void s3_pci_write(int func, int addr, uint8_t val, void *p)
{
s3_t *s3 = (s3_t *)p;
svga_t *svga = &s3->svga;
switch (addr)
{
case 0x12:
svga->crtc[0x5a] = val & 0x80;
s3_updatemapping(s3);
break;
case 0x13:
svga->crtc[0x59] = val;
s3_updatemapping(s3);
break;
}
}
static void *s3_init()
{
s3_t *s3 = malloc(sizeof(s3_t));
svga_t *svga = &s3->svga;
memset(s3, 0, sizeof(s3_t));
io_removehandler(0x03c0, 0x0020, s3_in, NULL, NULL, s3_out, NULL, NULL, s3);
mem_mapping_add(&s3->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &s3->svga);
mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3);
mem_mapping_disable(&s3->mmio_mapping);
io_removehandler(0x42e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x46e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x4ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x82e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x86e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x92e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x96e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xa2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xa6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xaae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xaee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xb2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xb6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xbae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xbee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xe2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
}
svga_init(&s3->svga, s3, 1 << 22, /*4mb - 864 supports 8mb but buggy VESA driver reports 0mb*/
s3_recalctimings,
s3_in, s3_out,
s3_hwcursor_draw);
static void s3_io_set(s3_t *s3)
{
s3_io_remove(s3);
io_sethandler(0x03c0, 0x0020, s3_in, NULL, NULL, s3_out, NULL, NULL, s3);
svga->crtc[0x36] = 1 | (2 << 2) | (1 << 4) | (4 << 5);
svga->crtc[0x37] = 1 | (7 << 5);
io_sethandler(0x42e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x46e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
@ -1624,31 +1702,149 @@ static void *s3_init()
io_sethandler(0xbae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xbee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xe2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
}
uint8_t s3_pci_read(int func, int addr, void *p)
{
s3_t *s3 = (s3_t *)p;
svga_t *svga = &s3->svga;
// pclog("S3 PCI read %08X\n", addr);
switch (addr)
{
case 0x00: return 0x33; /*'S3'*/
case 0x01: return 0x53;
case 0x02: return s3->id_ext;
case 0x03: return 0x88;
case PCI_REG_COMMAND:
return s3->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
case 0x07: return 1 << 1; /*Medium DEVSEL timing*/
case 0x08: return 0; /*Revision ID*/
case 0x09: return 0; /*Programming interface*/
case 0x0a: return 0x01; /*Supports VGA interface*/
case 0x0b: return 0x03;
case 0x10: return 0x00; /*Linear frame buffer address*/
case 0x11: return 0x00;
case 0x12: return svga->crtc[0x5a] & 0x80;
case 0x13: return svga->crtc[0x59];
case 0x30: return s3->pci_regs[0x30] & 0x01; /*BIOS ROM address*/
case 0x31: return 0x00;
case 0x32: return s3->pci_regs[0x32];
case 0x33: return s3->pci_regs[0x33];
}
return 0;
}
void s3_pci_write(int func, int addr, uint8_t val, void *p)
{
s3_t *s3 = (s3_t *)p;
svga_t *svga = &s3->svga;
pclog("s3_pci_write: addr=%02x val=%02x\n", addr, val);
switch (addr)
{
case PCI_REG_COMMAND:
s3->pci_regs[PCI_REG_COMMAND] = val & 0x27;
if (val & PCI_COMMAND_IO)
s3_io_set(s3);
else
s3_io_remove(s3);
s3_updatemapping(s3);
break;
case 0x12:
svga->crtc[0x5a] = val & 0x80;
s3_updatemapping(s3);
break;
case 0x13:
svga->crtc[0x59] = val;
s3_updatemapping(s3);
break;
case 0x30: case 0x32: case 0x33:
s3->pci_regs[addr] = val;
if (s3->pci_regs[0x30] & 0x01)
{
uint32_t addr = (s3->pci_regs[0x32] << 16) | (s3->pci_regs[0x33] << 24);
pclog("S3 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&s3->bios_rom.mapping, addr, 0x8000);
}
else
{
pclog("S3 bios_rom disabled\n");
mem_mapping_disable(&s3->bios_rom.mapping);
}
return;
}
}
static void *s3_init(char *bios_fn)
{
s3_t *s3 = malloc(sizeof(s3_t));
svga_t *svga = &s3->svga;
memset(s3, 0, sizeof(s3_t));
rom_init(&s3->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&s3->bios_rom.mapping);
mem_mapping_add(&s3->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, 0, &s3->svga);
mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, NULL, 0, s3);
mem_mapping_disable(&s3->mmio_mapping);
svga_init(&s3->svga, s3, 1 << 22, /*4mb - 864 supports 8mb but buggy VESA driver reports 0mb*/
s3_recalctimings,
s3_in, s3_out,
s3_hwcursor_draw);
svga->crtc[0x36] = 1 | (2 << 2) | (1 << 4) | (4 << 5);
svga->crtc[0x37] = 1 | (7 << 5);
s3_io_set(s3);
pci_add(s3_pci_read, s3_pci_write, s3);
s3->pci_regs[0x04] = 7;
s3->pci_regs[0x30] = 0x00;
s3->pci_regs[0x32] = 0x0c;
s3->pci_regs[0x33] = 0x00;
return s3;
}
void *s3_bahamas64_init()
{
s3_t *s3 = s3_init();
s3_t *s3 = s3_init("roms/bahamas64.bin");
s3->id = 0xc1; /*Vision864P*/
s3->id_ext = 0xc1; /*Trio64*/
s3->id_ext = 0xc1;
s3->packed_mmio = 0;
s3->getclock = sdac_getclock;
s3->getclock_p = &s3->ramdac;
return s3;
}
int s3_bahamas64_available()
{
return rom_present("roms/bahamas64.bin");
}
void *s3_9fx_init()
{
s3_t *s3 = s3_init();
s3_t *s3 = s3_init("roms/s3_764.bin");
s3->id = 0xe1;
s3->id_ext = 0x11; /*Trio64*/
s3->id = 0xe1; /*Trio64*/
s3->id_ext = 0x11;
s3->packed_mmio = 1;
s3->getclock = s3_trio64_getclock;
s3->getclock_p = s3;
@ -1656,6 +1852,12 @@ void *s3_9fx_init()
return s3;
}
int s3_9fx_available()
{
return rom_present("roms/s3_764.bin");
}
void s3_close(void *p)
{
s3_t *s3 = (s3_t *)p;
@ -1692,7 +1894,7 @@ device_t s3_bahamas64_device =
0,
s3_bahamas64_init,
s3_close,
NULL,
s3_bahamas64_available,
s3_speed_changed,
s3_force_redraw,
s3_add_status_info
@ -1704,7 +1906,7 @@ device_t s3_9fx_device =
0,
s3_9fx_init,
s3_close,
NULL,
s3_9fx_available,
s3_speed_changed,
s3_force_redraw,
s3_add_status_info

1011
src/vid_s3_virge.c
View file

File diff suppressed because it is too large Load diff

2
src/vid_svga.c
View file

@ -641,7 +641,7 @@ int svga_init(svga_t *svga, void *p, int memsize,
svga->hwcursor_draw = hwcursor_draw;
// _svga_recalctimings(svga);
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga);
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL, 0, svga);
timer_add(svga_poll, &svga->vidtime, TIMER_ALWAYS_ENABLED, svga);
vramp = svga->vram;

2
src/vid_tandy.c
View file

@ -667,7 +667,7 @@ void *tandy_init()
q_filt[c] = 512.0 * sin((3.14 * (tandy_tint + c * 4) / 16.0) - 33.0 / 180.0);
}
timer_add(tandy_poll, &tandy->vidtime, TIMER_ALWAYS_ENABLED, tandy);
mem_mapping_add(&tandy->mapping, 0xb8000, 0x08000, tandy_read, NULL, NULL, tandy_write, NULL, NULL, tandy);
mem_mapping_add(&tandy->mapping, 0xb8000, 0x08000, tandy_read, NULL, NULL, tandy_write, NULL, NULL, NULL, 0, tandy);
io_sethandler(0x03d0, 0x0010, tandy_in, NULL, NULL, tandy_out, NULL, NULL, tandy);
io_sethandler(0x00a0, 0x0001, tandy_in, NULL, NULL, tandy_out, NULL, NULL, tandy);
return tandy;

35
src/vid_tgui9440.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_svga_render.h"
@ -15,6 +16,8 @@ typedef struct tgui_t
mem_mapping_t linear_mapping;
mem_mapping_t accel_mapping;
rom_t bios_rom;
svga_t svga;
struct
@ -462,37 +465,20 @@ void tgui_pci_write(int func, int addr, uint8_t val, void *p)
}
}
void *tgui8900d_init()
{
tgui_t *tgui = malloc(sizeof(tgui_t));
memset(tgui, 0, sizeof(tgui_t));
svga_init(&tgui->svga, tgui, 1 << 20, /*1mb - chip supports 2mb, but drivers are buggy*/
tgui_recalctimings,
tgui_in, tgui_out,
NULL);
mem_mapping_add(&tgui->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tgui->svga);
mem_mapping_add(&tgui->accel_mapping, 0xbc000, 0x4000, tgui_accel_read, tgui_accel_read_w, tgui_accel_read_l, tgui_accel_write, tgui_accel_write_w, tgui_accel_write_l, tgui);
mem_mapping_disable(&tgui->linear_mapping);
mem_mapping_disable(&tgui->accel_mapping);
io_sethandler(0x03c0, 0x0020, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
return tgui;
}
void *tgui9440_init()
{
tgui_t *tgui = malloc(sizeof(tgui_t));
memset(tgui, 0, sizeof(tgui_t));
rom_init(&tgui->bios_rom, "roms/9440.vbi", 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&tgui->svga, tgui, 1 << 21, /*2mb*/
tgui_recalctimings,
tgui_in, tgui_out,
tgui_hwcursor_draw);
mem_mapping_add(&tgui->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tgui->svga);
mem_mapping_add(&tgui->accel_mapping, 0xbc000, 0x4000, tgui_accel_read, tgui_accel_read_w, tgui_accel_read_l, tgui_accel_write, tgui_accel_write_w, tgui_accel_write_l, tgui);
mem_mapping_add(&tgui->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, 0, &tgui->svga);
mem_mapping_add(&tgui->accel_mapping, 0xbc000, 0x4000, tgui_accel_read, tgui_accel_read_w, tgui_accel_read_l, tgui_accel_write, tgui_accel_write_w, tgui_accel_write_l, NULL, 0, tgui);
mem_mapping_disable(&tgui->accel_mapping);
io_sethandler(0x03c0, 0x0020, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
@ -503,6 +489,11 @@ void *tgui9440_init()
return tgui;
}
static int tgui9440_available()
{
return rom_present("roms/9440.vbi");
}
void tgui_close(void *p)
{
tgui_t *tgui = (tgui_t *)p;
@ -1127,7 +1118,7 @@ device_t tgui9440_device =
0,
tgui9440_init,
tgui_close,
NULL,
tgui9440_available,
tgui_speed_changed,
tgui_force_redraw,
tgui_add_status_info

19
src/vid_tvga.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_svga_render.h"
@ -17,6 +18,8 @@ typedef struct tvga_t
svga_t svga;
tkd8001_ramdac_t ramdac;
rom_t bios_rom;
uint8_t tvga_3d8, tvga_3d9;
int oldmode;
@ -48,7 +51,10 @@ void tvga_out(uint16_t addr, uint8_t val, void *p)
break;
case 0xd:
if (tvga->oldmode)
tvga->oldctrl2 = val;
{
tvga->oldctrl2 = val;
svga->vrammask = (val & 0x10) ? 0xfffff : 0x3ffff;
}
else
tvga->newctrl2 = val;
break;
@ -92,7 +98,7 @@ void tvga_out(uint16_t addr, uint8_t val, void *p)
if (svga->crtcreg <= 7 && svga->crtc[0x11] & 0x80) return;
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
// if (svga->crtcreg != 0xE && svga->crtcreg != 0xF) pclog("CRTC R%02X = %02X\n", svga->crtcreg, val);
// if (svga->crtcreg != 0xC && svga->crtcreg != 0xE && svga->crtcreg != 0xF) pclog("CRTC R%02X = %02X %04X:%04X\n", svga->crtcreg, val, CS, pc);
if (old != val)
{
if (svga->crtcreg < 0xE || svga->crtcreg > 0x10)
@ -240,6 +246,8 @@ void *tvga8900d_init()
{
tvga_t *tvga = malloc(sizeof(tvga_t));
memset(tvga, 0, sizeof(tvga_t));
rom_init(&tvga->bios_rom, "roms/trident.bin", 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&tvga->svga, tvga, 1 << 20, /*1mb - chip supports 2mb, but drivers are buggy*/
tvga_recalctimings,
@ -251,6 +259,11 @@ void *tvga8900d_init()
return tvga;
}
static int tvga8900d_available()
{
return rom_present("roms/trident.bin");
}
void tvga_close(void *p)
{
tvga_t *tvga = (tvga_t *)p;
@ -287,7 +300,7 @@ device_t tvga8900d_device =
0,
tvga8900d_init,
tvga_close,
NULL,
tvga8900d_available,
tvga_speed_changed,
tvga_force_redraw,
tvga_add_status_info

12
src/vid_vga.c
View file

@ -4,6 +4,7 @@
#include "device.h"
#include "io.h"
#include "mem.h"
#include "rom.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_vga.h"
@ -11,6 +12,8 @@
typedef struct vga_t
{
svga_t svga;
rom_t bios_rom;
} vga_t;
void vga_out(uint16_t addr, uint8_t val, void *p)
@ -78,6 +81,8 @@ void *vga_init()
vga_t *vga = malloc(sizeof(vga_t));
memset(vga, 0, sizeof(vga_t));
rom_init(&vga->bios_rom, "roms/ibm_vga.bin", 0xc0000, 0x8000, 0x7fff, 0, 0);
svga_init(&vga->svga, vga, 1 << 18, /*256kb*/
NULL,
vga_in, vga_out,
@ -91,6 +96,11 @@ void *vga_init()
return vga;
}
static int vga_available()
{
return rom_present("roms/ibm_vga.bin");
}
void vga_close(void *p)
{
vga_t *vga = (vga_t *)p;
@ -127,7 +137,7 @@ device_t vga_device =
DEVICE_NOT_WORKING,
vga_init,
vga_close,
NULL,
vga_available,
vga_speed_changed,
vga_force_redraw,
vga_add_status_info

6
src/vid_voodoo.c
View file

@ -734,9 +734,9 @@ void voodoo_init()
voodoo_make_dither();
pci_add(voodoo_pci_read, voodoo_pci_write, NULL);
mem_mapping_add(&voodoo.mmio_mapping, 0, 0, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL);
mem_mapping_add(&voodoo.fb_mapping, 0, 0, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL);
mem_mapping_add(&voodoo.tex_mapping, 0, 0, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL);
mem_mapping_add(&voodoo.mmio_mapping, 0, 0, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL, 0, NULL);
mem_mapping_add(&voodoo.fb_mapping, 0, 0, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL, 0, NULL);
mem_mapping_add(&voodoo.tex_mapping, 0, 0, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL, 0, NULL);
voodoo.fb_mem = malloc(2 * 1024 * 1024);
voodoo.tex_mem = malloc(2 * 1024 * 1024);

11
src/video.c
View file

@ -8,6 +8,7 @@
#include "vid_svga.h"
#include "io.h"
#include "cpu.h"
#include "rom.h"
#include "timer.h"
#include "vid_ati18800.h"
@ -229,11 +230,15 @@ void video_init()
return;
case ROM_PC2086:
case ROM_PC3086:
device_add(&paradise_pvga1a_device);
device_add(&paradise_pvga1a_pc2086_device);
return;
case ROM_PC3086:
device_add(&paradise_pvga1a_pc3086_device);
return;
case ROM_MEGAPC:
device_add(&paradise_wd90c11_device);
device_add(&paradise_wd90c11_megapc_device);
return;
case ROM_ACER386:

15
src/win.c
View file

@ -386,18 +386,14 @@ int WINAPI WinMain (HINSTANCE hThisInstance,
}
}
d = gfxcard;
for (c = 0; c < 18; c++)
{
gfxcard = c;
gfx_present[c] = mem_load_video_bios();
}
gfxcard = d;
c = mem_load_video_bios();
if (!c)
gfx_present[c] = video_card_available(video_old_to_new(c));
if (!video_card_available(video_old_to_new(gfxcard)))
{
if (romset!=-1) MessageBox(hwnd,"Configured video BIOS not available.\nDefaulting to available romset.","PCem error",MB_OK);
for (c=0;c<18;c++)
for (c = 17; c >= 0; c--)
{
if (gfx_present[c])
{
@ -783,7 +779,6 @@ BOOL CALLBACK configdlgproc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPara
sound_card_current = temp_sound_card_current;
mem_resize();
mem_load_video_bios();
loadbios();
resetpchard();
}