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Fixed compiler warnings for Windows builds.

Browse source 
Added -Werror to Windows makefiles.
This commit is contained in:
SarahW 2017-04-11 19:34:41 +01:00
commit 2b892d2a7a
168 changed files with 1927 additions and 1963 deletions
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5
src/386.c
View file

@ -2,11 +2,13 @@
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
#include "ibm.h" #include "ibm.h"
#include "386.h"
#include "x86.h" #include "x86.h"
#include "x87.h" #include "x87.h"
#include "mem.h" #include "mem.h"
#include "cpu.h" #include "cpu.h"
#include "fdc.h" #include "fdc.h"
#include "pic.h"
#include "timer.h" #include "timer.h"
#include "386_common.h" #include "386_common.h"
@ -231,7 +233,7 @@ void exec386(int cycs)
/* testr[8]=flags;*/ /* testr[8]=flags;*/
// oldcs2=oldcs; // oldcs2=oldcs;
// oldpc2=oldpc; // oldpc2=oldpc;
opcode_realstart:
oldcs=CS; oldcs=CS;
cpu_state.oldpc = cpu_state.pc; cpu_state.oldpc = cpu_state.pc;
oldcpl=CPL; oldcpl=CPL;
@ -242,7 +244,6 @@ dontprint=0;
cpu_state.ea_seg = &_ds; cpu_state.ea_seg = &_ds;
cpu_state.ssegs = 0; cpu_state.ssegs = 0;
opcodestart:
fetchdat = fastreadl(cs + cpu_state.pc); fetchdat = fastreadl(cs + cpu_state.pc);
if (!cpu_state.abrt) if (!cpu_state.abrt)

13
src/386.h
View file

@ -1,2 +1,15 @@
extern void cpu_386_flags_extract(); extern void cpu_386_flags_extract();
extern void cpu_386_flags_rebuild(); extern void cpu_386_flags_rebuild();
void pmodeint(int num, int soft);
void loadcscall(uint16_t seg);
void loadcsjmp(uint16_t seg, uint32_t oxpc);
void pmoderetf(int is32, uint16_t off);
void pmodeiret(int is32);
void x86_int_sw(int num);
int divl(uint32_t val);
int idivl(int32_t val);
int rep386(int fv);

5
src/386_common.h
View file

@ -13,6 +13,7 @@ extern uint16_t ea_rseg;
#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFC) writememll(s,a,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v #define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFC) writememll(s,a,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFF8) writememql(s,a,v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v #define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFF8) writememql(s,a,v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
int checkio(int port);
#define check_io_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \ #define check_io_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
{ \ { \
@ -75,7 +76,7 @@ static inline uint8_t fastreadb(uint32_t a)
return *((uint8_t *)&pccache2[a]); return *((uint8_t *)&pccache2[a]);
t = getpccache(a); t = getpccache(a);
if (cpu_state.abrt) if (cpu_state.abrt)
return; return 0;
pccache = a >> 12; pccache = a >> 12;
pccache2 = t; pccache2 = t;
return *((uint8_t *)&pccache2[a]); return *((uint8_t *)&pccache2[a]);
@ -94,7 +95,7 @@ static inline uint16_t fastreadw(uint32_t a)
if ((a>>12)==pccache) return *((uint16_t *)&pccache2[a]); if ((a>>12)==pccache) return *((uint16_t *)&pccache2[a]);
t = getpccache(a); t = getpccache(a);
if (cpu_state.abrt) if (cpu_state.abrt)
return; return 0;
pccache = a >> 12; pccache = a >> 12;
pccache2 = t; pccache2 = t;

8
src/386_dynarec.c
View file

@ -2,6 +2,7 @@
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
#include "ibm.h" #include "ibm.h"
#include "386.h"
#include "x86.h" #include "x86.h"
#include "x86_ops.h" #include "x86_ops.h"
#include "x87.h" #include "x87.h"
@ -9,6 +10,7 @@
#include "codegen.h" #include "codegen.h"
#include "cpu.h" #include "cpu.h"
#include "fdc.h" #include "fdc.h"
#include "pic.h"
#include "timer.h" #include "timer.h"
#include "386_common.h" #include "386_common.h"
@ -261,7 +263,6 @@ void x86_int_sw(int num)
void x86illegal() void x86illegal()
{ {
uint16_t addr;
// pclog("x86 illegal %04X %08X %04X:%08X %02X\n",msw,cr0,CS,pc,opcode); // pclog("x86 illegal %04X %08X %04X:%08X %02X\n",msw,cr0,CS,pc,opcode);
// if (output) // if (output)
@ -363,7 +364,6 @@ int rep386(int fv)
uint8_t temp2; uint8_t temp2;
uint16_t tempw,tempw2,of; uint16_t tempw,tempw2,of;
uint32_t ipc = cpu_state.oldpc;//pc-1; uint32_t ipc = cpu_state.oldpc;//pc-1;
uint32_t oldds;
uint32_t rep32 = cpu_state.op32; uint32_t rep32 = cpu_state.op32;
uint32_t templ,templ2; uint32_t templ,templ2;
int tempz; int tempz;
@ -1376,7 +1376,6 @@ void exec386_dynarec(int cycs)
cpu_state.ea_seg = &_ds; cpu_state.ea_seg = &_ds;
cpu_state.ssegs = 0; cpu_state.ssegs = 0;
opcodestart:
fetchdat = fastreadl(cs + cpu_state.pc); fetchdat = fastreadl(cs + cpu_state.pc);
// if (!fetchdat) // if (!fetchdat)
// fatal("Dead with cache off\n"); // fatal("Dead with cache off\n");
@ -1509,7 +1508,6 @@ inrecomp=0;
} }
else if (valid_block && !cpu_state.abrt) else if (valid_block && !cpu_state.abrt)
{ {
uint32_t start_page = cpu_state.pc >> 12;
uint32_t start_pc = cpu_state.pc; uint32_t start_pc = cpu_state.pc;
// pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]); // pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]);
@ -1532,7 +1530,6 @@ inrecomp=0;
cpu_state.ea_seg = &_ds; cpu_state.ea_seg = &_ds;
cpu_state.ssegs = 0; cpu_state.ssegs = 0;
opcodestart_compile:
fetchdat = fastreadl(cs + cpu_state.pc); fetchdat = fastreadl(cs + cpu_state.pc);
// if (fetchdat == 0xffffffff) // if (fetchdat == 0xffffffff)
// fatal("Dead ffffffff\n"); // fatal("Dead ffffffff\n");
@ -1592,7 +1589,6 @@ inrecomp=0;
else if (!cpu_state.abrt) else if (!cpu_state.abrt)
{ {
/*Mark block but do not recompile*/ /*Mark block but do not recompile*/
uint32_t start_page = cpu_state.pc >> 12;
uint32_t start_pc = cpu_state.pc; uint32_t start_pc = cpu_state.pc;
// pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]); // pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]);

2
src/386_dynarec_ops.c
View file

@ -1,10 +1,12 @@
#include "ibm.h" #include "ibm.h"
#include "cpu.h" #include "cpu.h"
#include "386.h"
#include "x86.h" #include "x86.h"
#include "x86_ops.h" #include "x86_ops.h"
#include "x87.h" #include "x87.h"
#include "x86_flags.h" #include "x86_flags.h"
#include "mem.h" #include "mem.h"
#include "pic.h"
#include "codegen.h" #include "codegen.h"
#define CPU_BLOCK_END() cpu_block_end = 1 #define CPU_BLOCK_END() cpu_block_end = 1

18
src/808x.c
View file

@ -9,9 +9,12 @@
4 clocks - fetch mod/rm 4 clocks - fetch mod/rm
2 clocks - fetch opcode 1 2 clocks - execute 2 clocks - fetch opcode 1 2 clocks - execute
2 clocks - fetch opcode 2 etc*/ 2 clocks - fetch opcode 2 etc*/
#include <unistd.h>
#include <stdio.h> #include <stdio.h>
#include "ibm.h" #include "ibm.h"
#include "x86_ops.h"
#include "codegen.h"
#include "cpu.h" #include "cpu.h"
#include "keyboard.h" #include "keyboard.h"
#include "mem.h" #include "mem.h"
@ -19,6 +22,7 @@
#include "pic.h" #include "pic.h"
#include "timer.h" #include "timer.h"
#include "x86.h" #include "x86.h"
#include "x87.h"
int xt_cpu_multi; int xt_cpu_multi;
int nmi = 0; int nmi = 0;
@ -93,7 +97,6 @@ void writememl(uint32_t s, uint32_t a, uint32_t v)
} }
void dumpregs();
uint16_t oldcs; uint16_t oldcs;
int oldcpl; int oldcpl;
@ -436,12 +439,6 @@ static inline void seteaw(uint16_t val)
} }
} }
#define getr8(r) ((r & 4) ? cpu_state.regs[r & 3].b.h : cpu_state.regs[r & 3].b.l)
#define setr8(r,v) if (r & 4) cpu_state.regs[r & 3].b.h = v; \
else cpu_state.regs[r & 3].b.l = v;
/*Flags*/ /*Flags*/
uint8_t znptable8[256]; uint8_t znptable8[256];
uint16_t znptable16[65536]; uint16_t znptable16[65536];
@ -500,7 +497,7 @@ int indump = 0;
void dumpregs() void dumpregs()
{ {
int c,d=0,e=0,ff; int c,d=0,e=0;
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
FILE *f; FILE *f;
if (indump) return; if (indump) return;
@ -647,7 +644,6 @@ void resetx86()
makeznptable(); makeznptable();
resetreadlookup(); resetreadlookup();
makemod1table(); makemod1table();
resetmcr();
FETCHCLEAR(); FETCHCLEAR();
x87_reset(); x87_reset();
cpu_set_edx(); cpu_set_edx();
@ -2782,8 +2778,8 @@ void execx86(int cycs)
c--; c--;
cycles-=4; cycles-=4;
} }
if (temp) flags|=C_FLAG; if (templ) flags|=C_FLAG;
else flags&=~C_FLAG; else flags&=~C_FLAG;
seteaw(tempw); seteaw(tempw);
if ((flags&C_FLAG)^(tempw>>15)) flags|=V_FLAG; if ((flags&C_FLAG)^(tempw>>15)) flags|=V_FLAG;
else flags&=~V_FLAG; else flags&=~V_FLAG;

2
src/Makefile.mingw
View file

@ -2,7 +2,7 @@ VPATH = . dosbox resid-fp
CPP = g++.exe CPP = g++.exe
CC = gcc.exe CC = gcc.exe
WINDRES = windres.exe WINDRES = windres.exe
CFLAGS = -O3 -march=i686 -fomit-frame-pointer -msse2 -mstackrealign CFLAGS = -O3 -march=i686 -fomit-frame-pointer -msse2 -mstackrealign -Wall -Werror -fno-strict-aliasing
OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acer386sx.o ali1429.o amstrad.o cdrom-ioctl.o cdrom-iso.o \ OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acer386sx.o ali1429.o amstrad.o cdrom-ioctl.o cdrom-iso.o \
codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86.o compaq.o config.o cpu.o dac.o \ codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86.o compaq.o config.o cpu.o dac.o \
device.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o hdd.o hdd_esdi.o headland.o i430lx.o i430fx.o \ device.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o hdd.o hdd_esdi.o headland.o i430lx.o i430fx.o \

2
src/Makefile.mingw64
View file

@ -2,7 +2,7 @@ VPATH = . dosbox resid-fp
CPP = g++.exe CPP = g++.exe
CC = gcc.exe CC = gcc.exe
WINDRES = windres.exe WINDRES = windres.exe
CFLAGS = -O3 -fomit-frame-pointer -msse2 CFLAGS = -O3 -fomit-frame-pointer -msse2 -Wall -Werror -fno-strict-aliasing
OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acer386sx.o ali1429.o amstrad.o cdrom-ioctl.o cdrom-iso.o \ OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acer386sx.o ali1429.o amstrad.o cdrom-ioctl.o cdrom-iso.o \
codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86-64.o compaq.o config.o cpu.o dac.o \ codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86-64.o compaq.o config.o cpu.o dac.o \
device.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o hdd.o hdd_esdi.o headland.o i430lx.o i430fx.o \ device.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o hdd.o hdd_esdi.o headland.o i430lx.o i430fx.o \

2
src/ali1429.c
View file

@ -43,8 +43,6 @@ static void ali1429_recalc()
void ali1429_write(uint16_t port, uint8_t val, void *priv) void ali1429_write(uint16_t port, uint8_t val, void *priv)
{ {
int c;
if (!(port & 1)) if (!(port & 1))
ali1429_index = val; ali1429_index = val;
else else

1
src/ali1429.h
View file

@ -1 +1,2 @@
void ali1429_init(); void ali1429_init();
void ali1429_reset();

2
src/amstrad.c
View file

@ -1,4 +1,6 @@
#include <stdlib.h>
#include "ibm.h" #include "ibm.h"
#include "dac.h"
#include "io.h" #include "io.h"
#include "keyboard.h" #include "keyboard.h"
#include "lpt.h" #include "lpt.h"

42
src/cdrom-ioctl.c
View file

@ -29,7 +29,6 @@ static ATAPI ioctl_atapi;
static uint32_t last_block = 0; static uint32_t last_block = 0;
static uint32_t cdrom_capacity = 0; static uint32_t cdrom_capacity = 0;
static int ioctl_inited = 0;
static char ioctl_path[8]; static char ioctl_path[8];
void ioctl_close(void); void ioctl_close(void);
static HANDLE hIOCTL; static HANDLE hIOCTL;
@ -235,7 +234,7 @@ static int ioctl_ready(void)
// pclog("Ready? %i\n",cdrom_drive); // pclog("Ready? %i\n",cdrom_drive);
if (!cdrom_drive) return 0; if (!cdrom_drive) return 0;
ioctl_open(0); ioctl_open(0);
temp=DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&ltoc,sizeof(ltoc),&size,NULL); temp=DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&ltoc,sizeof(ltoc),(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
if (!temp) if (!temp)
return 0; return 0;
@ -275,7 +274,7 @@ static int ioctl_get_last_block(unsigned char starttrack, int msf, int maxlen, i
ioctl_cd_state = CD_STOPPED; ioctl_cd_state = CD_STOPPED;
ioctl_open(0); ioctl_open(0);
DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&lbtoc,sizeof(lbtoc),&size,NULL); DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&lbtoc,sizeof(lbtoc),(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
tocvalid = 1; tocvalid = 1;
for (c = 0; c <= lbtoc.LastTrack; c++) for (c = 0; c <= lbtoc.LastTrack; c++)
@ -295,7 +294,7 @@ static int ioctl_medium_changed(void)
CDROM_TOC ltoc; CDROM_TOC ltoc;
if (!cdrom_drive) return 0; /* This will be handled by the not ready handler instead. */ if (!cdrom_drive) return 0; /* This will be handled by the not ready handler instead. */
ioctl_open(0); ioctl_open(0);
temp=DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&ltoc,sizeof(ltoc),&size,NULL); temp=DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&ltoc,sizeof(ltoc),(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
if (!temp) if (!temp)
return 0; /* Drive empty, a not ready handler matter, not disc change. */ return 0; /* Drive empty, a not ready handler matter, not disc change. */
@ -331,7 +330,7 @@ static uint8_t ioctl_getcurrentsubchannel(uint8_t *b, int msf)
insub.Format = IOCTL_CDROM_CURRENT_POSITION; insub.Format = IOCTL_CDROM_CURRENT_POSITION;
ioctl_open(0); ioctl_open(0);
DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_Q_CHANNEL,&insub,sizeof(insub),&sub,sizeof(sub),&size,NULL); DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_Q_CHANNEL,&insub,sizeof(insub),&sub,sizeof(sub),(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
if (ioctl_cd_state == CD_PLAYING || ioctl_cd_state == CD_PAUSED) if (ioctl_cd_state == CD_PLAYING || ioctl_cd_state == CD_PAUSED)
@ -413,7 +412,7 @@ static void ioctl_eject(void)
if (!cdrom_drive) return; if (!cdrom_drive) return;
ioctl_cd_state = CD_STOPPED; ioctl_cd_state = CD_STOPPED;
ioctl_open(0); ioctl_open(0);
DeviceIoControl(hIOCTL,IOCTL_STORAGE_EJECT_MEDIA,NULL,0,NULL,0,&size,NULL); DeviceIoControl(hIOCTL,IOCTL_STORAGE_EJECT_MEDIA,NULL,0,NULL,0,(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
} }
@ -423,7 +422,7 @@ static void ioctl_load(void)
if (!cdrom_drive) return; if (!cdrom_drive) return;
ioctl_cd_state = CD_STOPPED; ioctl_cd_state = CD_STOPPED;
ioctl_open(0); ioctl_open(0);
DeviceIoControl(hIOCTL,IOCTL_STORAGE_LOAD_MEDIA,NULL,0,NULL,0,&size,NULL); DeviceIoControl(hIOCTL,IOCTL_STORAGE_LOAD_MEDIA,NULL,0,NULL,0,(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
cdrom_capacity = ioctl_get_last_block(0, 0, 4096, 0); cdrom_capacity = ioctl_get_last_block(0, 0, 4096, 0);
} }
@ -441,7 +440,6 @@ static int ioctl_readsector(uint8_t *b, int sector)
LARGE_INTEGER pos; LARGE_INTEGER pos;
BOOL status; BOOL status;
long size; long size;
int c;
if (!cdrom_drive) if (!cdrom_drive)
return -1; return -1;
@ -453,7 +451,7 @@ static int ioctl_readsector(uint8_t *b, int sector)
pos.QuadPart=sector*2048; pos.QuadPart=sector*2048;
ioctl_open(0); ioctl_open(0);
SetFilePointer(hIOCTL,pos.LowPart,&pos.HighPart,FILE_BEGIN); SetFilePointer(hIOCTL,pos.LowPart,&pos.HighPart,FILE_BEGIN);
status = ReadFile(hIOCTL,b,2048,&size,NULL); status = ReadFile(hIOCTL,b,2048,(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
/*If the read failed, try again using SPTI*/ /*If the read failed, try again using SPTI*/
@ -497,14 +495,6 @@ static int ioctl_readsector(uint8_t *b, int sector)
return !status; return !status;
} }
static void lba_to_msf(uint8_t *buf, int lba)
{
lba += 150;
buf[0] = (lba / 75) / 60;
buf[1] = (lba / 75) % 60;
buf[2] = lba % 75;
}
static int is_track_audio(uint32_t pos) static int is_track_audio(uint32_t pos)
{ {
int c; int c;
@ -539,17 +529,15 @@ static int ioctl_is_track_audio(uint32_t pos, int ismsf)
static void ioctl_readsector_raw(uint8_t *b, int sector) static void ioctl_readsector_raw(uint8_t *b, int sector)
{ {
LARGE_INTEGER pos;
long size; long size;
uint32_t temp;
if (!cdrom_drive) return; if (!cdrom_drive) return;
if (ioctl_cd_state == CD_PLAYING) if (ioctl_cd_state == CD_PLAYING)
return; return;
ioctl_cd_state = CD_STOPPED; ioctl_cd_state = CD_STOPPED;
pos.QuadPart=sector*2048;
ioctl_open(0); ioctl_open(0);
DeviceIoControl(hIOCTL, IOCTL_CDROM_RAW_READ, NULL, 0, b, 1, &size, NULL); DeviceIoControl(hIOCTL, IOCTL_CDROM_RAW_READ, NULL, 0, b, 1, (LPDWORD)&size, NULL);
ioctl_close(); ioctl_close();
} }
@ -562,7 +550,7 @@ static int ioctl_readtoc(unsigned char *b, unsigned char starttrack, int msf, in
if (!cdrom_drive) return 0; if (!cdrom_drive) return 0;
ioctl_cd_state = CD_STOPPED; ioctl_cd_state = CD_STOPPED;
ioctl_open(0); ioctl_open(0);
DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&toc,sizeof(toc),&size,NULL); DeviceIoControl(hIOCTL,IOCTL_CDROM_READ_TOC, NULL,0,&toc,sizeof(toc),(LPDWORD)&size,NULL);
ioctl_close(); ioctl_close();
tocvalid=1; tocvalid=1;
// pclog("Read TOC done! %i\n",single); // pclog("Read TOC done! %i\n",single);
@ -628,7 +616,7 @@ static int ioctl_readtoc_session(unsigned char *b, int msf, int maxlen)
uint32_t temp; uint32_t temp;
CDROM_READ_TOC_EX toc_ex; CDROM_READ_TOC_EX toc_ex;
CDROM_TOC_SESSION_DATA toc; CDROM_TOC_SESSION_DATA toc;
if (!cdrom_drive) return; if (!cdrom_drive) return 0;
ioctl_cd_state = CD_STOPPED; ioctl_cd_state = CD_STOPPED;
memset(&toc_ex,0,sizeof(toc_ex)); memset(&toc_ex,0,sizeof(toc_ex));
memset(&toc,0,sizeof(toc)); memset(&toc,0,sizeof(toc));
@ -668,9 +656,7 @@ static int ioctl_readtoc_raw(unsigned char *b, int maxlen)
{ {
int len=4; int len=4;
int size; int size;
uint32_t temp;
int i; int i;
int BytesRead = 0;
CDROM_READ_TOC_EX toc_ex; CDROM_READ_TOC_EX toc_ex;
CDROM_TOC_FULL_TOC_DATA toc; CDROM_TOC_FULL_TOC_DATA toc;
if (!cdrom_drive) return 0; if (!cdrom_drive) return 0;
@ -715,7 +701,7 @@ static uint32_t ioctl_size()
static int ioctl_status() static int ioctl_status()
{ {
if (!(ioctl_ready) && (cdrom_drive <= 0)) if (!(ioctl_ready()) && (cdrom_drive <= 0))
return CD_STATUS_EMPTY; return CD_STATUS_EMPTY;
switch(ioctl_cd_state) switch(ioctl_cd_state)
@ -727,12 +713,12 @@ static int ioctl_status()
case CD_STOPPED: case CD_STOPPED:
return CD_STATUS_STOPPED; return CD_STATUS_STOPPED;
} }
return CD_STATUS_STOPPED;
} }
void ioctl_reset() void ioctl_reset()
{ {
CDROM_TOC ltoc; CDROM_TOC ltoc;
int temp;
long size; long size;
if (!cdrom_drive) if (!cdrom_drive)
@ -742,7 +728,7 @@ void ioctl_reset()
} }
ioctl_open(0); ioctl_open(0);
temp = DeviceIoControl(hIOCTL, IOCTL_CDROM_READ_TOC, NULL, 0, &ltoc, sizeof(ltoc), &size, NULL); DeviceIoControl(hIOCTL, IOCTL_CDROM_READ_TOC, NULL, 0, &ltoc, sizeof(ltoc), (LPDWORD)&size, NULL);
ioctl_close(); ioctl_close();
toc = ltoc; toc = ltoc;

2
src/cdrom-ioctl.h
View file

@ -8,5 +8,7 @@ extern int ioctl_open(char d);
extern void ioctl_reset(); extern void ioctl_reset();
extern void ioctl_close(); extern void ioctl_close();
void ioctl_set_drive(char d); void ioctl_set_drive(char d);
void ioctl_audio_callback(int16_t *output, int len);
void ioctl_audio_stop();
#endif /* ! CDROM_IOCTL_H */ #endif /* ! CDROM_IOCTL_H */

9
src/cdrom-iso.c
View file

@ -15,8 +15,6 @@ void iso_close(void);
static FILE *iso_image = NULL; static FILE *iso_image = NULL;
static int iso_changed = 0; static int iso_changed = 0;
static uint32_t iso_cd_pos = 0, iso_cd_end = 0;
void iso_audio_callback(int16_t *output, int len) void iso_audio_callback(int16_t *output, int len)
{ {
memset(output, 0, len * 2); memset(output, 0, len * 2);
@ -28,12 +26,6 @@ void iso_audio_stop()
pclog("iso_audio_stop stub\n"); pclog("iso_audio_stop stub\n");
} }
static int get_track_nr(uint32_t pos)
{
pclog("get_track_nr stub\n");
return 0;
}
static void iso_playaudio(uint32_t pos, uint32_t len, int ismsf) static void iso_playaudio(uint32_t pos, uint32_t len, int ismsf)
{ {
pclog("iso_playaudio stub\n"); pclog("iso_playaudio stub\n");
@ -118,7 +110,6 @@ static void lba_to_msf(uint8_t *buf, int lba)
static void iso_readsector_raw(uint8_t *b, int sector) static void iso_readsector_raw(uint8_t *b, int sector)
{ {
uint32_t temp;
if (!cdrom_drive) return; if (!cdrom_drive) return;
fseek(iso_image, sector*2048, SEEK_SET); fseek(iso_image, sector*2048, SEEK_SET);
fread(b+16, 2048, 1, iso_image); fread(b+16, 2048, 1, iso_image);

3
src/cdrom-null.c
View file

@ -59,8 +59,9 @@ static void null_load(void)
{ {
} }
static void null_readsector(uint8_t *b, int sector) static int null_readsector(uint8_t *b, int sector)
{ {
return 0;
} }
static void null_readsector_raw(uint8_t *b, int sector) static void null_readsector_raw(uint8_t *b, int sector)

3
src/codegen.h
View file

@ -249,6 +249,7 @@ void codegen_block_init(uint32_t phys_addr);
void codegen_block_remove(); void codegen_block_remove();
void codegen_block_start_recompile(codeblock_t *block); void codegen_block_start_recompile(codeblock_t *block);
void codegen_block_end_recompile(codeblock_t *block); void codegen_block_end_recompile(codeblock_t *block);
void codegen_block_end();
void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc); void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc);
void codegen_generate_seg_restore(); void codegen_generate_seg_restore();
void codegen_set_op32(); void codegen_set_op32();
@ -308,7 +309,7 @@ static inline void addbyte(uint8_t val)
static inline void addword(uint16_t val) static inline void addword(uint16_t val)
{ {
*(uint16_t *)&codeblock[block_current].data[block_pos] = val; *(uint16_t *)(void *)&codeblock[block_current].data[block_pos] = val;
block_pos += 2; block_pos += 2;
if (block_pos >= BLOCK_MAX) if (block_pos >= BLOCK_MAX)
{ {

348
src/codegen_ops_arith.h
View file

@ -2,15 +2,15 @@ static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{ {
int host_reg; int host_reg;
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7); host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, 1); ADD_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg); STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -21,15 +21,15 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{ {
int host_reg; int host_reg;
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7); host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, 1); ADD_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg); STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -40,15 +40,15 @@ static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{ {
int host_reg; int host_reg;
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7); host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, 1); SUB_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg); STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -59,15 +59,15 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{ {
int host_reg; int host_reg;
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7); host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, 1); SUB_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg); STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -93,12 +93,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_CHECK_WRITE(target_seg); \ MEM_CHECK_WRITE(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \ dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \
} \ } \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \ src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \ STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \ STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \ op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \ STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) \ if (writeback) \
{ \ { \
if ((fetchdat & 0xc0) == 0xc0) \ if ((fetchdat & 0xc0) == 0xc0) \
@ -133,12 +133,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_CHECK_WRITE_W(target_seg); \ MEM_CHECK_WRITE_W(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \ dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \
} \ } \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \ src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \ STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \ STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \ op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \ STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) \ if (writeback) \
{ \ { \
if ((fetchdat & 0xc0) == 0xc0) \ if ((fetchdat & 0xc0) == 0xc0) \
@ -173,12 +173,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_CHECK_WRITE_L(target_seg); \ MEM_CHECK_WRITE_L(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \ dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \
} \ } \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \ src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \ STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \ STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \ op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \ STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) \ if (writeback) \
{ \ { \
if ((fetchdat & 0xc0) == 0xc0) \ if ((fetchdat & 0xc0) == 0xc0) \
@ -215,11 +215,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \ } \
\ \
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \ dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \ STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \ STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \ op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \ STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \ if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \ else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \ RELEASE_REG(src_reg); \
@ -244,11 +244,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \ } \
\ \
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \ dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \ STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \ STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \ op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \ STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \ if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \ else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \ RELEASE_REG(src_reg); \
@ -273,11 +273,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \ } \
\ \
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \ dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \ STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \ STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \ op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \ STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \ if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \ else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \ RELEASE_REG(src_reg); \
@ -308,11 +308,11 @@ static uint32_t ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
} }
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg); dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg); RELEASE_REG(dst_reg);
RELEASE_REG(src_reg); RELEASE_REG(src_reg);
@ -336,11 +336,11 @@ static uint32_t ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
} }
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg); dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg); RELEASE_REG(dst_reg);
RELEASE_REG(src_reg); RELEASE_REG(src_reg);
@ -364,11 +364,11 @@ static uint32_t ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
} }
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg); dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg); RELEASE_REG(dst_reg);
RELEASE_REG(src_reg); RELEASE_REG(src_reg);
@ -392,12 +392,12 @@ static uint32_t ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0; dst_reg = 0;
} }
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg); dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg); RELEASE_REG(dst_reg);
RELEASE_REG(src_reg); RELEASE_REG(src_reg);
@ -420,12 +420,12 @@ static uint32_t ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0; dst_reg = 0;
} \ } \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg); dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg); RELEASE_REG(dst_reg);
RELEASE_REG(src_reg); RELEASE_REG(src_reg);
@ -448,12 +448,12 @@ static uint32_t ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0; dst_reg = 0;
} }
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg); dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg); RELEASE_REG(dst_reg);
RELEASE_REG(src_reg); RELEASE_REG(src_reg);
@ -466,11 +466,11 @@ static uint32_t ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{ {
int host_reg = LOAD_REG_B(REG_AL); int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff); ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg); STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -480,11 +480,11 @@ static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{ {
int host_reg = LOAD_REG_W(REG_AX); int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff); ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg); STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -494,12 +494,12 @@ static uint32_t ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{ {
int host_reg = LOAD_REG_L(REG_EAX); int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc); fetchdat = fastreadl(cs + op_pc);
ADD_HOST_REG_IMM(host_reg, fetchdat); ADD_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg); STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -510,11 +510,11 @@ static uint32_t ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{ {
int host_reg = LOAD_REG_B(REG_AL); int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff); host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg); RELEASE_REG(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -524,11 +524,11 @@ static uint32_t ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{ {
int host_reg = LOAD_REG_W(REG_AX); int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff); host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg); RELEASE_REG(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -538,12 +538,12 @@ static uint32_t ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{ {
int host_reg = LOAD_REG_L(REG_EAX); int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc); fetchdat = fastreadl(cs + op_pc);
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat); host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg); RELEASE_REG(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -554,11 +554,11 @@ static uint32_t ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{ {
int host_reg = LOAD_REG_B(REG_AL); int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff); SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg); STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -568,11 +568,11 @@ static uint32_t ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{ {
int host_reg = LOAD_REG_W(REG_AX); int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff); SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg); STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -582,12 +582,12 @@ static uint32_t ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{ {
int host_reg = LOAD_REG_L(REG_EAX); int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc); fetchdat = fastreadl(cs + op_pc);
SUB_HOST_REG_IMM(host_reg, fetchdat); SUB_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg); STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1; codegen_flags_changed = 1;
@ -598,7 +598,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
{ {
int host_reg; int host_reg;
uint32_t imm; uint32_t imm;
x86seg *target_seg; x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) if ((fetchdat & 0x30) == 0x10)
return 0; return 0;
@ -629,38 +629,38 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*ADD*/ case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, imm); ADD_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD8);
break; break;
case 0x08: /*OR*/ case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm); OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
break; break;
case 0x20: /*AND*/ case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffffff00); AND_HOST_REG_IMM(host_reg, imm | 0xffffff00);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
break; break;
case 0x28: /*SUB*/ case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, imm); SUB_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
break; break;
case 0x30: /*XOR*/ case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm); XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
break; break;
case 0x38: /*CMP*/ case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, imm); host_reg = CMP_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
break; break;
} }
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) if ((fetchdat & 0x38) != 0x38)
{ {
if ((fetchdat & 0xc0) != 0xc0) if ((fetchdat & 0xc0) != 0xc0)
@ -684,7 +684,7 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{ {
int host_reg; int host_reg;
uint32_t imm; uint32_t imm;
x86seg *target_seg; x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) if ((fetchdat & 0x30) == 0x10)
return 0; return 0;
@ -715,38 +715,38 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*ADD*/ case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm); ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
break; break;
case 0x08: /*OR*/ case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm); OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break; break;
case 0x20: /*AND*/ case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000); AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break; break;
case 0x28: /*SUB*/ case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm); SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break; break;
case 0x30: /*XOR*/ case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm); XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break; break;
case 0x38: /*CMP*/ case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm); host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break; break;
} }
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) if ((fetchdat & 0x38) != 0x38)
{ {
if ((fetchdat & 0xc0) != 0xc0) if ((fetchdat & 0xc0) != 0xc0)
@ -769,7 +769,7 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{ {
int host_reg; int host_reg;
uint32_t imm; uint32_t imm;
x86seg *target_seg; x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) if ((fetchdat & 0x30) == 0x10)
return 0; return 0;
@ -799,38 +799,38 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*ADD*/ case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm); ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
break; break;
case 0x08: /*OR*/ case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm); OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break; break;
case 0x20: /*AND*/ case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm); AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break; break;
case 0x28: /*SUB*/ case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm); SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break; break;
case 0x30: /*XOR*/ case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm); XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break; break;
case 0x38: /*CMP*/ case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm); host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break; break;
} }
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) if ((fetchdat & 0x38) != 0x38)
{ {
if ((fetchdat & 0xc0) != 0xc0) if ((fetchdat & 0xc0) != 0xc0)
@ -854,7 +854,7 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{ {
int host_reg; int host_reg;
uint32_t imm; uint32_t imm;
x86seg *target_seg; x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) if ((fetchdat & 0x30) == 0x10)
return 0; return 0;
@ -888,38 +888,38 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*ADD*/ case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm); ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
break; break;
case 0x08: /*OR*/ case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm); OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break; break;
case 0x20: /*AND*/ case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000); AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break; break;
case 0x28: /*SUB*/ case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm); SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break; break;
case 0x30: /*XOR*/ case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm); XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break; break;
case 0x38: /*CMP*/ case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm); host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break; break;
} }
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) if ((fetchdat & 0x38) != 0x38)
{ {
if ((fetchdat & 0xc0) != 0xc0) if ((fetchdat & 0xc0) != 0xc0)
@ -942,7 +942,7 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{ {
int host_reg; int host_reg;
uint32_t imm; uint32_t imm;
x86seg *target_seg; x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) if ((fetchdat & 0x30) == 0x10)
return 0; return 0;
@ -976,38 +976,38 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*ADD*/ case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm); ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
break; break;
case 0x08: /*OR*/ case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm); OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break; break;
case 0x20: /*AND*/ case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm); AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break; break;
case 0x28: /*SUB*/ case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm); SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break; break;
case 0x30: /*XOR*/ case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm); XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break; break;
case 0x38: /*CMP*/ case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm); host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break; break;
} }
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) if ((fetchdat & 0x38) != 0x38)
{ {
if ((fetchdat & 0xc0) != 0xc0) if ((fetchdat & 0xc0) != 0xc0)

2
src/codegen_ops_fpu.h
View file

@ -491,7 +491,7 @@ static uint32_t ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
int host_reg; int host_reg;
FP_ENTER(); FP_ENTER();
host_reg = LOAD_VAR_W(&cpu_state.npxs); host_reg = LOAD_VAR_W((uintptr_t)&cpu_state.npxs);
STORE_REG_TARGET_W_RELEASE(host_reg, REG_AX); STORE_REG_TARGET_W_RELEASE(host_reg, REG_AX);
return op_pc; return op_pc;

20
src/codegen_ops_jump.h
View file

@ -75,16 +75,16 @@ static uint32_t ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return op_pc+1; return op_pc+1;
} }
static int BRANCH_COND_B(int pc_offset, uint32_t op_pc, uint32_t offset, int not) static void BRANCH_COND_B(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{ {
CALL_FUNC(CF_SET); CALL_FUNC((uintptr_t)CF_SET);
if (not) if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else else
TEST_NONZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_NONZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
} }
static int BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not) static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{ {
int host_reg; int host_reg;
@ -122,7 +122,7 @@ static int BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not
break; break;
case FLAGS_UNKNOWN: case FLAGS_UNKNOWN:
CALL_FUNC(ZF_SET); CALL_FUNC((uintptr_t)ZF_SET);
if (not) if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else else
@ -131,25 +131,25 @@ static int BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not
} }
} }
static int BRANCH_COND_O(int pc_offset, uint32_t op_pc, uint32_t offset, int not) static void BRANCH_COND_O(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{ {
CALL_FUNC(VF_SET); CALL_FUNC((uintptr_t)VF_SET);
if (not) if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else else
TEST_NONZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_NONZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
} }
static int BRANCH_COND_P(int pc_offset, uint32_t op_pc, uint32_t offset, int not) static void BRANCH_COND_P(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{ {
CALL_FUNC(PF_SET); CALL_FUNC((uintptr_t)PF_SET);
if (not) if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else else
TEST_NONZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_NONZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
} }
static int BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not) static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{ {
int host_reg; int host_reg;
@ -204,7 +204,7 @@ static int BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not
break; break;
case FLAGS_UNKNOWN: case FLAGS_UNKNOWN:
CALL_FUNC(NF_SET); CALL_FUNC((uintptr_t)NF_SET);
if (not) if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt); TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else else

62
src/codegen_ops_misc.h
View file

@ -27,13 +27,13 @@ static uint32_t ropSTI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int host_reg; int host_reg;
if ((fetchdat & 0x30) != 0x00) if ((fetchdat & 0x30) != 0x00)
return 0; return 0;
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_B(fetchdat & 7); host_reg = LOAD_REG_B(fetchdat & 7);
@ -50,18 +50,18 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*INC*/ case 0x00: /*INC*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, 1); ADD_HOST_REG_IMM_B(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
break; break;
case 0x08: /*DEC*/ case 0x08: /*DEC*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, 1); SUB_HOST_REG_IMM_B(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC8); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
break; break;
} }
@ -79,14 +79,14 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
static uint32_t codegen_temp; static uint32_t codegen_temp;
static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int host_reg; int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08)) if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0; return 0;
if ((fetchdat & 0x30) == 0x00) if ((fetchdat & 0x30) == 0x00)
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_W(fetchdat & 7); host_reg = LOAD_REG_W(fetchdat & 7);
@ -111,11 +111,11 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*INC*/ case 0x00: /*INC*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, 1); ADD_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_W_RELEASE(host_reg); STORE_REG_W_RELEASE(host_reg);
else else
@ -126,11 +126,11 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
codegen_flags_changed = 1; codegen_flags_changed = 1;
return op_pc + 1; return op_pc + 1;
case 0x08: /*DEC*/ case 0x08: /*DEC*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, 1); SUB_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC16); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_W_RELEASE(host_reg); STORE_REG_W_RELEASE(host_reg);
else else
@ -168,17 +168,18 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-2); SP_MODIFY(-2);
return op_pc + 1; return op_pc + 1;
} }
return 0;
} }
static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int host_reg; int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08)) if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0; return 0;
if ((fetchdat & 0x30) == 0x00) if ((fetchdat & 0x30) == 0x00)
CALL_FUNC(flags_rebuild_c); CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_L(fetchdat & 7); host_reg = LOAD_REG_L(fetchdat & 7);
@ -203,11 +204,11 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*INC*/ case 0x00: /*INC*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, 1); ADD_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_L_RELEASE(host_reg); STORE_REG_L_RELEASE(host_reg);
else else
@ -218,11 +219,11 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
codegen_flags_changed = 1; codegen_flags_changed = 1;
return op_pc + 1; return op_pc + 1;
case 0x08: /*DEC*/ case 0x08: /*DEC*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, 1); SUB_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC32); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg); STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_L_RELEASE(host_reg); STORE_REG_L_RELEASE(host_reg);
else else
@ -260,4 +261,5 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-4); SP_MODIFY(-4);
return op_pc + 1; return op_pc + 1;
} }
return 0;
} }

12
src/codegen_ops_mov.h
View file

@ -512,22 +512,22 @@ static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
switch (fetchdat & 0x38) switch (fetchdat & 0x38)
{ {
case 0x00: /*ES*/ case 0x00: /*ES*/
host_reg = LOAD_VAR_WL(&ES); host_reg = LOAD_VAR_WL((uintptr_t)&ES);
break; break;
case 0x08: /*CS*/ case 0x08: /*CS*/
host_reg = LOAD_VAR_WL(&CS); host_reg = LOAD_VAR_WL((uintptr_t)&CS);
break; break;
case 0x18: /*DS*/ case 0x18: /*DS*/
host_reg = LOAD_VAR_WL(&DS); host_reg = LOAD_VAR_WL((uintptr_t)&DS);
break; break;
case 0x10: /*SS*/ case 0x10: /*SS*/
host_reg = LOAD_VAR_WL(&SS); host_reg = LOAD_VAR_WL((uintptr_t)&SS);
break; break;
case 0x20: /*FS*/ case 0x20: /*FS*/
host_reg = LOAD_VAR_WL(&FS); host_reg = LOAD_VAR_WL((uintptr_t)&FS);
break; break;
case 0x28: /*GS*/ case 0x28: /*GS*/
host_reg = LOAD_VAR_WL(&GS); host_reg = LOAD_VAR_WL((uintptr_t)&GS);
break; break;
default: default:
return 0; return 0;

24
src/codegen_ops_shift.h
View file

@ -13,29 +13,29 @@
reg = MEM_LOAD_ADDR_EA_ ## size ## _NO_ABRT(target_seg); \ reg = MEM_LOAD_ADDR_EA_ ## size ## _NO_ABRT(target_seg); \
if (immediate) count = fastreadb(cs + op_pc + 1) & 0x1f; \ if (immediate) count = fastreadb(cs + op_pc + 1) & 0x1f; \
} \ } \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, count); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, count); \
\ \
res_store((uint32_t)&cpu_state.flags_op1, reg); \ res_store((uintptr_t)&cpu_state.flags_op1, reg); \
\ \
switch (fetchdat & 0x38) \ switch (fetchdat & 0x38) \
{ \ { \
case 0x20: case 0x30: /*SHL*/ \ case 0x20: case 0x30: /*SHL*/ \
SHL_ ## size ## _IMM(reg, count); \ SHL_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SHL ## size2); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SHL ## size2); \
break; \ break; \
\ \
case 0x28: /*SHR*/ \ case 0x28: /*SHR*/ \
SHR_ ## size ## _IMM(reg, count); \ SHR_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SHR ## size2); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SHR ## size2); \
break; \ break; \
\ \
case 0x38: /*SAR*/ \ case 0x38: /*SAR*/ \
SAR_ ## size ## _IMM(reg, count); \ SAR_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SAR ## size2); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SAR ## size2); \
break; \ break; \
} \ } \
\ \
res_store((uint32_t)&cpu_state.flags_res, reg); \ res_store((uintptr_t)&cpu_state.flags_res, reg); \
if ((fetchdat & 0xc0) == 0xc0) \ if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_ ## size ## _RELEASE(reg); \ STORE_REG_ ## size ## _RELEASE(reg); \
else \ else \
@ -46,7 +46,7 @@
static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int count; int count;
int reg; int reg;
@ -59,7 +59,7 @@ static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
} }
static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int count; int count;
int reg; int reg;
@ -72,7 +72,7 @@ static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
} }
static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int count; int count;
int reg; int reg;
@ -86,7 +86,7 @@ static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int count = 1; int count = 1;
int reg; int reg;
@ -99,7 +99,7 @@ static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
} }
static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int count = 1; int count = 1;
int reg; int reg;
@ -112,7 +112,7 @@ static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
} }
static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
x86seg *target_seg; x86seg *target_seg = NULL;
int count = 1; int count = 1;
int reg; int reg;

14
src/codegen_ops_stack.h
View file

@ -85,8 +85,6 @@ static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
int host_reg;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0); LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&_ss); MEM_LOAD_ADDR_EA_W(&_ss);
@ -97,8 +95,6 @@ static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} }
static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
int host_reg;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0); LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&_ss); MEM_LOAD_ADDR_EA_L(&_ss);
@ -110,8 +106,6 @@ static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
int host_reg;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0); LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&_ss); MEM_LOAD_ADDR_EA_W(&_ss);
@ -122,8 +116,6 @@ static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} }
static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
int host_reg;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0); LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&_ss); MEM_LOAD_ADDR_EA_L(&_ss);
@ -136,7 +128,6 @@ static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
uint16_t offset = fetchdat & 0xffff; uint16_t offset = fetchdat & 0xffff;
int host_reg;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0); LOAD_STACK_TO_EA(0);
@ -149,7 +140,6 @@ static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{ {
uint16_t offset = fetchdat & 0xffff; uint16_t offset = fetchdat & 0xffff;
int host_reg;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0); LOAD_STACK_TO_EA(0);
@ -254,8 +244,6 @@ ROP_PUSH_SEG(SS)
#define ROP_POP_SEG(seg, rseg) \ #define ROP_POP_SEG(seg, rseg) \
static uint32_t ropPOP_ ## seg ## _16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \ static uint32_t ropPOP_ ## seg ## _16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \ { \
int host_reg; \
\
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
LOAD_STACK_TO_EA(0); \ LOAD_STACK_TO_EA(0); \
MEM_LOAD_ADDR_EA_W(&_ss); \ MEM_LOAD_ADDR_EA_W(&_ss); \
@ -266,8 +254,6 @@ static uint32_t ropPOP_ ## seg ## _16(uint8_t opcode, uint32_t fetchdat, uint32_
} \ } \
static uint32_t ropPOP_ ## seg ## _32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \ static uint32_t ropPOP_ ## seg ## _32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \ { \
int host_reg; \
\
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \ STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
LOAD_STACK_TO_EA(0); \ LOAD_STACK_TO_EA(0); \
MEM_LOAD_ADDR_EA_W(&_ss); \ MEM_LOAD_ADDR_EA_W(&_ss); \

845
src/codegen_ops_x86-64.h
View file

File diff suppressed because it is too large Load diff

995
src/codegen_ops_x86.h
View file

File diff suppressed because it is too large Load diff

2
src/codegen_timing_486.c
View file

@ -254,7 +254,7 @@ static uint8_t last_prefix;
static inline int COUNT(int *c, int op_32) static inline int COUNT(int *c, int op_32)
{ {
if ((uintptr_t)c <= 10000) if ((uintptr_t)c <= 10000)
return (int)c; return (int)(uintptr_t)c;
if (((uintptr_t)c & ~0xffff) == (-1 & ~0xffff)) if (((uintptr_t)c & ~0xffff) == (-1 & ~0xffff))
{ {
if (op_32 & 0x100) if (op_32 & 0x100)

2
src/codegen_timing_686.c
View file

@ -855,7 +855,7 @@ void codegen_timing_686_prefix(uint8_t prefix, uint32_t fetchdat)
void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32) void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{ {
int *timings; uint32_t *timings;
int mod3 = ((fetchdat & 0xc0) == 0xc0); int mod3 = ((fetchdat & 0xc0) == 0xc0);
int bit8 = !(opcode & 1); int bit8 = !(opcode & 1);

2
src/codegen_timing_pentium.c
View file

@ -888,7 +888,7 @@ void codegen_timing_pentium_prefix(uint8_t prefix, uint32_t fetchdat)
void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32) void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{ {
int *timings; uint32_t *timings;
int mod3 = ((fetchdat & 0xc0) == 0xc0); int mod3 = ((fetchdat & 0xc0) == 0xc0);
int bit8 = !(opcode & 1); int bit8 = !(opcode & 1);

2
src/codegen_timing_winchip.c
View file

@ -254,7 +254,7 @@ static uint8_t last_prefix;
static inline int COUNT(int *c, int op_32) static inline int COUNT(int *c, int op_32)
{ {
if ((uintptr_t)c <= 10000) if ((uintptr_t)c <= 10000)
return (int)c; return (int)(uintptr_t)c;
if (((uintptr_t)c & ~0xffff) == (-1 & ~0xffff)) if (((uintptr_t)c & ~0xffff) == (-1 & ~0xffff))
{ {
if (op_32 & 0x100) if (op_32 & 0x100)

70
src/codegen_x86-64.c
View file

@ -61,7 +61,6 @@ static int last_ssegs;
void codegen_init() void codegen_init()
{ {
int c;
#ifdef __linux__ #ifdef __linux__
void *start; void *start;
size_t len; size_t len;
@ -251,7 +250,6 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
void codegen_block_init(uint32_t phys_addr) void codegen_block_init(uint32_t phys_addr)
{ {
codeblock_t *block; codeblock_t *block;
int has_evicted = 0;
page_t *page = &pages[phys_addr >> 12]; page_t *page = &pages[phys_addr >> 12];
if (!page->block) if (!page->block)
@ -292,7 +290,6 @@ void codegen_block_init(uint32_t phys_addr)
void codegen_block_start_recompile(codeblock_t *block) void codegen_block_start_recompile(codeblock_t *block)
{ {
int has_evicted = 0;
page_t *page = &pages[block->phys >> 12]; page_t *page = &pages[block->phys >> 12];
if (!page->block) if (!page->block)
@ -475,14 +472,14 @@ void codegen_block_end_recompile(codeblock_t *block)
{ {
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/ addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d); addbyte(0x6d);
addbyte(cpu_state_offset(_cycles)); addbyte((uint8_t)cpu_state_offset(_cycles));
addlong((uint32_t)codegen_block_cycles); addlong((uint32_t)codegen_block_cycles);
} }
if (codegen_block_ins) if (codegen_block_ins)
{ {
addbyte(0x81); /*ADD $codegen_block_ins,ins*/ addbyte(0x81); /*ADD $codegen_block_ins,ins*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(cpu_recomp_ins)); addbyte((uint8_t)cpu_state_offset(cpu_recomp_ins));
addlong(codegen_block_ins); addlong(codegen_block_ins);
} }
#if 0 #if 0
@ -529,29 +526,6 @@ void codegen_flush()
return; return;
} }
static int opcode_conditional_jump[256] =
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, /*00*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*10*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*30*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*60*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*70*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*d0*/
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*f0*/
};
static int opcode_modrm[256] = static int opcode_modrm[256] =
{ {
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
@ -611,13 +585,13 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
{ {
addbyte(0xC7); /*MOVL $0,(ssegs)*/ addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
addlong((fetchdat >> 8) & 0xffff); addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2; (*op_pc) += 2;
} }
else else
{ {
int base_reg, index_reg; int base_reg = 0, index_reg = 0;
switch (cpu_rm) switch (cpu_rm)
{ {
@ -721,7 +695,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
} }
addbyte(0x89); /*MOV eaaddr, EAX*/ addbyte(0x89); /*MOV eaaddr, EAX*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
if (mod1seg[cpu_rm] == &ss && !op_ssegs) if (mod1seg[cpu_rm] == &ss && !op_ssegs)
op_ea_seg = &_ss; op_ea_seg = &_ss;
@ -876,7 +850,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte(0x89); /*MOV eaaddr, EAX*/ addbyte(0x89); /*MOV eaaddr, EAX*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
} }
else else
{ {
@ -887,7 +861,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
new_eaaddr = fastreadl(cs + (*op_pc) + 1); new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/ addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
addlong(new_eaaddr); addlong(new_eaaddr);
(*op_pc) += 4; (*op_pc) += 4;
return op_ea_seg; return op_ea_seg;
@ -918,14 +892,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
} }
addbyte(0x89); /*MOV eaaddr, EAX*/ addbyte(0x89); /*MOV eaaddr, EAX*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
} }
else else
{ {
addbyte(0x44); /*MOV eaaddr, base_reg*/ addbyte(0x44); /*MOV eaaddr, base_reg*/
addbyte(0x89); addbyte(0x89);
addbyte(0x45 | (base_reg << 3)); addbyte(0x45 | (base_reg << 3));
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
} }
} }
return op_ea_seg; return op_ea_seg;
@ -1093,17 +1067,17 @@ generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32); codegen_timing_opcode(opcode, fetchdat, op_32);
if ((op_table == x86_dynarec_opcodes && if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 || ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
(opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 || (opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 ||
(opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30))) || (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
(op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))) (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
{ {
/*Opcode is likely to cause block to exit, update cycle count*/ /*Opcode is likely to cause block to exit, update cycle count*/
if (codegen_block_cycles) if (codegen_block_cycles)
{ {
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/ addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d); addbyte(0x6d);
addbyte(cpu_state_offset(_cycles)); addbyte((uint8_t)cpu_state_offset(_cycles));
addlong((uint32_t)codegen_block_cycles); addlong((uint32_t)codegen_block_cycles);
codegen_block_cycles = 0; codegen_block_cycles = 0;
} }
@ -1111,7 +1085,7 @@ generate_call:
{ {
addbyte(0x81); /*ADD $codegen_block_ins,ins*/ addbyte(0x81); /*ADD $codegen_block_ins,ins*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(cpu_recomp_ins)); addbyte((uint8_t)cpu_state_offset(cpu_recomp_ins));
addlong(codegen_block_ins); addlong(codegen_block_ins);
codegen_block_ins = 0; codegen_block_ins = 0;
} }
@ -1152,7 +1126,7 @@ generate_call:
last_ssegs = op_ssegs; last_ssegs = op_ssegs;
addbyte(0xC6); /*MOVB $0,(ssegs)*/ addbyte(0xC6); /*MOVB $0,(ssegs)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(ssegs)); addbyte((uint8_t)cpu_state_offset(ssegs));
addbyte(op_ssegs); addbyte(op_ssegs);
} }
//#if 0 //#if 0
@ -1171,7 +1145,7 @@ generate_call:
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/ addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(rm_data.rm_mod_reg_data)); addbyte((uint8_t)cpu_state_offset(rm_data.rm_mod_reg_data));
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16)); addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
op_pc += pc_off; op_pc += pc_off;
@ -1187,25 +1161,25 @@ generate_call:
// last_ea_seg = op_ea_seg; // last_ea_seg = op_ea_seg;
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/ addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(ea_seg)); addbyte((uint8_t)cpu_state_offset(ea_seg));
addlong((uint32_t)op_ea_seg); addlong((uint32_t)(uintptr_t)op_ea_seg);
} }
addbyte(0xC7); /*MOVL [pc],new_pc*/ addbyte(0xC7); /*MOVL [pc],new_pc*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(pc)); addbyte((uint8_t)cpu_state_offset(pc));
addlong(op_pc + pc_off); addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/ addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(oldpc)); addbyte((uint8_t)cpu_state_offset(oldpc));
addlong(old_pc); addlong(old_pc);
if (op_32 != last_op32) if (op_32 != last_op32)
{ {
last_op32 = op_32; last_op32 = op_32;
addbyte(0xC7); /*MOVL $use32,(op32)*/ addbyte(0xC7); /*MOVL $use32,(op32)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(op32)); addbyte((uint8_t)cpu_state_offset(op32));
addlong(op_32); addlong(op_32);
} }
@ -1219,7 +1193,7 @@ generate_call:
addbyte(0x85); /*OR %eax, %eax*/ addbyte(0x85); /*OR %eax, %eax*/
addbyte(0xc0); addbyte(0xc0);
addbyte(0x0F); addbyte(0x85); /*JNZ 0*/ addbyte(0x0F); addbyte(0x85); /*JNZ 0*/
addlong((uint32_t)&block->data[BLOCK_EXIT_OFFSET] - (uint32_t)(&block->data[block_pos + 4])); addlong((uint32_t)(uintptr_t)&block->data[BLOCK_EXIT_OFFSET] - (uint32_t)(uintptr_t)(&block->data[block_pos + 4]));
// call(block, codegen_debug); // call(block, codegen_debug);

2
src/codegen_x86-64.h
View file

@ -17,7 +17,7 @@ enum
OP_RET = 0xc3 OP_RET = 0xc3
}; };
#define NR_HOST_REGS 3 #define NR_HOST_REGS 4
extern int host_reg_mapping[NR_HOST_REGS]; extern int host_reg_mapping[NR_HOST_REGS];
#define NR_HOST_XMM_REGS 7 #define NR_HOST_XMM_REGS 7
extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS]; extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS];

190
src/codegen_x86.c
View file

@ -80,7 +80,7 @@ uint32_t mem_check_write_l;
static uint32_t gen_MEM_LOAD_ADDR_EA_B() static uint32_t gen_MEM_LOAD_ADDR_EA_B()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -115,7 +115,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B()
addbyte(8); addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*MOVZX EAX, AL*/ addbyte(0x0f); /*MOVZX EAX, AL*/
addbyte(0xb6); addbyte(0xb6);
@ -130,7 +130,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B()
static uint32_t gen_MEM_LOAD_ADDR_EA_W() static uint32_t gen_MEM_LOAD_ADDR_EA_W()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -172,7 +172,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W()
addbyte(8); addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*MOVZX EAX, AX*/ addbyte(0x0f); /*MOVZX EAX, AX*/
addbyte(0xb7); addbyte(0xb7);
@ -187,7 +187,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W()
static uint32_t gen_MEM_LOAD_ADDR_EA_L() static uint32_t gen_MEM_LOAD_ADDR_EA_L()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -228,7 +228,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L()
addbyte(8); addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -240,7 +240,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L()
static uint32_t gen_MEM_LOAD_ADDR_EA_Q() static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -285,7 +285,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
addbyte(8); addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -297,7 +297,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
static uint32_t gen_MEM_STORE_ADDR_EA_B() static uint32_t gen_MEM_STORE_ADDR_EA_B()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/ /*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/ addbyte(0x89); /*MOV EBX, ESI*/
@ -333,7 +333,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B()
addbyte(12); addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -345,7 +345,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B()
static uint32_t gen_MEM_STORE_ADDR_EA_W() static uint32_t gen_MEM_STORE_ADDR_EA_W()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/ /*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/ addbyte(0x89); /*MOV EBX, ESI*/
@ -389,7 +389,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W()
addbyte(12); addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -401,7 +401,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W()
static uint32_t gen_MEM_STORE_ADDR_EA_L() static uint32_t gen_MEM_STORE_ADDR_EA_L()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/ /*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/ addbyte(0x89); /*MOV EBX, ESI*/
@ -444,7 +444,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L()
addbyte(12); addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -456,7 +456,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L()
static uint32_t gen_MEM_STORE_ADDR_EA_Q() static uint32_t gen_MEM_STORE_ADDR_EA_Q()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = EBX/ECX, seg = ESI, addr = EAX*/ /*dat = EBX/ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EDX, ESI*/ addbyte(0x89); /*MOV EDX, ESI*/
@ -504,7 +504,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_Q()
addbyte(16); addbyte(16);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -517,7 +517,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_Q()
static char gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_B_NO_ABRT aborted\n"; static char gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_B_NO_ABRT aborted\n";
static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT() static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -553,7 +553,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
#endif #endif
addbyte(0x0f); /*MOVZX ECX, AL*/ addbyte(0x0f); /*MOVZX ECX, AL*/
@ -568,7 +568,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err*/ addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04); addbyte(0x04);
addbyte(0x24); addbyte(0x24);
addlong(gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err); addlong((uint32_t)gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/ addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4])); addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/ /*Should not return!*/
@ -579,7 +579,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
static char gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_W_NO_ABRT aborted\n"; static char gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_W_NO_ABRT aborted\n";
static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT() static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -622,7 +622,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
#endif #endif
addbyte(0x0f); /*MOVZX ECX, AX*/ addbyte(0x0f); /*MOVZX ECX, AX*/
@ -637,7 +637,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err*/ addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04); addbyte(0x04);
addbyte(0x24); addbyte(0x24);
addlong(gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err); addlong((uint32_t)gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/ addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4])); addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/ /*Should not return!*/
@ -648,7 +648,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
static char gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_L_NO_ABRT aborted\n"; static char gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_L_NO_ABRT aborted\n";
static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT() static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/ addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6); addbyte(0xd6);
@ -692,7 +692,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/ addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1); addbyte(1);
@ -705,7 +705,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err*/ addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err*/
addbyte(0x04); addbyte(0x04);
addbyte(0x24); addbyte(0x24);
addlong(gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err); addlong((uint32_t)gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/ addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4])); addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/ /*Should not return!*/
@ -716,7 +716,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_ABRT aborted\n"; static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_ABRT aborted\n";
static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT() static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/ /*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/ addbyte(0x89); /*MOV EBX, ESI*/
@ -753,7 +753,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/ addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1); addbyte(1);
@ -763,7 +763,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err*/ addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04); addbyte(0x04);
addbyte(0x24); addbyte(0x24);
addlong(gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err); addlong((uint32_t)gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/ addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4])); addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/ /*Should not return!*/
@ -774,7 +774,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_ABRT aborted\n"; static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_ABRT aborted\n";
static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT() static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/ /*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/ addbyte(0x89); /*MOV EBX, ESI*/
@ -819,7 +819,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/ addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1); addbyte(1);
@ -829,7 +829,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/ addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04); addbyte(0x04);
addbyte(0x24); addbyte(0x24);
addlong(gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err); addlong((uint32_t)gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/ addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4])); addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/ /*Should not return!*/
@ -840,7 +840,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_ABRT aborted\n"; static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_ABRT aborted\n";
static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT() static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/ /*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/ addbyte(0x89); /*MOV EBX, ESI*/
@ -884,17 +884,17 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/ addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1); addbyte(1);
#endif #endif
addbyte(0xc3); /*RET*/ addbyte(0xc3); /*RET*/
#ifndef RELEASE_BUILD #ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/ addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err*/
addbyte(0x04); addbyte(0x04);
addbyte(0x24); addbyte(0x24);
addlong(gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err); addlong((uint32_t)gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/ addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4])); addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/ /*Should not return!*/
@ -904,7 +904,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
static uint32_t gen_MEM_CHECK_WRITE() static uint32_t gen_MEM_CHECK_WRITE()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/ /*seg = ESI, addr = EAX*/
@ -949,7 +949,7 @@ static uint32_t gen_MEM_CHECK_WRITE()
addbyte(8); addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -966,7 +966,7 @@ static uint32_t gen_MEM_CHECK_WRITE()
static uint32_t gen_MEM_CHECK_WRITE_W() static uint32_t gen_MEM_CHECK_WRITE_W()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/ /*seg = ESI, addr = EAX*/
@ -1030,7 +1030,7 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
addbyte(1); addbyte(1);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -1048,7 +1048,7 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
static uint32_t gen_MEM_CHECK_WRITE_L() static uint32_t gen_MEM_CHECK_WRITE_L()
{ {
uint32_t addr = &codeblock[block_current].data[block_pos]; uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/ /*seg = ESI, addr = EAX*/
@ -1112,7 +1112,7 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
addbyte(3); addbyte(3);
addbyte(0x80); /*CMP abrt, 0*/ addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d); addbyte(0x7d);
addbyte(cpu_state_offset(abrt)); addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0); addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/ addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85); addbyte(0x85);
@ -1130,7 +1130,6 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
void codegen_init() void codegen_init()
{ {
int c;
#ifdef __linux__ #ifdef __linux__
void *start; void *start;
size_t len; size_t len;
@ -1161,7 +1160,7 @@ void codegen_init()
block_current = BLOCK_SIZE; block_current = BLOCK_SIZE;
block_pos = 0; block_pos = 0;
mem_abrt_rout = &codeblock[block_current].data[block_pos]; mem_abrt_rout = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x83); /*ADDL $16+4,%esp*/ addbyte(0x83); /*ADDL $16+4,%esp*/
addbyte(0xC4); addbyte(0xC4);
addbyte(0x10+4); addbyte(0x10+4);
@ -1171,39 +1170,39 @@ void codegen_init()
addbyte(0x5b); /*POP EDX*/ addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/ addbyte(0xC3); /*RET*/
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l = gen_MEM_LOAD_ADDR_EA_L(); mem_load_addr_ea_l = (uint32_t)gen_MEM_LOAD_ADDR_EA_L();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w = gen_MEM_LOAD_ADDR_EA_W(); mem_load_addr_ea_w = (uint32_t)gen_MEM_LOAD_ADDR_EA_W();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b = gen_MEM_LOAD_ADDR_EA_B(); mem_load_addr_ea_b = (uint32_t)gen_MEM_LOAD_ADDR_EA_B();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_q = gen_MEM_LOAD_ADDR_EA_Q(); mem_load_addr_ea_q = (uint32_t)gen_MEM_LOAD_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l = gen_MEM_STORE_ADDR_EA_L(); mem_store_addr_ea_l = (uint32_t)gen_MEM_STORE_ADDR_EA_L();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w = gen_MEM_STORE_ADDR_EA_W(); mem_store_addr_ea_w = (uint32_t)gen_MEM_STORE_ADDR_EA_W();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b = gen_MEM_STORE_ADDR_EA_B(); mem_store_addr_ea_b = (uint32_t)gen_MEM_STORE_ADDR_EA_B();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_q = gen_MEM_STORE_ADDR_EA_Q(); mem_store_addr_ea_q = (uint32_t)gen_MEM_STORE_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b_no_abrt = gen_MEM_LOAD_ADDR_EA_B_NO_ABRT(); mem_load_addr_ea_b_no_abrt = (uint32_t)gen_MEM_LOAD_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b_no_abrt = gen_MEM_STORE_ADDR_EA_B_NO_ABRT(); mem_store_addr_ea_b_no_abrt = (uint32_t)gen_MEM_STORE_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w_no_abrt = gen_MEM_LOAD_ADDR_EA_W_NO_ABRT(); mem_load_addr_ea_w_no_abrt = (uint32_t)gen_MEM_LOAD_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w_no_abrt = gen_MEM_STORE_ADDR_EA_W_NO_ABRT(); mem_store_addr_ea_w_no_abrt = (uint32_t)gen_MEM_STORE_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l_no_abrt = gen_MEM_LOAD_ADDR_EA_L_NO_ABRT(); mem_load_addr_ea_l_no_abrt = (uint32_t)gen_MEM_LOAD_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l_no_abrt = gen_MEM_STORE_ADDR_EA_L_NO_ABRT(); mem_store_addr_ea_l_no_abrt = (uint32_t)gen_MEM_STORE_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_check_write = gen_MEM_CHECK_WRITE(); mem_check_write = (uint32_t)gen_MEM_CHECK_WRITE();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_check_write_w = gen_MEM_CHECK_WRITE_W(); mem_check_write_w = (uint32_t)gen_MEM_CHECK_WRITE_W();
block_pos = (block_pos + 15) & ~15; block_pos = (block_pos + 15) & ~15;
mem_check_write_l = gen_MEM_CHECK_WRITE_L(); mem_check_write_l = (uint32_t)gen_MEM_CHECK_WRITE_L();
asm( asm(
"fstcw %0\n" "fstcw %0\n"
@ -1371,7 +1370,6 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
void codegen_block_init(uint32_t phys_addr) void codegen_block_init(uint32_t phys_addr)
{ {
codeblock_t *block; codeblock_t *block;
int has_evicted = 0;
page_t *page = &pages[phys_addr >> 12]; page_t *page = &pages[phys_addr >> 12];
if (!page->block) if (!page->block)
@ -1412,7 +1410,6 @@ void codegen_block_init(uint32_t phys_addr)
void codegen_block_start_recompile(codeblock_t *block) void codegen_block_start_recompile(codeblock_t *block)
{ {
int has_evicted = 0;
page_t *page = &pages[block->phys >> 12]; page_t *page = &pages[block->phys >> 12];
if (!page->block) if (!page->block)
@ -1569,14 +1566,14 @@ void codegen_block_end_recompile(codeblock_t *block)
{ {
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/ addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d); addbyte(0x6d);
addbyte(cpu_state_offset(_cycles)); addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(codegen_block_cycles); addlong(codegen_block_cycles);
} }
if (codegen_block_ins) if (codegen_block_ins)
{ {
addbyte(0x81); /*ADD $codegen_block_ins,ins*/ addbyte(0x81); /*ADD $codegen_block_ins,ins*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(cpu_recomp_ins)); addbyte((uint8_t)cpu_state_offset(cpu_recomp_ins));
addlong(codegen_block_ins); addlong(codegen_block_ins);
} }
#if 0 #if 0
@ -1616,29 +1613,6 @@ void codegen_flush()
return; return;
} }
static int opcode_conditional_jump[256] =
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, /*00*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*10*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*30*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*60*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*70*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*d0*/
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*f0*/
};
static int opcode_modrm[256] = static int opcode_modrm[256] =
{ {
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
@ -1698,7 +1672,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
{ {
addbyte(0xC7); /*MOVL $0,(ssegs)*/ addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
addlong((fetchdat >> 8) & 0xffff); addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2; (*op_pc) += 2;
} }
@ -1770,7 +1744,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
{ {
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/ addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(regs[sib & 7].l)); addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
} }
break; break;
case 1: case 1:
@ -1779,7 +1753,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addlong(new_eaaddr); addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/ addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(regs[sib & 7].l)); addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
(*op_pc)++; (*op_pc)++;
break; break;
case 2: case 2:
@ -1788,7 +1762,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addlong(new_eaaddr); addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/ addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(regs[sib & 7].l)); addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
(*op_pc) += 4; (*op_pc) += 4;
break; break;
} }
@ -1806,20 +1780,20 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
case 0: case 0:
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/ addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l));
break; break;
case 1: case 1:
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/ addbyte(0x8B); addbyte(0x5D); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/ addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/ addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break; break;
case 2: case 2:
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/ addbyte(0x8B); addbyte(0x5D); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1); addbyte(0xE3); addbyte(2); /*SHL $2,%ebx*/ addbyte(0xC1); addbyte(0xE3); addbyte(2); /*SHL $2,%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/ addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break; break;
case 3: case 3:
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/ addbyte(0x8B); addbyte(0x5D); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1); addbyte(0xE3); addbyte(3); /*SHL $2,%ebx*/ addbyte(0xC1); addbyte(0xE3); addbyte(3); /*SHL $2,%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/ addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break; break;
@ -1835,14 +1809,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
new_eaaddr = fastreadl(cs + (*op_pc) + 1); new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/ addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(eaaddr)); addbyte((uint8_t)cpu_state_offset(eaaddr));
addlong(new_eaaddr); addlong(new_eaaddr);
(*op_pc) += 4; (*op_pc) += 4;
return op_ea_seg; return op_ea_seg;
} }
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/ addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(regs[cpu_rm].l)); addbyte((uint8_t)cpu_state_offset(regs[cpu_rm].l));
// addbyte(0xa1); /*MOVL regs[cpu_rm].l, %eax*/ // addbyte(0xa1); /*MOVL regs[cpu_rm].l, %eax*/
// addlong((uint32_t)&cpu_state.regs[cpu_rm].l); // addlong((uint32_t)&cpu_state.regs[cpu_rm].l);
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l; cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
@ -2034,17 +2008,17 @@ generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32); codegen_timing_opcode(opcode, fetchdat, op_32);
if ((op_table == x86_dynarec_opcodes && if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 || ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
(opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 || (opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 ||
(opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30))) || (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
(op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))) (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
{ {
/*Opcode is likely to cause block to exit, update cycle count*/ /*Opcode is likely to cause block to exit, update cycle count*/
if (codegen_block_cycles) if (codegen_block_cycles)
{ {
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/ addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d); addbyte(0x6d);
addbyte(cpu_state_offset(_cycles)); addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(codegen_block_cycles); addlong(codegen_block_cycles);
codegen_block_cycles = 0; codegen_block_cycles = 0;
} }
@ -2052,7 +2026,7 @@ generate_call:
{ {
addbyte(0x81); /*ADD $codegen_block_ins,ins*/ addbyte(0x81); /*ADD $codegen_block_ins,ins*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(cpu_recomp_ins)); addbyte((uint8_t)cpu_state_offset(cpu_recomp_ins));
addlong(codegen_block_ins); addlong(codegen_block_ins);
codegen_block_ins = 0; codegen_block_ins = 0;
} }
@ -2094,7 +2068,7 @@ generate_call:
addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/ addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(ssegs)); addbyte((uint8_t)cpu_state_offset(ssegs));
addbyte(op_pc + pc_off); addbyte(op_pc + pc_off);
} }
@ -2113,7 +2087,7 @@ generate_call:
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/ addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(rm_data.rm_mod_reg_data)); addbyte((uint8_t)cpu_state_offset(rm_data.rm_mod_reg_data));
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16)); addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
op_pc += pc_off; op_pc += pc_off;
@ -2129,18 +2103,18 @@ generate_call:
last_ea_seg = op_ea_seg; last_ea_seg = op_ea_seg;
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/ addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(ea_seg)); addbyte((uint8_t)cpu_state_offset(ea_seg));
addlong((uint32_t)op_ea_seg); addlong((uint32_t)op_ea_seg);
} }
addbyte(0xC7); /*MOVL pc,new_pc*/ addbyte(0xC7); /*MOVL pc,new_pc*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(pc)); addbyte((uint8_t)cpu_state_offset(pc));
addlong(op_pc + pc_off); addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/ addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(oldpc)); addbyte((uint8_t)cpu_state_offset(oldpc));
addlong(old_pc); addlong(old_pc);
if (op_32 != last_op32) if (op_32 != last_op32)
@ -2148,7 +2122,7 @@ generate_call:
last_op32 = op_32; last_op32 = op_32;
addbyte(0xC7); /*MOVL $use32,(op32)*/ addbyte(0xC7); /*MOVL $use32,(op32)*/
addbyte(0x45); addbyte(0x45);
addbyte(cpu_state_offset(op32)); addbyte((uint8_t)cpu_state_offset(op32));
addlong(op_32); addlong(op_32);
} }

2
src/codegen_x86.h
View file

@ -17,7 +17,7 @@ enum
OP_RET = 0xc3 OP_RET = 0xc3
}; };
#define NR_HOST_REGS 3 #define NR_HOST_REGS 4
extern int host_reg_mapping[NR_HOST_REGS]; extern int host_reg_mapping[NR_HOST_REGS];
#define NR_HOST_XMM_REGS 7 #define NR_HOST_XMM_REGS 7
extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS]; extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS];

2
src/config.c
View file

@ -1,6 +1,7 @@
#include <stdio.h> #include <stdio.h>
#include <string.h> #include <string.h>
#include <stdlib.h> #include <stdlib.h>
#include "ibm.h"
#include "config.h" #include "config.h"
char config_file_default[256]; char config_file_default[256];
@ -278,7 +279,6 @@ char *config_get_string(char *head, char *name, char *def)
{ {
section_t *section; section_t *section;
entry_t *entry; entry_t *entry;
int value;
section = find_section(head); section = find_section(head);

3
src/cpu.h
View file

@ -125,6 +125,7 @@ uint8_t cyrix_read(uint16_t addr, void *priv);
extern int is8086; extern int is8086;
void cpu_CPUID();
void cpu_RDMSR(); void cpu_RDMSR();
void cpu_WRMSR(); void cpu_WRMSR();
@ -137,5 +138,7 @@ extern int isa_cycles;
#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT) #define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
void cpu_update_waitstates(); void cpu_update_waitstates();
void cpu_set();
void cpu_set_edx();
#endif #endif

1
src/dac.c
View file

@ -1,4 +1,5 @@
#include "ibm.h" #include "ibm.h"
#include "dac.h"
uint8_t dac,dac2; uint8_t dac,dac2;
uint8_t dacctrl; uint8_t dacctrl;

3
src/dac.h Normal file
View file

@ -0,0 +1,3 @@
void writedac(uint16_t addr, uint8_t val);
void writedacctrl(uint16_t addr, uint8_t val);
uint8_t readdacfifo();

2
src/device.c
View file

@ -100,7 +100,7 @@ void device_force_redraw()
} }
} }
char *device_add_status_info(char *s, int max_len) void device_add_status_info(char *s, int max_len)
{ {
int c; int c;

2
src/device.h
View file

@ -39,7 +39,7 @@ void device_close_all();
int device_available(device_t *d); int device_available(device_t *d);
void device_speed_changed(); void device_speed_changed();
void device_force_redraw(); void device_force_redraw();
char *device_add_status_info(char *s, int max_len); void device_add_status_info(char *s, int max_len);
int device_get_config_int(char *name); int device_get_config_int(char *name);
char *device_get_config_string(char *name); char *device_get_config_string(char *name);

2
src/disc.c
View file

@ -152,7 +152,7 @@ void disc_poll()
int disc_get_bitcell_period(int rate) int disc_get_bitcell_period(int rate)
{ {
int bit_rate; int bit_rate = 0;
switch (rate) switch (rate)
{ {

2
src/disc.h
View file

@ -5,7 +5,7 @@ typedef struct
void (*writesector)(int drive, int sector, int track, int side, int density, int sector_size); void (*writesector)(int drive, int sector, int track, int side, int density, int sector_size);
void (*readaddress)(int drive, int track, int side, int density); void (*readaddress)(int drive, int track, int side, int density);
void (*format)(int drive, int track, int side, int density, uint8_t fill); void (*format)(int drive, int track, int side, int density, uint8_t fill);
uint8_t (*hole)(int drive); int (*hole)(int drive);
void (*stop)(); void (*stop)();
void (*poll)(); void (*poll)();
} DRIVE; } DRIVE;

25
src/disc_fdi.c
View file

@ -107,7 +107,6 @@ void fdi_close(int drive)
void fdi_seek(int drive, int track) void fdi_seek(int drive, int track)
{ {
int c;
int density; int density;
if (!fdi[drive].f) if (!fdi[drive].f)
@ -141,7 +140,7 @@ void fdi_seek(int drive, int track)
else else
{ {
memset(fdi[drive].track_data[1][density], 0, 65536); memset(fdi[drive].track_data[1][density], 0, 65536);
fdi[drive].tracklen[1][density] = fdi[drive].tracklen[1][density] = 10000; fdi[drive].tracklen[1][density] = fdi[drive].trackindex[1][density] = 10000;
} }
} }
} }
@ -332,11 +331,6 @@ void fdi_poll()
if (readidpoll) if (readidpoll)
{ {
fdi_sectordat[5 - pollbytesleft] = decodefm(fdi_buffer); fdi_sectordat[5 - pollbytesleft] = decodefm(fdi_buffer);
if (fdi_inreadaddr && !fdc_sectorid)// && pollbytesleft > 1)
{
// rpclog("inreadaddr - %02X\n", fdi_sectordat[5 - pollbytesleft]);
fdc_data(fdi_sectordat[5 - pollbytesleft]);
}
if (!pollbytesleft) if (!pollbytesleft)
{ {
// pclog("Header over %i,%i %i,%i\n", fdi_sectordat[0], fdi_sectordat[2], fdi_track, fdi_sector); // pclog("Header over %i,%i %i,%i\n", fdi_sectordat[0], fdi_sectordat[2], fdi_track, fdi_sector);
@ -354,15 +348,9 @@ void fdi_poll()
// exit(-1); // exit(-1);
inreadop = 0; inreadop = 0;
if (fdi_inreadaddr) if (fdi_inreadaddr)
{ fdc_sectorid(fdi_sectordat[0], fdi_sectordat[1], fdi_sectordat[2], fdi_sectordat[3], fdi_sectordat[4], fdi_sectordat[5]);
// rpclog("inreadaddr - %02X\n", fdi_sector); else
// fdc_data(fdi_sector); fdc_headercrcerror();
if (fdc_sectorid)
fdc_sectorid(fdi_sectordat[0], fdi_sectordat[1], fdi_sectordat[2], fdi_sectordat[3], fdi_sectordat[4], fdi_sectordat[5]);
else
fdc_finishread();
}
else fdc_headercrcerror();
return; return;
} }
// pclog("Sector %i,%i %i,%i\n", fdi_sectordat[0], fdi_sectordat[2], fdi_track, fdi_sector); // pclog("Sector %i,%i %i,%i\n", fdi_sectordat[0], fdi_sectordat[2], fdi_track, fdi_sector);
@ -375,10 +363,7 @@ void fdi_poll()
} }
if (fdi_inreadaddr) if (fdi_inreadaddr)
{ {
if (fdc_sectorid) fdc_sectorid(fdi_sectordat[0], fdi_sectordat[1], fdi_sectordat[2], fdi_sectordat[3], fdi_sectordat[4], fdi_sectordat[5]);
fdc_sectorid(fdi_sectordat[0], fdi_sectordat[1], fdi_sectordat[2], fdi_sectordat[3], fdi_sectordat[4], fdi_sectordat[5]);
else
fdc_finishread();
fdi_inreadaddr = 0; fdi_inreadaddr = 0;
} }
} }

4
src/disc_img.c
View file

@ -318,7 +318,7 @@ void img_seek(int drive, int track)
int side; int side;
int current_xdft = img[drive].xdf_type - 1; int current_xdft = img[drive].xdf_type - 1;
uint8_t sectors_fat, effective_sectors, sector_gap; /* Needed for XDF */ uint8_t sectors_fat, effective_sectors; /* Needed for XDF */
if (!img[drive].f) if (!img[drive].f)
return; return;
@ -351,7 +351,7 @@ void img_seek(int drive, int track)
{ {
sectors_fat = xdf_track0[current_xdft][0]; sectors_fat = xdf_track0[current_xdft][0];
effective_sectors = xdf_track0[current_xdft][1]; effective_sectors = xdf_track0[current_xdft][1];
sector_gap = xdf_track0[current_xdft][2]; // sector_gap = xdf_track0[current_xdft][2];
if (!track) if (!track)
{ {

1
src/disc_sector.c
View file

@ -1,6 +1,7 @@
#include "ibm.h" #include "ibm.h"
#include "disc.h" #include "disc.h"
#include "disc_sector.h" #include "disc_sector.h"
#include "fdc.h"
#include "fdd.h" #include "fdd.h"
/*Handling for 'sector based' image formats (like .IMG) as opposed to 'stream based' formats (eg .FDI)*/ /*Handling for 'sector based' image formats (like .IMG) as opposed to 'stream based' formats (eg .FDI)*/

3
src/dma.c
View file

@ -5,6 +5,7 @@
#include "io.h" #include "io.h"
#include "mem.h" #include "mem.h"
#include "video.h" #include "video.h"
#include "x86.h"
static uint8_t dmaregs[16]; static uint8_t dmaregs[16];
static uint8_t dma16regs[16]; static uint8_t dma16regs[16];
@ -121,7 +122,7 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
static uint8_t dma_ps2_read(uint16_t addr, void *priv) static uint8_t dma_ps2_read(uint16_t addr, void *priv)
{ {
uint8_t temp; uint8_t temp = 0xff;
switch (addr) switch (addr)
{ {

6
src/dosbox/dbopl.cpp
View file

@ -883,6 +883,9 @@ Channel* Channel::BlockTemplate( Chip* chip, Bit32u samples, Bit32s* output ) {
return (this + 2); return (this + 2);
} }
break; break;
case sm2Percussion:
case sm3Percussion:
break;
} }
//Init the operators with the the current vibrato and tremolo values //Init the operators with the the current vibrato and tremolo values
Op( 0 )->Prepare( chip ); Op( 0 )->Prepare( chip );
@ -954,6 +957,9 @@ Channel* Channel::BlockTemplate( Chip* chip, Bit32u samples, Bit32s* output ) {
output[ i * 2 + 0 ] += sample & maskLeft; output[ i * 2 + 0 ] += sample & maskLeft;
output[ i * 2 + 1 ] += sample & maskRight; output[ i * 2 + 1 ] += sample & maskRight;
break; break;
case sm2Percussion:
case sm3Percussion:
break;
} }
} }
switch( mode ) { switch( mode ) {

7
src/dosbox/vid_cga_comp.c
View file

@ -58,18 +58,11 @@ int video_sharpness;
int tandy_mode_control = 0; int tandy_mode_control = 0;
static bool new_cga = 0; static bool new_cga = 0;
static bool is_bw = 0;
static bool is_bpp1 = 0;
static uint8_t comp_pal[256][3];
static Bit8u byte_clamp_other(int v) { return v < 0 ? 0 : (v > 255 ? 255 : v); }
FILE *df; FILE *df;
void update_cga16_color(uint8_t cgamode) { void update_cga16_color(uint8_t cgamode) {
int x; int x;
Bit32u x2;
if (!new_cga) { if (!new_cga) {
min_v = chroma_multiplexer[0] + intensity[0]; min_v = chroma_multiplexer[0] + intensity[0];

4
src/fdc.c
View file

@ -3,6 +3,7 @@
#include "ibm.h" #include "ibm.h"
#include "disc.h" #include "disc.h"
#include "disc_sector.h"
#include "dma.h" #include "dma.h"
#include "fdd.h" #include "fdd.h"
#include "io.h" #include "io.h"
@ -94,7 +95,6 @@ void fdc_reset()
void fdc_reset_fifo_buf() void fdc_reset_fifo_buf()
{ {
int i = 0;
memset(fdc.fifobuf, 0, 16); memset(fdc.fifobuf, 0, 16);
fdc.fifobufpos = 0; fdc.fifobufpos = 0;
} }
@ -304,6 +304,8 @@ static int fdc_get_densel(int drive)
case 2: case 2:
return fdc.densel_polarity ? 0 : 1; return fdc.densel_polarity ? 0 : 1;
} }
return 0;
} }
static void fdc_rate(int drive) static void fdc_rate(int drive)

2
src/fdc37c665.c
View file

@ -36,7 +36,7 @@ void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
} }
else else
{ {
uint16_t com3_addr, com4_addr; uint16_t com3_addr = 0, com4_addr = 0;
fdc37c665_regs[fdc37c665_curreg] = val; fdc37c665_regs[fdc37c665_curreg] = val;
// pclog("Write superIO %02x %02x %04x(%08x):%08x\n", fdc37c665_curreg, val, CS, cs, pc); // pclog("Write superIO %02x %02x %04x(%08x):%08x\n", fdc37c665_curreg, val, CS, cs, pc);

4
src/fdd.c
View file

@ -78,12 +78,8 @@ int fdd_swap = 0;
void fdd_seek(int drive, int track_diff) void fdd_seek(int drive, int track_diff)
{ {
int old_track;
drive ^= fdd_swap; drive ^= fdd_swap;
old_track = fdd[drive].track;
fdd[drive].track += track_diff; fdd[drive].track += track_diff;
if (fdd[drive].track < 0) if (fdd[drive].track < 0)

6
src/fdi2raw.c
View file

@ -1813,16 +1813,16 @@ static void fdi2_celltiming (FDI *fdi, uint32_t totalavg, int bitoffset, uae_u16
static int decode_lowlevel_track (FDI *fdi, int track, struct fdi_cache *cache) static int decode_lowlevel_track (FDI *fdi, int track, struct fdi_cache *cache)
{ {
uae_u8 *p1, *d; uae_u8 *p1;
uae_u32 *p2; uae_u32 *p2;
uae_u32 *avgp, *minp = 0, *maxp = 0; uae_u32 *avgp, *minp = 0, *maxp = 0;
uae_u8 *idxp = 0; uae_u8 *idxp = 0;
uae_u32 maxidx, totalavg, weakbits; uae_u32 maxidx, totalavg, weakbits;
int i, j, len, pulses, indexoffset; int i, j, len, pulses, indexoffset;
int avg_free, min_free = 0, max_free = 0, idx_free; int avg_free, min_free = 0, max_free = 0, idx_free;
int idx_off1, idx_off2, idx_off3; int idx_off1 = 0, idx_off2 = 0, idx_off3 = 0;
d = fdi->track_dst; // d = fdi->track_dst;
p1 = fdi->track_src; p1 = fdi->track_src;
pulses = get_u32 (p1); pulses = get_u32 (p1);
if (!pulses) if (!pulses)

1
src/hdd_esdi.c
View file

@ -5,6 +5,7 @@
#include <stdio.h> #include <stdio.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <stdlib.h>
#include <sys/types.h> #include <sys/types.h>
#include "ibm.h" #include "ibm.h"

3
src/i430fx.c
View file

@ -1,8 +1,11 @@
#include <string.h> #include <string.h>
#include "ibm.h" #include "ibm.h"
#include "io.h"
#include "keyboard_at.h"
#include "mem.h" #include "mem.h"
#include "pci.h" #include "pci.h"
#include "x86.h"
#include "i430fx.h" #include "i430fx.h"

3
src/i430lx.c
View file

@ -1,8 +1,11 @@
#include <string.h> #include <string.h>
#include "ibm.h" #include "ibm.h"
#include "io.h"
#include "keyboard_at.h"
#include "mem.h" #include "mem.h"
#include "pci.h" #include "pci.h"
#include "x86.h"
#include "i430lx.h" #include "i430lx.h"

20
src/ibm.h
View file

@ -539,3 +539,23 @@ void resetpc_cad();
extern int start_in_fullscreen; extern int start_in_fullscreen;
extern int window_w, window_h, window_x, window_y, window_remember; extern int window_w, window_h, window_x, window_y, window_remember;
void get_executable_name(char *s, int size);
void startblit();
void endblit();
void set_window_title(char *s);
void updatewindowsize(int x, int y);
void initpc(int argc, char *argv[]);
void runpc();
void closepc();
void resetpc();
void resetpchard();
void speedchanged();
void saveconfig();
#define UNUSED(x) (void)x

13
src/ide.c
View file

@ -1111,7 +1111,7 @@ void writeide(int ide_board, uint16_t addr, uint8_t val)
uint8_t readide(int ide_board, uint16_t addr) uint8_t readide(int ide_board, uint16_t addr)
{ {
IDE *ide = &ide_drives[cur_ide[ide_board]]; IDE *ide = &ide_drives[cur_ide[ide_board]];
uint8_t temp; uint8_t temp = 0xff;
uint16_t tempw; uint16_t tempw;
addr|=0x80; addr|=0x80;
@ -1784,8 +1784,6 @@ static uint32_t atapi_event_status(IDE *ide, uint8_t *buffer)
return 8; return 8;
} }
static int changed_status = 0;
void atapi_cmd_error(IDE *ide, uint8_t sensekey, uint8_t asc) void atapi_cmd_error(IDE *ide, uint8_t sensekey, uint8_t asc)
{ {
ide->error = (sensekey << 4); ide->error = (sensekey << 4);
@ -1994,9 +1992,9 @@ static void atapicommand(int ide_board)
break; break;
case GPCMD_MECHANISM_STATUS: /*0xbd*/ case GPCMD_MECHANISM_STATUS: /*0xbd*/
len=(idebufferb[7]<<16)|(idebufferb[8]<<8)|idebufferb[9]; alloc_length = (idebufferb[7]<<16)|(idebufferb[8]<<8)|idebufferb[9];
if (len == 0) if (alloc_length == 0)
fatal("Zero allocation length to MECHANISM STATUS not impl.\n"); fatal("Zero allocation length to MECHANISM STATUS not impl.\n");
atapi_command_send_init(ide, idebufferb[0], 8, alloc_length); atapi_command_send_init(ide, idebufferb[0], 8, alloc_length);
@ -2293,7 +2291,7 @@ static void atapicommand(int ide_board)
case GPCMD_GET_EVENT_STATUS_NOTIFICATION: /*0x4a*/ case GPCMD_GET_EVENT_STATUS_NOTIFICATION: /*0x4a*/
temp_command = idebufferb[0]; temp_command = idebufferb[0];
alloc_length = len; alloc_length = (idebufferb[7]<<16)|(idebufferb[8]<<8)|idebufferb[9];
{ {
struct __attribute__((__packed__)) struct __attribute__((__packed__))
@ -2613,7 +2611,7 @@ atapi_out:
break; break;
case GPCMD_READ_CDROM_CAPACITY: case GPCMD_READ_CDROM_CAPACITY:
atapi_command_send_init(ide, temp_command, 8, 8); atapi_command_send_init(ide, 0, 8, 8);
size = atapi->size(); size = atapi->size();
idebufferb[0] = (size >> 24) & 0xff; idebufferb[0] = (size >> 24) & 0xff;
idebufferb[1] = (size >> 16) & 0xff; idebufferb[1] = (size >> 16) & 0xff;
@ -2629,7 +2627,6 @@ atapi_out:
case GPCMD_SEND_DVD_STRUCTURE: case GPCMD_SEND_DVD_STRUCTURE:
default: default:
bad_atapi_command:
ide->atastat = READY_STAT | ERR_STAT; /*CHECK CONDITION*/ ide->atastat = READY_STAT | ERR_STAT; /*CHECK CONDITION*/
ide->error = (SENSE_ILLEGAL_REQUEST << 4) | ABRT_ERR; ide->error = (SENSE_ILLEGAL_REQUEST << 4) | ABRT_ERR;
if (atapi_sense.sensekey == SENSE_UNIT_ATTENTION) if (atapi_sense.sensekey == SENSE_UNIT_ATTENTION)

3
src/ide.h
View file

@ -53,6 +53,9 @@ extern char ide_fn[4][512];
extern int cdrom_channel; extern int cdrom_channel;
uint32_t atapi_get_cd_channel(int channel);
uint32_t atapi_get_cd_volume(int channel);
#define CDROM_ISO 200 #define CDROM_ISO 200
#endif //__IDE__ #endif //__IDE__

19
src/io.c
View file

@ -20,11 +20,20 @@ void io_init()
pclog("io_init\n"); pclog("io_init\n");
for (c = 0; c < 0x10000; c++) for (c = 0; c < 0x10000; c++)
{ {
port_inb[c][0] = port_inw[c][0] = port_inl[c][0] = NULL; port_inb[c][0] = NULL;
port_outb[c][0] = port_outw[c][0] = port_outl[c][0] = NULL; port_inw[c][0] = NULL;
port_inb[c][1] = port_inw[c][1] = port_inl[c][1] = NULL; port_inl[c][0] = NULL;
port_outb[c][1] = port_outw[c][1] = port_outl[c][1] = NULL; port_outb[c][0] = NULL;
port_priv[c][0] = port_priv[c][1] = NULL; port_outw[c][0] = NULL;
port_outl[c][0] = NULL;
port_inb[c][1] = NULL;
port_inw[c][1] = NULL;
port_inl[c][1] = NULL;
port_outb[c][1] = NULL;
port_outw[c][1] = NULL;
port_outl[c][1] = NULL;
port_priv[c][0] = NULL;
port_priv[c][1] = NULL;
} }
} }

2
src/joystick_ch_flightstick_pro.c
View file

@ -8,6 +8,7 @@
static void *ch_flightstick_pro_init() static void *ch_flightstick_pro_init()
{ {
return NULL;
} }
static void ch_flightstick_pro_close(void *p) static void ch_flightstick_pro_close(void *p)
@ -64,6 +65,7 @@ static int ch_flightstick_pro_read_axis(void *p, int axis)
case 3: case 3:
return joystick_state[0].axis[2]; return joystick_state[0].axis[2];
} }
return 0;
} }
static void ch_flightstick_pro_a0_over(void *p) static void ch_flightstick_pro_a0_over(void *p)

5
src/joystick_standard.c
View file

@ -8,6 +8,7 @@
static void *joystick_standard_init() static void *joystick_standard_init()
{ {
return NULL;
} }
static void joystick_standard_close(void *p) static void joystick_standard_close(void *p)
@ -80,6 +81,7 @@ static int joystick_standard_read_axis(void *p, int axis)
return AXIS_NOT_PRESENT; return AXIS_NOT_PRESENT;
return joystick_state[1].axis[1]; return joystick_state[1].axis[1];
} }
return 0;
} }
static int joystick_standard_read_axis_4button(void *p, int axis) static int joystick_standard_read_axis_4button(void *p, int axis)
@ -98,6 +100,7 @@ static int joystick_standard_read_axis_4button(void *p, int axis)
case 3: case 3:
return 0; return 0;
} }
return 0;
} }
static int joystick_standard_read_axis_6button(void *p, int axis) static int joystick_standard_read_axis_6button(void *p, int axis)
{ {
@ -115,6 +118,7 @@ static int joystick_standard_read_axis_6button(void *p, int axis)
case 3: case 3:
return joystick_state[0].button[5] ? -32767 : 32768; return joystick_state[0].button[5] ? -32767 : 32768;
} }
return 0;
} }
static int joystick_standard_read_axis_8button(void *p, int axis) static int joystick_standard_read_axis_8button(void *p, int axis)
{ {
@ -140,6 +144,7 @@ static int joystick_standard_read_axis_8button(void *p, int axis)
return 32768; return 32768;
return 0; return 0;
} }
return 0;
} }
static void joystick_standard_a0_over(void *p) static void joystick_standard_a0_over(void *p)

2
src/joystick_tm_fcs.c
View file

@ -8,6 +8,7 @@
static void *tm_fcs_init() static void *tm_fcs_init()
{ {
return NULL;
} }
static void tm_fcs_close(void *p) static void tm_fcs_close(void *p)
@ -63,6 +64,7 @@ static int tm_fcs_read_axis(void *p, int axis)
return 16384; return 16384;
return 0; return 0;
} }
return 0;
} }
static void tm_fcs_a0_over(void *p) static void tm_fcs_a0_over(void *p)

1
src/keyboard.h
View file

@ -1,5 +1,6 @@
extern void (*keyboard_send)(uint8_t val); extern void (*keyboard_send)(uint8_t val);
extern void (*keyboard_poll)(); extern void (*keyboard_poll)();
void keyboard_process();
extern int keyboard_scan; extern int keyboard_scan;
extern int pcem_key[272]; extern int pcem_key[272];

2
src/keyboard_amstrad.c
View file

@ -110,7 +110,7 @@ void keyboard_amstrad_write(uint16_t port, uint8_t val, void *priv)
uint8_t keyboard_amstrad_read(uint16_t port, void *priv) uint8_t keyboard_amstrad_read(uint16_t port, void *priv)
{ {
uint8_t temp; uint8_t temp = 0xff;
// pclog("keyboard_amstrad : read %04X ", port); // pclog("keyboard_amstrad : read %04X ", port);
switch (port) switch (port)
{ {

1
src/keyboard_at.c
View file

@ -6,6 +6,7 @@
#include "sound.h" #include "sound.h"
#include "sound_speaker.h" #include "sound_speaker.h"
#include "timer.h" #include "timer.h"
#include "x86.h"
#include "keyboard.h" #include "keyboard.h"
#include "keyboard_at.h" #include "keyboard_at.h"

1
src/keyboard_at.h
View file

@ -3,6 +3,7 @@ void keyboard_at_init_ps2();
void keyboard_at_reset(); void keyboard_at_reset();
void keyboard_at_poll(); void keyboard_at_poll();
void keyboard_at_set_mouse(void (*mouse_write)(uint8_t val, void *p), void *p); void keyboard_at_set_mouse(void (*mouse_write)(uint8_t val, void *p), void *p);
void keyboard_at_adddata_mouse(uint8_t val);
extern int mouse_queue_start, mouse_queue_end; extern int mouse_queue_start, mouse_queue_end;
extern int mouse_scan; extern int mouse_scan;

4
src/keyboard_olim24.c
View file

@ -1,8 +1,10 @@
#include <stdlib.h>
#include "ibm.h" #include "ibm.h"
#include "io.h" #include "io.h"
#include "mem.h" #include "mem.h"
#include "mouse.h" #include "mouse.h"
#include "pic.h" #include "pic.h"
#include "pit.h"
#include "sound.h" #include "sound.h"
#include "sound_speaker.h" #include "sound_speaker.h"
#include "timer.h" #include "timer.h"
@ -159,7 +161,7 @@ void keyboard_olim24_write(uint16_t port, uint8_t val, void *priv)
uint8_t keyboard_olim24_read(uint16_t port, void *priv) uint8_t keyboard_olim24_read(uint16_t port, void *priv)
{ {
uint8_t temp; uint8_t temp = 0xff;
// pclog("keyboard_olim24 : read %04X ", port); // pclog("keyboard_olim24 : read %04X ", port);
switch (port) switch (port)
{ {

3
src/keyboard_pcjr.c
View file

@ -4,6 +4,7 @@
#include "mem.h" #include "mem.h"
#include "nmi.h" #include "nmi.h"
#include "pic.h" #include "pic.h"
#include "pit.h"
#include "sound.h" #include "sound.h"
#include "sound_sn76489.h" #include "sound_sn76489.h"
#include "sound_speaker.h" #include "sound_speaker.h"
@ -155,7 +156,7 @@ void keyboard_pcjr_write(uint16_t port, uint8_t val, void *priv)
uint8_t keyboard_pcjr_read(uint16_t port, void *priv) uint8_t keyboard_pcjr_read(uint16_t port, void *priv)
{ {
uint8_t temp; uint8_t temp = 0xff;
// pclog("keyboard_pcjr : read %04X ", port); // pclog("keyboard_pcjr : read %04X ", port);
switch (port) switch (port)
{ {

5
src/keyboard_xt.c
View file

@ -1,9 +1,12 @@
#include "ibm.h" #include "ibm.h"
#include "device.h"
#include "io.h" #include "io.h"
#include "mem.h" #include "mem.h"
#include "pic.h" #include "pic.h"
#include "pit.h"
#include "sound.h" #include "sound.h"
#include "sound_speaker.h" #include "sound_speaker.h"
#include "tandy_eeprom.h"
#include "timer.h" #include "timer.h"
#include "keyboard.h" #include "keyboard.h"
@ -99,7 +102,7 @@ void keyboard_xt_write(uint16_t port, uint8_t val, void *priv)
uint8_t keyboard_xt_read(uint16_t port, void *priv) uint8_t keyboard_xt_read(uint16_t port, void *priv)
{ {
uint8_t temp; uint8_t temp = 0xff;
// pclog("keyboard_xt : read %04X ", port); // pclog("keyboard_xt : read %04X ", port);
switch (port) switch (port)
{ {

9
src/lpt.c
View file

@ -1,4 +1,5 @@
#include "ibm.h" #include "ibm.h"
#include "dac.h"
#include "io.h" #include "io.h"
#include "lpt.h" #include "lpt.h"
@ -11,11 +12,11 @@ void lpt1_write(uint16_t port, uint8_t val, void *priv)
switch (port & 3) switch (port & 3)
{ {
case 0: case 0:
writedac(val); writedac(0,val);
lpt1_dat = val; lpt1_dat = val;
break; break;
case 2: case 2:
writedacctrl(val); writedacctrl(0,val);
lpt1_ctrl = val; lpt1_ctrl = val;
break; break;
} }
@ -39,11 +40,11 @@ void lpt2_write(uint16_t port, uint8_t val, void *priv)
switch (port & 3) switch (port & 3)
{ {
case 0: case 0:
writedac(val); writedac(0,val);
lpt2_dat = val; lpt2_dat = val;
break; break;
case 2: case 2:
writedacctrl(val); writedacctrl(0,val);
lpt2_ctrl = val; lpt2_ctrl = val;
break; break;
} }

6
src/mca.c
View file

@ -15,7 +15,11 @@ void mca_init(int nr_cards)
int c; int c;
for (c = 0; c < 8; c++) for (c = 0; c < 8; c++)
mca_card_read[c] = mca_card_write[c] = mca_priv[c] = NULL; {
mca_card_read[c] = NULL;
mca_card_write[c] = NULL;
mca_priv[c] = NULL;
}
mca_index = 0; mca_index = 0;
mca_nr_cards = nr_cards; mca_nr_cards = nr_cards;

2
src/mem.c
View file

@ -1534,6 +1534,7 @@ static inline int mem_mapping_read_allowed(uint32_t flags, int state)
default: default:
fatal("mem_mapping_read_allowed : bad state %x\n", state); fatal("mem_mapping_read_allowed : bad state %x\n", state);
} }
return 0;
} }
static inline int mem_mapping_write_allowed(uint32_t flags, int state) static inline int mem_mapping_write_allowed(uint32_t flags, int state)
@ -1551,6 +1552,7 @@ static inline int mem_mapping_write_allowed(uint32_t flags, int state)
default: default:
fatal("mem_mapping_write_allowed : bad state %x\n", state); fatal("mem_mapping_write_allowed : bad state %x\n", state);
} }
return 0;
} }
static void mem_mapping_recalc(uint64_t base, uint64_t size) static void mem_mapping_recalc(uint64_t base, uint64_t size)

17
src/mem.h
View file

@ -166,4 +166,21 @@ extern mem_mapping_t ram_low_mapping;
void mem_remap_top_256k(); void mem_remap_top_256k();
void mem_remap_top_384k(); void mem_remap_top_384k();
void mem_flush_write_page(uint32_t addr, uint32_t virt);
void mem_add_bios();
void mem_init();
void mem_resize();
void flushmmucache();
void flushmmucache_nopc();
void flushmmucache_cr3();
void resetreadlookup();
void mmu_invalidate(uint32_t addr);
int loadbios();
#endif #endif

3
src/mfm_at.c
View file

@ -5,6 +5,7 @@
#include <stdio.h> #include <stdio.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <stdlib.h>
#include <sys/types.h> #include <sys/types.h>
@ -380,7 +381,7 @@ void mfm_writew(uint16_t port, uint16_t val, void *p)
uint8_t mfm_read(uint16_t port, void *p) uint8_t mfm_read(uint16_t port, void *p)
{ {
mfm_t *mfm = (mfm_t *)p; mfm_t *mfm = (mfm_t *)p;
uint8_t temp; uint8_t temp = 0xff;
switch (port) switch (port)
{ {

1
src/mfm_xebec.c
View file

@ -5,6 +5,7 @@
#include <stdio.h> #include <stdio.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <stdlib.h>
#include <sys/types.h> #include <sys/types.h>
#include "ibm.h" #include "ibm.h"

94
src/model.c
View file

@ -27,6 +27,8 @@
#include "keyboard_pcjr.h" #include "keyboard_pcjr.h"
#include "keyboard_xt.h" #include "keyboard_xt.h"
#include "lpt.h" #include "lpt.h"
#include "mem.h"
#include "mouse_ps2.h"
#include "neat.h" #include "neat.h"
#include "nmi.h" #include "nmi.h"
#include "nvr.h" #include "nvr.h"
@ -87,52 +89,52 @@ int AMSTRAD, AT, PCI, TANDY;
MODEL models[] = MODEL models[] =
{ {
{"IBM PC", ROM_IBMPC, "ibmpc", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"IBM PC", ROM_IBMPC, "ibmpc", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"IBM XT", ROM_IBMXT, "ibmxt", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"IBM XT", ROM_IBMXT, "ibmxt", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"IBM PCjr", ROM_IBMPCJR, "ibmpcjr", { "", cpus_pcjr, "", NULL, "", NULL}, 1, 0, 128, 640, 64, pcjr_init, &pcjr_device}, {"IBM PCjr", ROM_IBMPCJR, "ibmpcjr", { {"", cpus_pcjr}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 64, pcjr_init, &pcjr_device},
{"Generic XT clone", ROM_GENXT, "genxt", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"Generic XT clone", ROM_GENXT, "genxt", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"AMI XT clone", ROM_AMIXT, "amixt", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"AMI XT clone", ROM_AMIXT, "amixt", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"DTK XT clone", ROM_DTKXT, "dtk", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"DTK XT clone", ROM_DTKXT, "dtk", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"VTech Laser Turbo XT", ROM_LTXT, "ltxt", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"VTech Laser Turbo XT", ROM_LTXT, "ltxt", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"VTech Laser XT3", ROM_LXT3, "lxt3", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"VTech Laser XT3", ROM_LXT3, "lxt3", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"Phoenix XT clone", ROM_PXXT, "pxxt", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"Phoenix XT clone", ROM_PXXT, "pxxt", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"Juko XT clone", ROM_JUKOPC, "jukopc", { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, {"Juko XT clone", ROM_JUKOPC, "jukopc", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, xt_init, NULL},
{"Tandy 1000", ROM_TANDY, "tandy", { "", cpus_8088, "", NULL, "", NULL}, 1, 0, 128, 640, 128, tandy1k_init, &tandy1000_device}, {"Tandy 1000", ROM_TANDY, "tandy", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, tandy1k_init, &tandy1000_device},
{"Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", { "", cpus_8088, "", NULL, "", NULL}, 1, 0, 256, 640, 128, tandy1k_init, &tandy1000hx_device}, {"Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", { {"", cpus_8088}, {"", NULL}, {"", NULL}}, 1, 0, 256, 640, 128, tandy1k_init, &tandy1000hx_device},
{"Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", { "", cpus_8086, "", NULL, "", NULL}, 1, 0, 512, 768, 128, tandy1ksl2_init, NULL}, {"Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 1, 0, 512, 768, 128, tandy1ksl2_init, NULL},
{"Amstrad PC1512", ROM_PC1512, "pc1512", { "", cpus_pc1512, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 512, 640, 128, ams_init, NULL}, {"Amstrad PC1512", ROM_PC1512, "pc1512", { {"", cpus_pc1512}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, ams_init, NULL},
{"Sinclair PC200", ROM_PC200, "pc200", { "", cpus_8086, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 512, 640, 128, ams_init, NULL}, {"Sinclair PC200", ROM_PC200, "pc200", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, ams_init, NULL},
{"Euro PC", ROM_EUROPC, "europc", { "", cpus_8086, "", NULL, "", NULL}, 0, 0, 512, 640, 128, europc_init, NULL}, {"Euro PC", ROM_EUROPC, "europc", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 0, 0, 512, 640, 128, europc_init, NULL},
{"Olivetti M24", ROM_OLIM24, "olivetti_m24", { "", cpus_8086, "", NULL, "", NULL}, 1, MODEL_OLIM24, 128, 640, 128, olim24_init, NULL}, {"Olivetti M24", ROM_OLIM24, "olivetti_m24", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 1, MODEL_OLIM24, 128, 640, 128, olim24_init, NULL},
{"Amstrad PC1640", ROM_PC1640, "pc1640", { "", cpus_8086, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 640, 640, 0, ams_init, NULL}, {"Amstrad PC1640", ROM_PC1640, "pc1640", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, ams_init, NULL},
{"Amstrad PC2086", ROM_PC2086, "pc2086", { "", cpus_8086, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 640, 640, 0, ams_init, NULL}, {"Amstrad PC2086", ROM_PC2086, "pc2086", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, ams_init, NULL},
{"Amstrad PC3086", ROM_PC3086, "pc3086", { "", cpus_8086, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 640, 640, 0, ams_init, NULL}, {"Amstrad PC3086", ROM_PC3086, "pc3086", { {"", cpus_8086}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, ams_init, NULL},
{"IBM AT", ROM_IBMAT, "ibmat", { "", cpus_ibmat, "", NULL, "", NULL}, 0, MODEL_AT, 1, 16, 1, at_init, NULL}, {"IBM AT", ROM_IBMAT, "ibmat", { {"", cpus_ibmat}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 16, 1, at_init, NULL},
{"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", { "", cpus_286, "", NULL, "", NULL}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_ide_init, NULL}, {"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", { {"", cpus_286}, {"", NULL}, {"", NULL}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_ide_init, NULL},
{"AMI 286 clone", ROM_AMI286, "ami286", { "", cpus_286, "", NULL, "", NULL}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_neat_init, NULL}, {"AMI 286 clone", ROM_AMI286, "ami286", { {"", cpus_286}, {"", NULL}, {"", NULL}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_neat_init, NULL},
{"Award 286 clone", ROM_AWARD286, "award286", { "", cpus_286, "", NULL, "", NULL}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_scat_init, NULL}, {"Award 286 clone", ROM_AWARD286, "award286", { {"", cpus_286}, {"", NULL}, {"", NULL}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_scat_init, NULL},
{"DELL System 200", ROM_DELL200, "dells200", { "", cpus_286, "", NULL, "", NULL}, 0, MODEL_AT, 1, 16, 1, at_init, NULL}, {"DELL System 200", ROM_DELL200, "dells200", { {"", cpus_286}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 16, 1, at_init, NULL},
{"IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", { "", cpus_ps1_m2011, "", NULL, "", NULL}, 1, MODEL_AT|MODEL_PS2, 1, 16, 1, ps1_m2011_init, NULL}, {"IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", { {"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}}, 1, MODEL_AT|MODEL_PS2, 1, 16, 1, ps1_m2011_init, NULL},
{"IBM PS/2 Model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", { "", cpus_ps2_m30_286, "", NULL, "", NULL}, 1, MODEL_AT|MODEL_PS2, 1, 16, 1, ps2_m30_286_init, NULL}, {"IBM PS/2 Model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", { {"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}}, 1, MODEL_AT|MODEL_PS2, 1, 16, 1, ps2_m30_286_init, NULL},
{"IBM PS/2 Model 50", ROM_IBMPS2_M50, "ibmps2_m50", { "", cpus_ps2_m30_286, "", NULL, "", NULL}, 1, MODEL_AT|MODEL_PS2|MODEL_MCA, 1, 16, 1, ps2_model_50_init, NULL}, {"IBM PS/2 Model 50", ROM_IBMPS2_M50, "ibmps2_m50", { {"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}}, 1, MODEL_AT|MODEL_PS2|MODEL_MCA, 1, 16, 1, ps2_model_50_init, NULL},
{"IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 1, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 16, 1, ps1_m2121_init, NULL}, {"IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", { {"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}}, 1, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 16, 1, ps1_m2121_init, NULL},
{"Compaq Deskpro 386", ROM_DESKPRO_386, "deskpro386", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC}, 0, MODEL_AT, 1, 15, 1, deskpro386_init, NULL}, {"Compaq Deskpro 386", ROM_DESKPRO_386, "deskpro386", { {"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}}, 0, MODEL_AT, 1, 15, 1, deskpro386_init, NULL},
{"IBM PS/2 Model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 1, MODEL_AT|MODEL_PS2|MODEL_MCA, 1, 8, 1, ps2_model_55sx_init, NULL}, {"IBM PS/2 Model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", { {"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}}, 1, MODEL_AT|MODEL_PS2|MODEL_MCA, 1, 8, 1, ps2_model_55sx_init, NULL},
{"Acer 386SX25/N", ROM_ACER386, "acer386", { "Intel", cpus_acer, "", NULL, "", NULL}, 1, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 16, 1, at_acer386sx_init, NULL}, {"Acer 386SX25/N", ROM_ACER386, "acer386", { {"Intel", cpus_acer}, {"", NULL}, {"", NULL}}, 1, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 16, 1, at_acer386sx_init, NULL},
{"DTK 386SX clone", ROM_DTK386, "dtk386", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_neat_init, NULL}, {"DTK 386SX clone", ROM_DTK386, "dtk386", { {"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 16, 1, at_neat_init, NULL},
/* {"Phoenix 386 clone", ROM_PX386, { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 0, MODEL_AT, 1, 16, 1, at_init, NULL},*/ /* {"Phoenix 386 clone", ROM_PX386, { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 0, MODEL_AT, 1, 16, 1, at_init, NULL},*/
{"Amstrad MegaPC", ROM_MEGAPC, "megapc", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 1, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 16, 1, at_wd76c10_init, NULL}, {"Amstrad MegaPC", ROM_MEGAPC, "megapc", { {"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}}, 1, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 16, 1, at_wd76c10_init, NULL},
{"AMI 386SX clone", ROM_AMI386SX, "ami386", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_headland_init, NULL}, {"AMI 386SX clone", ROM_AMI386SX, "ami386", { {"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_headland_init, NULL},
{"MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_opti495_init, NULL}, {"MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", { {"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_opti495_init, NULL},
{"AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_opti495_init, NULL}, {"AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", { {"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_opti495_init, NULL},
{"AMI 486 clone", ROM_AMI486, "ami486", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_ali1429_init, NULL}, {"AMI 486 clone", ROM_AMI486, "ami486", { {"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_ali1429_init, NULL},
{"AMI WinBIOS 486", ROM_WIN486, "win486", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_ali1429_init, NULL}, {"AMI WinBIOS 486", ROM_WIN486, "win486", { {"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_ali1429_init, NULL},
/* {"AMI WinBIOS 486 PCI", ROM_PCI486, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, 1, 1, 256, 1, at_um8881f_init},*/ /* {"AMI WinBIOS 486 PCI", ROM_PCI486, { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, 1, 1, 256, 1, at_um8881f_init},*/
{"Award SiS 496/497", ROM_SIS496, "sis496", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_sis496_init, NULL}, {"Award SiS 496/497", ROM_SIS496, "sis496", { {"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}}, 0, MODEL_AT|MODEL_HAS_IDE, 1, 256, 1, at_sis496_init, NULL},
{"Intel Premiere/PCI", ROM_REVENGE, "revenge", { "Intel", cpus_Pentium5V, "", NULL, "", NULL}, 0, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 128, 1, at_batman_init, NULL}, {"Intel Premiere/PCI", ROM_REVENGE, "revenge", { {"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}}, 0, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 128, 1, at_batman_init, NULL},
{"Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "Cyrix", cpus_6x86}, 0, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 128, 1, at_endeavor_init, NULL}, {"Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", { {"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}}, 0, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 128, 1, at_endeavor_init, NULL},
{"Award 430VX PCI", ROM_430VX, "430vx", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86}, 0, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 256, 1, at_i430vx_init, NULL}, {"Award 430VX PCI", ROM_430VX, "430vx", { {"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}}, 0, MODEL_AT|MODEL_PS2|MODEL_HAS_IDE, 1, 256, 1, at_i430vx_init, NULL},
{"", -1, "", {"", 0, "", 0, "", 0}, 0,0,0, 0} {"", -1, "", {{"", 0}, {"", 0}, {"", 0}}, 0,0,0, 0}
}; };
int model_count() int model_count()
@ -348,7 +350,7 @@ void ps2_m30_286_init()
dma16_init(); dma16_init();
ide_init(); ide_init();
keyboard_at_init(); keyboard_at_init();
mouse_ps2_init(); // mouse_ps2_init();
nvr_init(); nvr_init();
pic2_init(); pic2_init();
ps2board_init(); ps2board_init();
@ -365,7 +367,7 @@ static void ps2_common_init()
ide_init(); ide_init();
keyboard_at_init(); keyboard_at_init();
keyboard_at_init_ps2(); keyboard_at_init_ps2();
mouse_ps2_init(); // mouse_ps2_init();
nvr_init(); nvr_init();
pic2_init(); pic2_init();

2
src/mouse.h
View file

@ -19,7 +19,7 @@ typedef struct
char name[80]; char name[80];
void *(*init)(); void *(*init)();
void (*close)(void *p); void (*close)(void *p);
uint8_t (*poll)(int x, int y, int z, int b, void *p); void (*poll)(int x, int y, int z, int b, void *p);
int type; int type;
} mouse_t; } mouse_t;

1
src/mouse_ps2.c
View file

@ -1,3 +1,4 @@
#include <stdlib.h>
#include "ibm.h" #include "ibm.h"
#include "keyboard_at.h" #include "keyboard_at.h"
#include "mouse.h" #include "mouse.h"

5
src/mouse_serial.c
View file

@ -1,3 +1,4 @@
#include <stdlib.h>
#include "ibm.h" #include "ibm.h"
#include "mouse.h" #include "mouse.h"
#include "pic.h" #include "pic.h"
@ -46,7 +47,7 @@ void mouse_serial_poll(int x, int y, int z, int b, void *p)
} }
} }
void mouse_serial_rcr(SERIAL *serial, void *p) void mouse_serial_rcr(struct SERIAL *serial, void *p)
{ {
mouse_serial_t *mouse = (mouse_serial_t *)p; mouse_serial_t *mouse = (mouse_serial_t *)p;
@ -68,7 +69,7 @@ void mousecallback(void *p)
void *mouse_serial_init() void *mouse_serial_init()
{ {
mouse_serial_t *mouse = (mouse_t *)malloc(sizeof(mouse_serial_t)); mouse_serial_t *mouse = (mouse_serial_t *)malloc(sizeof(mouse_serial_t));
memset(mouse, 0, sizeof(mouse_serial_t)); memset(mouse, 0, sizeof(mouse_serial_t));
mouse->serial = &serial1; mouse->serial = &serial1;

1
src/nmi.c
View file

@ -1,4 +1,5 @@
#include "ibm.h" #include "ibm.h"
#include "io.h"
#include "nmi.h" #include "nmi.h"
int nmi_mask; int nmi_mask;

4
src/nvr.h
View file

@ -4,5 +4,7 @@ extern int enable_sync;
extern int nvr_dosave; extern int nvr_dosave;
void time_get(char *nvrram); void loadnvr();
void savenvr();
void nvr_recalc();

9
src/pc.c
View file

@ -15,6 +15,7 @@
#include "cdrom-null.h" #include "cdrom-null.h"
#include "config.h" #include "config.h"
#include "cpu.h" #include "cpu.h"
#include "disc_fdi.h"
#include "dma.h" #include "dma.h"
#include "fdc.h" #include "fdc.h"
#include "fdd.h" #include "fdd.h"
@ -22,24 +23,29 @@
#include "sound_gus.h" #include "sound_gus.h"
#include "ide.h" #include "ide.h"
#include "keyboard.h" #include "keyboard.h"
#include "keyboard_at.h"
#include "model.h" #include "model.h"
#include "mouse.h" #include "mouse.h"
#include "nvr.h" #include "nvr.h"
#include "pic.h" #include "pic.h"
#include "pit.h" #include "pit.h"
#include "plat-joystick.h" #include "plat-joystick.h"
#include "plat-keyboard.h"
#include "plat-midi.h"
#include "plat-mouse.h" #include "plat-mouse.h"
#include "serial.h" #include "serial.h"
#include "sound.h" #include "sound.h"
#include "sound_cms.h" #include "sound_cms.h"
#include "sound_opl.h" #include "sound_opl.h"
#include "sound_sb.h" #include "sound_sb.h"
#include "sound_speaker.h"
#include "sound_ssi2001.h" #include "sound_ssi2001.h"
#include "timer.h" #include "timer.h"
#include "vid_voodoo.h" #include "vid_voodoo.h"
#include "video.h" #include "video.h"
#include "amstrad.h" #include "amstrad.h"
#include "hdd.h" #include "hdd.h"
#include "x86.h"
int window_w, window_h, window_x, window_y, window_remember; int window_w, window_h, window_x, window_y, window_remember;
@ -115,8 +121,7 @@ void pollmouse()
pollmouse_delay = 2; pollmouse_delay = 2;
mouse_poll_host(); mouse_poll_host();
mouse_get_mickeys(&x, &y, &z); mouse_get_mickeys(&x, &y, &z);
if (mouse_poll) mouse_poll(x, y, z, mouse_buttons);
mouse_poll(x, y, z, mouse_buttons);
// if (mousecapture) position_mouse(64,64); // if (mousecapture) position_mouse(64,64);
} }

7
src/pci.c
View file

@ -59,6 +59,7 @@ uint8_t pci_read(uint16_t port, void *priv)
return 0xff; return 0xff;
} }
return 0xff;
} }
void pci_type2_write(uint16_t port, uint8_t val, void *priv); void pci_type2_write(uint16_t port, uint8_t val, void *priv);
@ -134,7 +135,11 @@ void pci_init(int type, int min_card, int max_card)
} }
for (c = 0; c < 32; c++) for (c = 0; c < 32; c++)
pci_card_read[c] = pci_card_write[c] = pci_priv[c] = NULL; {
pci_card_read[c] = NULL;
pci_card_write[c] = NULL;
pci_priv[c] = NULL;
}
pci_min_card = min_card; pci_min_card = min_card;
pci_max_card = max_card; pci_max_card = max_card;

2
src/pic.c
View file

@ -1,6 +1,8 @@
#include "ibm.h" #include "ibm.h"
#include "io.h" #include "io.h"
#include "pic.h" #include "pic.h"
#include "pit.h"
#include "video.h"
int output; int output;
int intclear; int intclear;

1
src/pic.h
View file

@ -7,3 +7,4 @@ void picintlevel(uint16_t num);
void picintc(uint16_t num); void picintc(uint16_t num);
uint8_t picinterrupt(); uint8_t picinterrupt();
void picclear(int num); void picclear(int num);
void dumppic();

4
src/pit.c
View file

@ -7,10 +7,12 @@
#include "ibm.h" #include "ibm.h"
#include "cpu.h" #include "cpu.h"
#include "device.h"
#include "dma.h" #include "dma.h"
#include "io.h" #include "io.h"
#include "pic.h" #include "pic.h"
#include "pit.h" #include "pit.h"
#include "sound_speaker.h"
#include "timer.h" #include "timer.h"
#include "video.h" #include "video.h"
#include "model.h" #include "model.h"
@ -455,7 +457,7 @@ uint8_t pit_read(uint16_t addr, void *p)
{ {
PIT *pit = (PIT *)p; PIT *pit = (PIT *)p;
int t; int t;
uint8_t temp; uint8_t temp = 0xff;
cycles -= (int)PITCONST; cycles -= (int)PITCONST;
// printf("Read PIT %04X ",addr); // printf("Read PIT %04X ",addr);
switch (addr&3) switch (addr&3)

2
src/plat-midi.h
View file

@ -1,3 +1,5 @@
void midi_init(); void midi_init();
void midi_close(); void midi_close();
void midi_write(uint8_t val); void midi_write(uint8_t val);
int midi_get_num_devs();
void midi_get_dev_name(int num, char *s);

4
src/ps1.c
View file

@ -1,8 +1,12 @@
#include "ibm.h" #include "ibm.h"
#include "cpu.h"
#include "io.h"
#include "mem.h" #include "mem.h"
#include "ps1.h" #include "ps1.h"
#include "rom.h" #include "rom.h"
#include "lpt.h" #include "lpt.h"
#include "serial.h"
#include "x86.h"
static rom_t ps1_high_rom; static rom_t ps1_high_rom;
static uint8_t ps1_92, ps1_94, ps1_102, ps1_103, ps1_104, ps1_105, ps1_190; static uint8_t ps1_92, ps1_94, ps1_102, ps1_103, ps1_104, ps1_105, ps1_190;

4
src/ps2.c
View file

@ -1,8 +1,10 @@
#include "ibm.h" #include "ibm.h"
#include "io.h"
#include "lpt.h"
#include "mem.h" #include "mem.h"
#include "ps2.h" #include "ps2.h"
#include "rom.h" #include "rom.h"
#include "lpt.h" #include "serial.h"
static uint8_t ps2_92, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190; static uint8_t ps2_92, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190;

10
src/ps2_mca.c
View file

@ -1,9 +1,13 @@
#include "ibm.h" #include "ibm.h"
#include "cpu.h"
#include "io.h"
#include "lpt.h"
#include "mca.h"
#include "mem.h" #include "mem.h"
#include "ps2_mca.h" #include "ps2_mca.h"
#include "rom.h" #include "rom.h"
#include "lpt.h" #include "serial.h"
#include "mca.h" #include "x86.h"
//static uint8_t ps2_92, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190; //static uint8_t ps2_92, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190;
@ -92,6 +96,7 @@ static uint8_t model_50_read(uint16_t port)
case 0x107: case 0x107:
return ps2.subaddr_hi; return ps2.subaddr_hi;
} }
return 0xff;
} }
static uint8_t model_55sx_read(uint16_t port) static uint8_t model_55sx_read(uint16_t port)
@ -115,6 +120,7 @@ static uint8_t model_55sx_read(uint16_t port)
case 0x107: case 0x107:
return ps2.subaddr_hi; return ps2.subaddr_hi;
} }
return 0xff;
} }
static void model_50_write(uint16_t port, uint8_t val) static void model_50_write(uint16_t port, uint8_t val)

1
src/rom.c
View file

@ -1,6 +1,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
#include "ibm.h" #include "ibm.h"
#include "config.h"
#include "mem.h" #include "mem.h"
#include "rom.h" #include "rom.h"

15
src/rtc.c
View file

@ -26,9 +26,6 @@ struct
int year; int year;
} internal_clock; } internal_clock;
/* When the RTC was last updated */
static time_t rtc_set_time = 0;
/* Table for days in each month */ /* Table for days in each month */
static int rtc_days_in_month[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; static int rtc_days_in_month[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
@ -88,7 +85,7 @@ void rtc_tick()
} }
/* Called when modifying the NVR registers */ /* Called when modifying the NVR registers */
void time_update(char *nvrram, int reg) void time_update(uint8_t *nvrram, int reg)
{ {
int temp; int temp;
@ -162,10 +159,8 @@ static void time_internal_set(struct tm *time_var)
internal_clock.year = time_var->tm_year + 1900; internal_clock.year = time_var->tm_year + 1900;
} }
static void time_set_nvrram(char *nvrram, struct tm *cur_time_tm) static void time_set_nvrram(uint8_t *nvrram, struct tm *cur_time_tm)
{ {
int dow, mon, year;
if (nvrram[RTC_REGB] & RTC_DM) if (nvrram[RTC_REGB] & RTC_DM)
{ {
nvrram[RTC_SECONDS] = cur_time_tm->tm_sec; nvrram[RTC_SECONDS] = cur_time_tm->tm_sec;
@ -208,7 +203,7 @@ static void time_set_nvrram(char *nvrram, struct tm *cur_time_tm)
} }
} }
void time_internal_set_nvrram(char *nvrram) void time_internal_set_nvrram(uint8_t *nvrram)
{ {
int temp; int temp;
@ -229,7 +224,7 @@ void time_internal_set_nvrram(char *nvrram)
internal_clock.year += (nvrram[RTC_REGB] & RTC_DM) ? 1900 : (DCB(nvrram[RTC_CENTURY]) * 100); internal_clock.year += (nvrram[RTC_REGB] & RTC_DM) ? 1900 : (DCB(nvrram[RTC_CENTURY]) * 100);
} }
void time_internal_sync(char *nvrram) void time_internal_sync(uint8_t *nvrram)
{ {
struct tm *cur_time_tm; struct tm *cur_time_tm;
time_t cur_time; time_t cur_time;
@ -242,7 +237,7 @@ void time_internal_sync(char *nvrram)
time_set_nvrram(nvrram, cur_time_tm); time_set_nvrram(nvrram, cur_time_tm);
} }
void time_get(char *nvrram) void time_get(uint8_t *nvrram)
{ {
struct tm cur_time_tm; struct tm cur_time_tm;

8
src/rtc.h
View file

@ -168,7 +168,7 @@ enum RTC_RD_BITS
}; };
void rtc_tick(); void rtc_tick();
void time_update(char *nvrram, int reg); void time_update(uint8_t *nvrram, int reg);
void time_get(char *nvrram); void time_get(uint8_t *nvrram);
void time_internal_set_nvrram(char *nvrram); void time_internal_set_nvrram(uint8_t *nvrram);
void time_internal_sync(char *nvrram); void time_internal_sync(uint8_t *nvrram);

6
src/scat.c
View file

@ -1,8 +1,10 @@
/*This is the chipset used in the Award 286 clone model*/ /*This is the chipset used in the Award 286 clone model*/
#include "ibm.h" #include "ibm.h"
#include "cpu.h"
#include "io.h" #include "io.h"
#include "scat.h"
#include "mem.h" #include "mem.h"
#include "scat.h"
#include "x86.h"
static uint8_t scat_regs[256]; static uint8_t scat_regs[256];
static int scat_index; static int scat_index;
@ -17,7 +19,7 @@ static mem_mapping_t scat_512k_clip_mapping;
void scat_shadow_state_update() void scat_shadow_state_update()
{ {
int i, val, val2; int i, val;
// TODO - Segment A000 to BFFF shadow ram enable features and ROM enable features should be implemented later. // TODO - Segment A000 to BFFF shadow ram enable features and ROM enable features should be implemented later.
for (i = 8; i < 24; i++) for (i = 8; i < 24; i++)

2
src/serial.c
View file

@ -120,7 +120,7 @@ void serial_write(uint16_t addr, uint8_t val, void *p)
if ((val & 2) && !(serial->mctrl & 2)) if ((val & 2) && !(serial->mctrl & 2))
{ {
if (serial->rcr_callback) if (serial->rcr_callback)
serial->rcr_callback(serial, serial->rcr_callback_p); serial->rcr_callback((struct SERIAL *)serial, serial->rcr_callback_p);
// pclog("RCR raised! sending M\n"); // pclog("RCR raised! sending M\n");
} }
serial->mctrl = val; serial->mctrl = val;

2
src/serial.h
View file

@ -27,4 +27,6 @@ typedef struct
int recieve_delay; int recieve_delay;
} SERIAL; } SERIAL;
void serial_write_fifo(SERIAL *serial, uint8_t dat);
extern SERIAL serial1, serial2; extern SERIAL serial1, serial2;

5
src/sound.c
View file

@ -3,6 +3,9 @@
#include "ibm.h" #include "ibm.h"
#include "device.h" #include "device.h"
#include "cdrom-ioctl.h"
#include "ide.h"
#include "filters.h" #include "filters.h"
#include "sound_opl.h" #include "sound_opl.h"
@ -107,7 +110,7 @@ static struct
static int sound_handlers_num; static int sound_handlers_num;
static int sound_poll_time = 0, sound_get_buffer_time = 0, sound_poll_latch; static int sound_poll_time = 0, sound_poll_latch;
int sound_pos_global = 0; int sound_pos_global = 0;
int soundon = 1; int soundon = 1;

9
src/sound.h
View file

@ -18,3 +18,12 @@ void sound_set_cd_volume(unsigned int vol_l, unsigned int vol_r);
extern int sound_pos_global; extern int sound_pos_global;
void sound_speed_changed(); void sound_speed_changed();
void sound_init();
void sound_reset();
void initalmain(int argc, char *argv[]);
void inital();
void givealbuffer(int32_t *buf);
void givealbuffer_cd(int16_t *buf);

7
src/sound_ad1848.c
View file

@ -1,8 +1,7 @@
/*PCem v0.8 by Tom Walker #include <math.h>
AD1848 CODEC emulation (Windows Sound System compatible)*/
#include "ibm.h" #include "ibm.h"
#include "dma.h"
#include "pic.h"
#include "sound.h" #include "sound.h"
#include "sound_ad1848.h" #include "sound_ad1848.h"

2
src/sound_ad1848.h
View file

@ -33,3 +33,5 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p);
void ad1848_update(ad1848_t *ad1848); void ad1848_update(ad1848_t *ad1848);
void ad1848_speed_changed(ad1848_t *ad1848); void ad1848_speed_changed(ad1848_t *ad1848);
void ad1848_init(ad1848_t *ad1848);

20
src/sound_emu8k.c
View file

@ -6,6 +6,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <math.h> #include <math.h>
#include "ibm.h" #include "ibm.h"
#include "io.h"
#include "device.h" #include "device.h"
#include "sound.h" #include "sound.h"
#include "sound_emu8k.h" #include "sound_emu8k.h"
@ -68,10 +69,10 @@ static inline void EMU8K_WRITE(emu8k_t *emu8k, uint32_t addr, uint16_t val)
static int ff = 0; static int ff = 0;
static int voice_count = 0; static int voice_count = 0;
uint16_t emu8k_inw(uint32_t addr, void *p) uint16_t emu8k_inw(uint16_t addr, void *p)
{ {
emu8k_t *emu8k = (emu8k_t *)p; emu8k_t *emu8k = (emu8k_t *)p;
uint16_t ret; uint16_t ret = 0xffff;
/* pclog("emu8k_inw %04X reg=%i voice=%i\n", addr, emu8k->cur_reg, emu8k->cur_voice);*/ /* pclog("emu8k_inw %04X reg=%i voice=%i\n", addr, emu8k->cur_reg, emu8k->cur_voice);*/
addr -= 0x220; addr -= 0x220;
@ -114,7 +115,7 @@ uint16_t emu8k_inw(uint32_t addr, void *p)
{ {
case 0: case 0:
{ {
uint32_t val = (emu8k->voice[emu8k->cur_voice].ccca & 0xff000000) | (emu8k->voice[emu8k->cur_voice].addr >> 8); // uint32_t val = (emu8k->voice[emu8k->cur_voice].ccca & 0xff000000) | (emu8k->voice[emu8k->cur_voice].addr >> 8);
READ16(addr, emu8k->voice[emu8k->cur_voice].ccca); READ16(addr, emu8k->voice[emu8k->cur_voice].ccca);
return ret; return ret;
} }
@ -170,7 +171,7 @@ uint16_t emu8k_inw(uint32_t addr, void *p)
{ {
case 0: case 0:
{ {
uint32_t val = (emu8k->voice[emu8k->cur_voice].ccca & 0xff000000) | (emu8k->voice[emu8k->cur_voice].addr >> 8); // uint32_t val = (emu8k->voice[emu8k->cur_voice].ccca & 0xff000000) | (emu8k->voice[emu8k->cur_voice].addr >> 8);
READ16(addr, emu8k->voice[emu8k->cur_voice].ccca); READ16(addr, emu8k->voice[emu8k->cur_voice].ccca);
return ret; return ret;
} }
@ -254,7 +255,7 @@ uint16_t emu8k_inw(uint32_t addr, void *p)
return 0xffff; return 0xffff;
} }
void emu8k_outw(uint32_t addr, uint16_t val, void *p) void emu8k_outw(uint16_t addr, uint16_t val, void *p)
{ {
emu8k_t *emu8k = (emu8k_t *)p; emu8k_t *emu8k = (emu8k_t *)p;
@ -487,14 +488,14 @@ void emu8k_outw(uint32_t addr, uint16_t val, void *p)
} }
} }
uint8_t emu8k_inb(uint32_t addr, void *p) uint8_t emu8k_inb(uint16_t addr, void *p)
{ {
if (addr & 1) if (addr & 1)
return emu8k_inw(addr & ~1, p) >> 1; return emu8k_inw(addr & ~1, p) >> 1;
return emu8k_inw(addr, p) & 0xff; return emu8k_inw(addr, p) & 0xff;
} }
void emu8k_outb(uint32_t addr, uint8_t val, void *p) void emu8k_outb(uint16_t addr, uint8_t val, void *p)
{ {
if (addr & 1) if (addr & 1)
emu8k_outw(addr & ~1, val << 8, p); emu8k_outw(addr & ~1, val << 8, p);
@ -510,7 +511,6 @@ void emu8k_update(emu8k_t *emu8k)
int32_t *buf; int32_t *buf;
int pos; int pos;
int c; int c;
int32_t out_l = 0, out_r = 0;
buf = &emu8k->buffer[emu8k->pos*2]; buf = &emu8k->buffer[emu8k->pos*2];
@ -526,9 +526,9 @@ void emu8k_update(emu8k_t *emu8k)
int32_t voice_l, voice_r; int32_t voice_l, voice_r;
int32_t dat; int32_t dat;
int lfo1_vibrato, lfo2_vibrato; int lfo1_vibrato, lfo2_vibrato;
int tremolo; // int tremolo;
tremolo = ((lfotable[(emu8k->voice[c].lfo1_count >> 8) & 4095] * emu8k->voice[c].lfo1_trem) * 4) >> 12; // tremolo = ((lfotable[(emu8k->voice[c].lfo1_count >> 8) & 4095] * emu8k->voice[c].lfo1_trem) * 4) >> 12;
if (freqtable[emu8k->voice[c].pitch] >> 32) if (freqtable[emu8k->voice[c].pitch] >> 32)
dat = EMU8K_READ(emu8k, emu8k->voice[c].addr >> 32); dat = EMU8K_READ(emu8k, emu8k->voice[c].addr >> 32);

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