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Implemented CR4 register for Winchip. Currently only Time Stamp Disable (TSD) has an effect.

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Fixed stupid bug in WRMSR - MSRs can now be written with values other than zero.
This commit is contained in:
TomW 2014-08-23 16:28:16 +01:00
commit 262b188790
6 changed files with 49 additions and 2 deletions
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8
src/cpu.c
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@ -20,6 +20,10 @@ int cpu_16bitbus;
int cpu_busspeed;
int cpu_hasrdtsc;
int cpu_hasMMX, cpu_hasMSR;
int cpu_hasCR4;
uint64_t cpu_CR4_mask;
uint64_t tsc = 0;
int timing_rr;
@ -267,6 +271,7 @@ void cpu_set()
cpu_hasrdtsc = 0;
cpu_hasMMX = 0;
cpu_hasMSR = 0;
cpu_hasCR4 = 0;
if (cpu_iscyrix)
io_sethandler(0x0022, 0x0002, cyrix_read, NULL, NULL, cyrix_write, NULL, NULL, NULL);
@ -413,6 +418,8 @@ void cpu_set()
cpu_hasrdtsc = 1;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
break;
default:
@ -549,7 +556,6 @@ void cpu_WRMSR()
switch (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type)
{
case CPU_WINCHIP:
EAX = EDX = 0;
switch (ECX)
{
case 0x02: