Retro/pcem
Watch
1
0
Fork
You've already forked pcem
 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.

Browse source
This commit is contained in:
SarahW 2016-11-25 21:32:02 +00:00
commit 1b73963997
33 changed files with 1139 additions and 261 deletions
Download patch file Download diff file Expand all files Collapse all files

21
src/x86_ops_xchg.h
View file

@ -6,6 +6,7 @@ static int opXCHG_b_a16(uint32_t fetchdat)
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
static int opXCHG_b_a32(uint32_t fetchdat)
@ -16,6 +17,7 @@ static int opXCHG_b_a32(uint32_t fetchdat)
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -27,6 +29,7 @@ static int opXCHG_w_a16(uint32_t fetchdat)
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
static int opXCHG_w_a32(uint32_t fetchdat)
@ -37,6 +40,7 @@ static int opXCHG_w_a32(uint32_t fetchdat)
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -48,6 +52,7 @@ static int opXCHG_l_a16(uint32_t fetchdat)
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
static int opXCHG_l_a32(uint32_t fetchdat)
@ -58,6 +63,7 @@ static int opXCHG_l_a32(uint32_t fetchdat)
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}
@ -68,6 +74,7 @@ static int opXCHG_AX_BX(uint32_t fetchdat)
AX = BX;
BX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_CX(uint32_t fetchdat)
@ -76,6 +83,7 @@ static int opXCHG_AX_CX(uint32_t fetchdat)
AX = CX;
CX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_DX(uint32_t fetchdat)
@ -84,6 +92,7 @@ static int opXCHG_AX_DX(uint32_t fetchdat)
AX = DX;
DX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_SI(uint32_t fetchdat)
@ -92,6 +101,7 @@ static int opXCHG_AX_SI(uint32_t fetchdat)
AX = SI;
SI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_DI(uint32_t fetchdat)
@ -100,6 +110,7 @@ static int opXCHG_AX_DI(uint32_t fetchdat)
AX = DI;
DI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_BP(uint32_t fetchdat)
@ -108,6 +119,7 @@ static int opXCHG_AX_BP(uint32_t fetchdat)
AX = BP;
BP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_SP(uint32_t fetchdat)
@ -116,6 +128,7 @@ static int opXCHG_AX_SP(uint32_t fetchdat)
AX = SP;
SP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -125,6 +138,7 @@ static int opXCHG_EAX_EBX(uint32_t fetchdat)
EAX = EBX;
EBX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_ECX(uint32_t fetchdat)
@ -133,6 +147,7 @@ static int opXCHG_EAX_ECX(uint32_t fetchdat)
EAX = ECX;
ECX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_EDX(uint32_t fetchdat)
@ -141,6 +156,7 @@ static int opXCHG_EAX_EDX(uint32_t fetchdat)
EAX = EDX;
EDX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_ESI(uint32_t fetchdat)
@ -149,6 +165,7 @@ static int opXCHG_EAX_ESI(uint32_t fetchdat)
EAX = ESI;
ESI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_EDI(uint32_t fetchdat)
@ -157,6 +174,7 @@ static int opXCHG_EAX_EDI(uint32_t fetchdat)
EAX = EDI;
EDI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_EBP(uint32_t fetchdat)
@ -165,6 +183,7 @@ static int opXCHG_EAX_EBP(uint32_t fetchdat)
EAX = EBP;
EBP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_ESP(uint32_t fetchdat)
@ -173,6 +192,7 @@ static int opXCHG_EAX_ESP(uint32_t fetchdat)
EAX = ESP;
ESP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -182,6 +202,7 @@ static int opXCHG_EAX_ESP(uint32_t fetchdat)
{ \
reg = (reg >> 24) | ((reg >> 8) & 0xff00) | ((reg << 8) & 0xff0000) | ((reg << 24) & 0xff000000); \
CLOCK_CYCLES(1); \
PREFETCH_RUN(1, 1, -1, 0,0,0,0, 0); \
return 0; \
}