Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.
This commit is contained in:
SarahW
parent
c5889e311f
commit
1b73963997
33 changed files with 1139 additions and 261 deletions
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@ -1,4 +1,4 @@
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#define OP_SHIFT_b(c) \
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#define OP_SHIFT_b(c, ea32) \
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{ \
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uint8_t temp_orig = temp; \
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if (!c) return 0; \
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@ -17,6 +17,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x08: /*ROR b,CL*/ \
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while (c > 0) \
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@ -31,6 +32,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL b,CL*/ \
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temp2 = flags & C_FLAG; \
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@ -47,6 +49,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x18: /*RCR b,CL*/ \
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temp2 = flags & C_FLAG; \
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@ -63,27 +66,31 @@
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x20: case 0x30: /*SHL b,CL*/ \
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seteab(temp << c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x28: /*SHR b,CL*/ \
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seteab(temp >> c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x38: /*SAR b,CL*/ \
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temp = (int8_t)temp >> c; \
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seteab(temp); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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} \
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}
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#define OP_SHIFT_w(c) \
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#define OP_SHIFT_w(c, ea32) \
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{ \
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uint16_t temp_orig = temp; \
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if (!c) return 0; \
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@ -102,6 +109,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x08: /*ROR w, c*/ \
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while (c > 0) \
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@ -116,6 +124,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL w, c*/ \
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temp2 = flags & C_FLAG; \
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@ -132,6 +141,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x18: /*RCR w, c*/ \
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temp2 = flags & C_FLAG; \
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@ -148,27 +158,31 @@
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x20: case 0x30: /*SHL w, c*/ \
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seteaw(temp << c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x28: /*SHR w, c*/ \
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seteaw(temp >> c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x38: /*SAR w, c*/ \
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temp = (int16_t)temp >> c; \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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} \
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}
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#define OP_SHIFT_l(c) \
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#define OP_SHIFT_l(c, ea32) \
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{ \
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uint32_t temp_orig = temp; \
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if (!c) return 0; \
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@ -187,6 +201,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x08: /*ROR l, c*/ \
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while (c > 0) \
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@ -201,6 +216,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x10: /*RCL l, c*/ \
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temp2 = CF_SET(); \
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@ -217,6 +233,7 @@
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x18: /*RCR l, c*/ \
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temp2 = flags & C_FLAG; \
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@ -233,22 +250,26 @@
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x20: case 0x30: /*SHL l, c*/ \
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seteal(temp << c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x28: /*SHR l, c*/ \
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seteal(temp >> c); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x38: /*SAR l, c*/ \
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temp = (int32_t)temp >> c; \
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seteal(temp); if (cpu_state.abrt) return 1; \
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set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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} \
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}
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@ -261,8 +282,9 @@ static int opC0_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c);
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OP_SHIFT_b(c, 0);
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return 0;
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}
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static int opC0_a32(uint32_t fetchdat)
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@ -273,8 +295,9 @@ static int opC0_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c);
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OP_SHIFT_b(c, 1);
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return 0;
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}
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static int opC1_w_a16(uint32_t fetchdat)
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@ -285,8 +308,9 @@ static int opC1_w_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c);
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OP_SHIFT_w(c, 0);
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return 0;
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}
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static int opC1_w_a32(uint32_t fetchdat)
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@ -297,8 +321,9 @@ static int opC1_w_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c);
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OP_SHIFT_w(c, 1);
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return 0;
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}
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static int opC1_l_a16(uint32_t fetchdat)
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@ -309,8 +334,9 @@ static int opC1_l_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteal(); if (cpu_state.abrt) return 1;
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OP_SHIFT_l(c);
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OP_SHIFT_l(c, 0);
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return 0;
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}
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static int opC1_l_a32(uint32_t fetchdat)
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@ -321,8 +347,9 @@ static int opC1_l_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
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PREFETCH_PREFIX();
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temp = geteal(); if (cpu_state.abrt) return 1;
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OP_SHIFT_l(c);
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OP_SHIFT_l(c, 1);
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return 0;
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}
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@ -334,7 +361,7 @@ static int opD0_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c);
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OP_SHIFT_b(c, 0);
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return 0;
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}
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static int opD0_a32(uint32_t fetchdat)
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@ -345,7 +372,7 @@ static int opD0_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c);
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OP_SHIFT_b(c, 1);
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return 0;
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}
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static int opD1_w_a16(uint32_t fetchdat)
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@ -356,7 +383,7 @@ static int opD1_w_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c);
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OP_SHIFT_w(c, 0);
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return 0;
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}
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static int opD1_w_a32(uint32_t fetchdat)
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@ -367,7 +394,7 @@ static int opD1_w_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c);
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OP_SHIFT_w(c, 1);
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return 0;
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}
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static int opD1_l_a16(uint32_t fetchdat)
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@ -378,7 +405,7 @@ static int opD1_l_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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temp = geteal(); if (cpu_state.abrt) return 1;
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OP_SHIFT_l(c);
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OP_SHIFT_l(c, 0);
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return 0;
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}
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static int opD1_l_a32(uint32_t fetchdat)
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@ -389,7 +416,7 @@ static int opD1_l_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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temp = geteal(); if (cpu_state.abrt) return 1;
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OP_SHIFT_l(c);
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OP_SHIFT_l(c, 1);
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return 0;
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}
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@ -402,7 +429,7 @@ static int opD2_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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c = CL & 31;
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c);
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OP_SHIFT_b(c, 0);
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return 0;
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}
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static int opD2_a32(uint32_t fetchdat)
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@ -414,7 +441,7 @@ static int opD2_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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c = CL & 31;
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temp = geteab(); if (cpu_state.abrt) return 1;
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OP_SHIFT_b(c);
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OP_SHIFT_b(c, 1);
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return 0;
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}
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static int opD3_w_a16(uint32_t fetchdat)
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@ -426,7 +453,7 @@ static int opD3_w_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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c = CL & 31;
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c);
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OP_SHIFT_w(c, 0);
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return 0;
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}
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static int opD3_w_a32(uint32_t fetchdat)
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@ -438,7 +465,7 @@ static int opD3_w_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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c = CL & 31;
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temp = geteaw(); if (cpu_state.abrt) return 1;
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OP_SHIFT_w(c);
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OP_SHIFT_w(c, 1);
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return 0;
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}
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static int opD3_l_a16(uint32_t fetchdat)
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@ -450,7 +477,7 @@ static int opD3_l_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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c = CL & 31;
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temp = geteal(); if (cpu_state.abrt) return 1;
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OP_SHIFT_l(c);
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OP_SHIFT_l(c, 0);
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return 0;
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}
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static int opD3_l_a32(uint32_t fetchdat)
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@ -462,7 +489,7 @@ static int opD3_l_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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c = CL & 31;
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temp = geteal(); if (cpu_state.abrt) return 1;
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OP_SHIFT_l(c);
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OP_SHIFT_l(c, 1);
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return 0;
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}
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||||
|
||||
|
|
@ -529,6 +556,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
operation(); \
|
||||
\
|
||||
CLOCK_CYCLES(3); \
|
||||
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## operation ## _CL_a16(uint32_t fetchdat) \
|
||||
|
|
@ -540,6 +568,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
operation(); \
|
||||
\
|
||||
CLOCK_CYCLES(3); \
|
||||
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## operation ## _i_a32(uint32_t fetchdat) \
|
||||
|
|
@ -551,6 +580,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
operation(); \
|
||||
\
|
||||
CLOCK_CYCLES(3); \
|
||||
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## operation ## _CL_a32(uint32_t fetchdat) \
|
||||
|
|
@ -562,6 +592,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
operation(); \
|
||||
\
|
||||
CLOCK_CYCLES(3); \
|
||||
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue