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Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.

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This commit is contained in:
SarahW 2016-11-25 21:32:02 +00:00
commit 1b73963997
33 changed files with 1139 additions and 261 deletions
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18
src/x86_ops_mov_seg.h
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@ -25,6 +25,7 @@ static int opMOV_w_seg_a16(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return cpu_state.abrt;
}
static int opMOV_w_seg_a32(uint32_t fetchdat)
@ -54,6 +55,7 @@ static int opMOV_w_seg_a32(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return cpu_state.abrt;
}
@ -90,6 +92,7 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return cpu_state.abrt;
}
static int opMOV_l_seg_a32(uint32_t fetchdat)
@ -125,6 +128,7 @@ static int opMOV_l_seg_a32(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return cpu_state.abrt;
}
@ -165,6 +169,7 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return cpu_state.abrt;
}
static int opMOV_seg_w_a32(uint32_t fetchdat)
@ -204,6 +209,7 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return cpu_state.abrt;
}
@ -220,6 +226,7 @@ static int opLDS_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0);
return 0;
}
static int opLDS_w_a32(uint32_t fetchdat)
@ -234,6 +241,7 @@ static int opLDS_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1);
return 0;
}
static int opLDS_l_a16(uint32_t fetchdat)
@ -249,6 +257,7 @@ static int opLDS_l_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 0);
return 0;
}
static int opLDS_l_a32(uint32_t fetchdat)
@ -264,6 +273,7 @@ static int opLDS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 1);
return 0;
}
@ -279,6 +289,7 @@ static int opLSS_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0);
return 1;
}
static int opLSS_w_a32(uint32_t fetchdat)
@ -293,6 +304,7 @@ static int opLSS_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1);
return 1;
}
static int opLSS_l_a16(uint32_t fetchdat)
@ -308,6 +320,7 @@ static int opLSS_l_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0);
return 1;
}
static int opLSS_l_a32(uint32_t fetchdat)
@ -323,6 +336,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1);
return 1;
}
@ -339,6 +353,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0); \
return 0; \
} \
\
@ -354,6 +369,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1); \
return 0; \
} \
\
@ -370,6 +386,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 0); \
return 0; \
} \
\
@ -386,6 +403,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 1); \
return 0; \
}