Retro/pcem
Watch
1
0
Fork
You've already forked pcem
 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.

Browse source
This commit is contained in:
SarahW 2016-11-25 21:32:02 +00:00
commit 1b73963997
33 changed files with 1139 additions and 261 deletions
Download patch file Download diff file Expand all files Collapse all files

28
src/x86_ops_mov_ctrl.h
View file

@ -33,6 +33,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_CRx_a32(uint32_t fetchdat)
@ -70,6 +71,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -84,6 +86,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_DRx_a32(uint32_t fetchdat)
@ -97,11 +100,14 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
static int opMOV_CRx_r_a16(uint32_t fetchdat)
{
uint32_t old_cr0 = cr0;
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
@ -119,6 +125,12 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
if (is486 && !(cr0 & (1 << 30)))
cpu_cache_int_enabled = 1;
else
cpu_cache_int_enabled = 0;
if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
cpu_update_waitstates();
break;
case 2:
cr2 = cpu_state.regs[cpu_rm].l;
@ -141,10 +153,13 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_CRx_r_a32(uint32_t fetchdat)
{
uint32_t old_cr0 = cr0;
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
@ -162,6 +177,12 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
if (is486 && !(cr0 & (1 << 30)))
cpu_cache_int_enabled = 1;
else
cpu_cache_int_enabled = 0;
if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
cpu_update_waitstates();
break;
case 2:
cr2 = cpu_state.regs[cpu_rm].l;
@ -184,6 +205,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -198,6 +220,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_DRx_r_a32(uint32_t fetchdat)
@ -211,6 +234,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
fetch_ea_16(fetchdat);
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -225,6 +249,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_TRx_a32(uint32_t fetchdat)
@ -238,6 +263,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -251,6 +277,7 @@ static int opMOV_TRx_r_a16(uint32_t fetchdat)
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_TRx_r_a32(uint32_t fetchdat)
@ -263,6 +290,7 @@ static int opMOV_TRx_r_a32(uint32_t fetchdat)
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}