Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.
This commit is contained in:
parent
c5889e311f
commit
1b73963997
33 changed files with 1139 additions and 261 deletions
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@ -2,48 +2,56 @@ static int opMOV_AL_imm(uint32_t fetchdat)
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{
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AL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_AH_imm(uint32_t fetchdat)
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{
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AH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_BL_imm(uint32_t fetchdat)
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{
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BL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_BH_imm(uint32_t fetchdat)
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{
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BH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_CL_imm(uint32_t fetchdat)
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{
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CL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_CH_imm(uint32_t fetchdat)
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{
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CH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_DL_imm(uint32_t fetchdat)
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{
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DL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_DH_imm(uint32_t fetchdat)
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{
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DH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
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return 0;
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}
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@ -51,48 +59,56 @@ static int opMOV_AX_imm(uint32_t fetchdat)
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{
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AX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_BX_imm(uint32_t fetchdat)
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{
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BX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_CX_imm(uint32_t fetchdat)
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{
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CX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_DX_imm(uint32_t fetchdat)
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{
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DX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_SI_imm(uint32_t fetchdat)
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{
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SI = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_DI_imm(uint32_t fetchdat)
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{
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DI = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_BP_imm(uint32_t fetchdat)
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{
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BP = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_SP_imm(uint32_t fetchdat)
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{
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SP = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
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return 0;
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}
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@ -101,6 +117,7 @@ static int opMOV_EAX_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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EAX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_EBX_imm(uint32_t fetchdat)
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@ -108,6 +125,7 @@ static int opMOV_EBX_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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EBX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_ECX_imm(uint32_t fetchdat)
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@ -115,6 +133,7 @@ static int opMOV_ECX_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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ECX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_EDX_imm(uint32_t fetchdat)
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@ -122,6 +141,7 @@ static int opMOV_EDX_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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EDX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_ESI_imm(uint32_t fetchdat)
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@ -129,6 +149,7 @@ static int opMOV_ESI_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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ESI = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_EDI_imm(uint32_t fetchdat)
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@ -136,6 +157,7 @@ static int opMOV_EDI_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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EDI = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_EBP_imm(uint32_t fetchdat)
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@ -143,6 +165,7 @@ static int opMOV_EBP_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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EBP = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_ESP_imm(uint32_t fetchdat)
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@ -150,6 +173,7 @@ static int opMOV_ESP_imm(uint32_t fetchdat)
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uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
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ESP = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
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return 0;
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}
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@ -161,6 +185,7 @@ static int opMOV_b_imm_a16(uint32_t fetchdat)
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CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
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seteab(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_b_imm_a32(uint32_t fetchdat)
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@ -170,6 +195,7 @@ static int opMOV_b_imm_a32(uint32_t fetchdat)
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temp = getbyte(); if (cpu_state.abrt) return 1;
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seteab(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 1);
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return cpu_state.abrt;
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}
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@ -180,6 +206,7 @@ static int opMOV_w_imm_a16(uint32_t fetchdat)
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temp = getword(); if (cpu_state.abrt) return 1;
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seteaw(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 4, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_w_imm_a32(uint32_t fetchdat)
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@ -189,6 +216,7 @@ static int opMOV_w_imm_a32(uint32_t fetchdat)
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temp = getword(); if (cpu_state.abrt) return 1;
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seteaw(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 4, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_l_imm_a16(uint32_t fetchdat)
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@ -198,6 +226,7 @@ static int opMOV_l_imm_a16(uint32_t fetchdat)
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temp = getlong(); if (cpu_state.abrt) return 1;
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seteal(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 6, rmdat, 0,0,0,(cpu_mod == 3) ? 1:0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_l_imm_a32(uint32_t fetchdat)
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@ -207,6 +236,7 @@ static int opMOV_l_imm_a32(uint32_t fetchdat)
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temp = getlong(); if (cpu_state.abrt) return 1;
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seteal(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 6, rmdat, 0,0,0,(cpu_mod == 3) ? 1:0, 1);
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return cpu_state.abrt;
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}
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@ -217,6 +247,7 @@ static int opMOV_AL_a16(uint32_t fetchdat)
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uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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AL = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 3, -1, 1,0,0,0, 0);
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return 0;
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}
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static int opMOV_AL_a32(uint32_t fetchdat)
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@ -225,6 +256,7 @@ static int opMOV_AL_a32(uint32_t fetchdat)
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uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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AL = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 5, -1, 1,0,0,0, 1);
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return 0;
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}
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static int opMOV_AX_a16(uint32_t fetchdat)
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@ -233,6 +265,7 @@ static int opMOV_AX_a16(uint32_t fetchdat)
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uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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AX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 3, -1, 1,0,0,0, 0);
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return 0;
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}
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static int opMOV_AX_a32(uint32_t fetchdat)
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@ -241,6 +274,7 @@ static int opMOV_AX_a32(uint32_t fetchdat)
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uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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AX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 5, -1, 1,0,0,0, 1);
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return 0;
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}
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static int opMOV_EAX_a16(uint32_t fetchdat)
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@ -249,6 +283,7 @@ static int opMOV_EAX_a16(uint32_t fetchdat)
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uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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EAX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 3, -1, 0,1,0,0, 0);
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return 0;
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}
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static int opMOV_EAX_a32(uint32_t fetchdat)
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@ -257,6 +292,7 @@ static int opMOV_EAX_a32(uint32_t fetchdat)
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uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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EAX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 5, -1, 0,1,0,0, 1);
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return 0;
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}
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@ -265,6 +301,7 @@ static int opMOV_a16_AL(uint32_t fetchdat)
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uint16_t addr = getwordf();
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writememb(cpu_state.ea_seg->base, addr, AL);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_a32_AL(uint32_t fetchdat)
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@ -272,6 +309,7 @@ static int opMOV_a32_AL(uint32_t fetchdat)
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uint32_t addr = getlong();
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writememb(cpu_state.ea_seg->base, addr, AL);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 5, -1, 0,0,1,0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_a16_AX(uint32_t fetchdat)
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@ -279,6 +317,7 @@ static int opMOV_a16_AX(uint32_t fetchdat)
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uint16_t addr = getwordf();
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writememw(cpu_state.ea_seg->base, addr, AX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_a32_AX(uint32_t fetchdat)
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@ -286,6 +325,7 @@ static int opMOV_a32_AX(uint32_t fetchdat)
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uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
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writememw(cpu_state.ea_seg->base, addr, AX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 5, -1, 0,0,1,0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_a16_EAX(uint32_t fetchdat)
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@ -293,6 +333,7 @@ static int opMOV_a16_EAX(uint32_t fetchdat)
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uint16_t addr = getwordf();
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writememl(cpu_state.ea_seg->base, addr, EAX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 3, -1, 0,0,0,1, 0);
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return cpu_state.abrt;
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}
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static int opMOV_a32_EAX(uint32_t fetchdat)
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@ -300,6 +341,7 @@ static int opMOV_a32_EAX(uint32_t fetchdat)
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uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
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writememl(cpu_state.ea_seg->base, addr, EAX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 5, -1, 0,0,0,1, 1);
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return cpu_state.abrt;
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}
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@ -310,6 +352,7 @@ static int opLEA_w_a16(uint32_t fetchdat)
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opLEA_w_a32(uint32_t fetchdat)
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@ -318,6 +361,7 @@ static int opLEA_w_a32(uint32_t fetchdat)
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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@ -327,6 +371,7 @@ static int opLEA_l_a16(uint32_t fetchdat)
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].l = cpu_state.eaaddr & 0xffff;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opLEA_l_a32(uint32_t fetchdat)
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@ -335,6 +380,7 @@ static int opLEA_l_a32(uint32_t fetchdat)
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].l = cpu_state.eaaddr;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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@ -346,6 +392,7 @@ static int opXLAT_a16(uint32_t fetchdat)
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uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
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AL = temp;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
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return 0;
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}
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static int opXLAT_a32(uint32_t fetchdat)
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@ -354,6 +401,7 @@ static int opXLAT_a32(uint32_t fetchdat)
|
|||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -364,12 +412,14 @@ static int opMOV_b_r_a16(uint32_t fetchdat)
|
|||
{
|
||||
setr8(cpu_rm, getr8(cpu_reg));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 0);
|
||||
}
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -380,12 +430,14 @@ static int opMOV_b_r_a32(uint32_t fetchdat)
|
|||
{
|
||||
setr8(cpu_rm, getr8(cpu_reg));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 1);
|
||||
}
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -396,12 +448,14 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 0);
|
||||
}
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -412,12 +466,14 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 1);
|
||||
}
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -428,12 +484,14 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
PREFETCH_RUN(2, 2, rmdat, 0,0,0,1, 0);
|
||||
}
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -444,12 +502,14 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
PREFETCH_RUN(2, 2, rmdat, 0,0,0,1, 1);
|
||||
}
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -461,6 +521,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
|||
{
|
||||
setr8(cpu_reg, getr8(cpu_rm));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -469,6 +530,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
|||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -479,6 +541,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
|||
{
|
||||
setr8(cpu_reg, getr8(cpu_rm));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -487,6 +550,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
|||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -497,6 +561,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -505,6 +570,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
|||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -515,6 +581,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -523,6 +590,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
|||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -533,6 +601,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -541,6 +610,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
|||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 0,1,0,0, 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -551,6 +621,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -559,6 +630,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 0,1,0,0, 1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue