Perform NULL segment checks upfront in opcode handlers, rather than on every memory access.
This removes the need to pass the segment to readmem*l()/writemem*l().
This commit is contained in:
SarahW
parent
648aa0e3e8
commit
0f0a1c3223
31 changed files with 976 additions and 325 deletions
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@ -4,14 +4,14 @@ extern uint16_t ea_rseg;
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#undef writememb
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#define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF)?readmemb386l(s,a): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uint32_t)((s) + (a))) )
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#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 7))?readmemql(s,a):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1)?readmemb386l((s)+(a)): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uint32_t)((s) + (a))) )
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#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 7))?readmemql((s)+(a)):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememb386l(s,a,v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1) writememb386l((s)+(a),v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl(s,a,v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll(s,a,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 7)) writememql(s,a,v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1)) writememwl((s)+(a),v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3)) writememll((s)+(a),v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 7)) writememql((s)+(a),v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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int checkio(int port);
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@ -37,6 +37,26 @@ int checkio(int port);
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} \
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}
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#define SEG_CHECK_READ(seg) \
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do \
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{ \
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if ((seg)->base == 0xffffffff) \
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{ \
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x86gpf("Segment can't read", 0);\
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return 1; \
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} \
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} while (0)
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#define SEG_CHECK_WRITE(seg) \
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do \
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{ \
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if ((seg)->base == 0xffffffff) \
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{ \
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x86gpf("Segment can't write", 0);\
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return 1; \
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} \
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} while (0)
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#define CHECK_READ(seg, low, high) \
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if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || ((msw & 1) && !(eflags & VM_FLAG) && (((seg)->access & 10) == 8))) \
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{ \
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@ -156,7 +176,7 @@ static inline uint8_t geteab()
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return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm&3].b.l;
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if (eal_r)
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return *(uint8_t *)eal_r;
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return readmemb(easeg, cpu_state.eaaddr);
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return readmemb(easeg,cpu_state.eaaddr);
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}
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static inline uint16_t geteaw()
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@ -166,7 +186,7 @@ static inline uint16_t geteaw()
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// cycles-=3;
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if (eal_r)
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return *(uint16_t *)eal_r;
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return readmemw(easeg, cpu_state.eaaddr);
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return readmemw(easeg,cpu_state.eaaddr);
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}
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static inline uint32_t geteal()
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@ -176,12 +196,12 @@ static inline uint32_t geteal()
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// cycles-=3;
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if (eal_r)
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return *eal_r;
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return readmeml(easeg, cpu_state.eaaddr);
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return readmeml(easeg,cpu_state.eaaddr);
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}
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static inline uint64_t geteaq()
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{
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return readmemq(easeg, cpu_state.eaaddr);
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return readmemq(easeg,cpu_state.eaaddr);
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}
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static inline uint8_t geteab_mem()
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@ -202,16 +222,16 @@ static inline uint32_t geteal_mem()
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static inline void seteaq(uint64_t v)
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{
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writememql(easeg, cpu_state.eaaddr, v);
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writememql(easeg+cpu_state.eaaddr, v);
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}
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#define seteab(v) if (cpu_mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
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#define seteab(v) if (cpu_mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg+cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,cpu_state.eaaddr,v);
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#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,cpu_state.eaaddr,v);
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#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg,cpu_state.eaaddr,v);
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg+cpu_state.eaaddr,v);
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#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg+cpu_state.eaaddr,v);
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#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg+cpu_state.eaaddr,v);
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#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
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#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
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@ -429,7 +429,7 @@ int checkio(int port)
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// pclog("CheckIO %04X %01X %01X %02X %04X %04X %08X ",CS,CPL,IOPL,port,t,t+(port>>3),tr.base+t+(port>>3));
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if ((t+(port>>3))>tr.limit) return 1;
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cpl_override = 1;
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d = readmemb386l(0, tr.base + t + (port >> 3));
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d = readmemb386l(tr.base + t + (port >> 3));
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// d=readmemb(tr.base,t+(port>>3));
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cpl_override = 0;
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// pclog("%02X %02X\n",d,d&(1<<(port&7)));
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20
src/808x.c
20
src/808x.c
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@ -38,13 +38,6 @@ int nopageerrors=0;
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void FETCHCOMPLETE();
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uint8_t readmembl(uint32_t addr);
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void writemembl(uint32_t addr, uint8_t val);
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uint16_t readmemwl(uint32_t seg, uint32_t addr);
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void writememwl(uint32_t seg, uint32_t addr, uint16_t val);
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uint32_t readmemll(uint32_t seg, uint32_t addr);
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void writememll(uint32_t seg, uint32_t addr, uint32_t val);
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#undef readmemb
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#undef readmemw
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uint8_t readmemb(uint32_t a)
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@ -63,7 +56,7 @@ uint8_t readmembf(uint32_t a)
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uint16_t readmemw(uint32_t s, uint16_t a)
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{
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if (a!=(cs+cpu_state.pc)) memcycs+=(8>>is8086);
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if ((readlookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF)) return readmemwl(s,a);
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if ((readlookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF)) return readmemwl(s+a);
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else return *(uint16_t *)(readlookup2[(s + a) >> 12] + s + a);
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}
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@ -76,24 +69,21 @@ void refreshread() { /*pclog("Refreshread\n"); */FETCHCOMPLETE(); memcycs+=4; }
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cpu_rm=rmdat&7; \
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if (cpu_mod!=3) fetcheal(); }
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void writemembl(uint32_t addr, uint8_t val);
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void writememb(uint32_t a, uint8_t v)
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{
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memcycs+=4;
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if (writelookup2[(a)>>12]==-1) writemembl(a,v);
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else *(uint8_t *)(writelookup2[a >> 12] + a) = v;
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}
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void writememwl(uint32_t seg, uint32_t addr, uint16_t val);
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void writememw(uint32_t s, uint32_t a, uint16_t v)
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{
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memcycs+=(8>>is8086);
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if (writelookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememwl(s,a,v);
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if (writelookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememwl(s+a,v);
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else *(uint16_t *)(writelookup2[(s + a) >> 12] + s + a) = v;
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}
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void writememll(uint32_t seg, uint32_t addr, uint32_t val);
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void writememl(uint32_t s, uint32_t a, uint32_t v)
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{
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if (writelookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememll(s,a,v);
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if (writelookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememll(s+a,v);
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else *(uint32_t *)(writelookup2[(s + a) >> 12] + s + a) = v;
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}
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@ -538,10 +528,10 @@ void dumpregs()
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fclose(f);*/
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pclog("Dumping rram4.dmp\n");
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f=fopen("rram4.dmp","wb");
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for (c=0;c<0x0050000;c++)
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for (c=0;c<0x0050000;c++)
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{
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cpu_state.abrt = 0;
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putc(readmemb386l(0,c+0x80000000),f);
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putc(readmemb386l(c+0x80000000),f);
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}
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fclose(f);
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pclog("Dumping done\n");
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20
src/ibm.h
20
src/ibm.h
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@ -31,8 +31,8 @@ int writelnext;
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extern int mmu_perm;
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#define readmemb(a) ((readlookup2[(a)>>12]==-1)?readmembl(a):*(uint8_t *)(readlookup2[(a) >> 12] + (a)))
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#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl(s,a):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 3))?readmemll(s,a):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1))?readmemwl((s)+(a)):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3))?readmemll((s)+(a)):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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//#define writememb(a,v) if (writelookup2[(a)>>12]==0xFFFFFFFF) writemembl(a,v); else ram[writelookup2[(a)>>12]+((a)&0xFFF)]=v
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//#define writememw(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememwl(s,a,v); else *((uint16_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v
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@ -43,14 +43,14 @@ extern int mmu_perm;
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//void writememb(uint32_t addr, uint8_t val);
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uint8_t readmembl(uint32_t addr);
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void writemembl(uint32_t addr, uint8_t val);
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uint8_t readmemb386l(uint32_t seg, uint32_t addr);
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void writememb386l(uint32_t seg, uint32_t addr, uint8_t val);
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uint16_t readmemwl(uint32_t seg, uint32_t addr);
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void writememwl(uint32_t seg, uint32_t addr, uint16_t val);
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uint32_t readmemll(uint32_t seg, uint32_t addr);
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void writememll(uint32_t seg, uint32_t addr, uint32_t val);
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uint64_t readmemql(uint32_t seg, uint32_t addr);
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void writememql(uint32_t seg, uint32_t addr, uint64_t val);
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uint8_t readmemb386l(uint32_t addr);
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void writememb386l(uint32_t addr, uint8_t val);
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uint16_t readmemwl(uint32_t addr);
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void writememwl(uint32_t addr, uint16_t val);
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uint32_t readmemll(uint32_t addr);
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void writememll(uint32_t addr, uint32_t val);
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uint64_t readmemql(uint32_t addr);
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void writememql(uint32_t addr, uint64_t val);
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uint8_t *getpccache(uint32_t a);
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340
src/mem.c
340
src/mem.c
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@ -295,7 +295,6 @@ uint32_t mmutranslatereal(uint32_t addr, int rw)
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if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && ((CPL == 3 && !cpl_override) || cr0&WP_FLAG)))
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{
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// if (!nopageerrors) pclog("Page not present! %08X %08X %02X %02X %i %08X %04X:%08X %04X:%08X %i %i %i\n",addr,temp,opcode,opcode2,frame,rmdat32, CS,pc,SS,ESP,ins,CPL,rw);
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// dumpregs();
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// exit(-1);
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// if (addr == 0x815F6E90) output = 3;
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@ -498,15 +497,9 @@ void writemembl(uint32_t addr, uint8_t val)
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// else pclog("Bad writemembl %08X %02X %04X:%08X\n", addr, val, CS, pc);
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}
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uint8_t readmemb386l(uint32_t seg, uint32_t addr)
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uint8_t readmemb386l(uint32_t addr)
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{
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if (seg==-1)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! rb %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return -1;
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}
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mem_logical_addr = addr = addr + seg;
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mem_logical_addr = addr;
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/* if (readlookup2[mem_logical_addr >> 12] != 0xFFFFFFFF)
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{
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return ram[readlookup2[mem_logical_addr >> 12] + (mem_logical_addr & 0xFFF)];
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@ -525,16 +518,9 @@ uint8_t readmemb386l(uint32_t seg, uint32_t addr)
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return 0xFF;
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}
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void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
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void writememb386l(uint32_t addr, uint8_t val)
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{
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if (seg==-1)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! wb %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return;
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}
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mem_logical_addr = addr = addr + seg;
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mem_logical_addr = addr;
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if (page_lookup[addr>>12])
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{
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page_lookup[addr>>12]->write_b(addr, val, page_lookup[addr>>12]);
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@ -555,352 +541,308 @@ void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
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// else pclog("Bad writememb386l %08X %02X %04X:%08X\n", addr, val, CS, pc);
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}
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uint16_t readmemwl(uint32_t seg, uint32_t addr)
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uint16_t readmemwl(uint32_t addr)
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{
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uint32_t addr2 = mem_logical_addr = seg + addr;
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mem_logical_addr = addr;
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if (seg==-1)
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if (addr & 1)
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{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! rw %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return -1;
|
||||
}
|
||||
if (addr2 & 1)
|
||||
{
|
||||
if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
|
||||
if (!cpu_cyrix_alignment || (addr & 7) == 7)
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFFE)
|
||||
if ((addr & 0xFFF) > 0xFFE)
|
||||
{
|
||||
if (cr0 >> 31)
|
||||
{
|
||||
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffff;
|
||||
if (mmutranslate_read(addr2+1) == 0xffffffff) return 0xffff;
|
||||
if (mmutranslate_read(addr) == 0xffffffff) return 0xffff;
|
||||
if (mmutranslate_read(addr+1) == 0xffffffff) return 0xffff;
|
||||
}
|
||||
if (is386) return readmemb386l(seg,addr)|(readmemb386l(seg,addr+1)<<8);
|
||||
else return readmembl(seg+addr)|(readmembl(seg+addr+1)<<8);
|
||||
if (is386) return readmemb386l(addr)|(readmemb386l(addr+1)<<8);
|
||||
else return readmembl(addr)|(readmembl(addr+1)<<8);
|
||||
}
|
||||
else if (readlookup2[addr2 >> 12] != -1)
|
||||
return *(uint16_t *)(readlookup2[addr2 >> 12] + addr2);
|
||||
else if (readlookup2[addr >> 12] != -1)
|
||||
return *(uint16_t *)(readlookup2[addr >> 12] + addr);
|
||||
}
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_read(addr2);
|
||||
if (addr2==0xFFFFFFFF) return 0xFFFF;
|
||||
addr = mmutranslate_read(addr);
|
||||
if (addr==0xFFFFFFFF) return 0xFFFF;
|
||||
}
|
||||
|
||||
addr2 &= rammask;
|
||||
addr &= rammask;
|
||||
|
||||
if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]);
|
||||
if (_mem_read_w[addr >> 14]) return _mem_read_w[addr >> 14](addr, _mem_priv_r[addr >> 14]);
|
||||
|
||||
if (_mem_read_b[addr2 >> 14])
|
||||
{
|
||||
if (AT) return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[(addr2 + 1) >> 14](addr2 + 1, _mem_priv_r[addr2 >> 14]) << 8);
|
||||
else return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[(seg + ((addr + 1) & 0xffff)) >> 14](seg + ((addr + 1) & 0xffff), _mem_priv_r[addr2 >> 14]) << 8);
|
||||
}
|
||||
// pclog("Bad readmemwl %08X\n", addr2);
|
||||
if (_mem_read_b[addr >> 14])
|
||||
return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]) | (_mem_read_b[(addr + 1) >> 14](addr + 1, _mem_priv_r[addr >> 14]) << 8);
|
||||
|
||||
// pclog("Bad readmemwl %08X\n", addr);
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
|
||||
void writememwl(uint32_t addr, uint16_t val)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
if (addr & 1)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! ww %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return;
|
||||
}
|
||||
|
||||
if (addr2 & 1)
|
||||
{
|
||||
if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
|
||||
if (!cpu_cyrix_alignment || (addr & 7) == 7)
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFFE)
|
||||
if ((addr & 0xFFF) > 0xFFE)
|
||||
{
|
||||
if (cr0 >> 31)
|
||||
{
|
||||
if (mmutranslate_write(addr2) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr2+1) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr+1) == 0xffffffff) return;
|
||||
}
|
||||
if (is386)
|
||||
{
|
||||
writememb386l(seg,addr,val);
|
||||
writememb386l(seg,addr+1,val>>8);
|
||||
writememb386l(addr,val);
|
||||
writememb386l(addr+1,val>>8);
|
||||
}
|
||||
else
|
||||
{
|
||||
writemembl(seg+addr,val);
|
||||
writemembl(seg+addr+1,val>>8);
|
||||
writemembl(addr,val);
|
||||
writemembl(addr+1,val>>8);
|
||||
}
|
||||
return;
|
||||
}
|
||||
else if (writelookup2[addr2 >> 12] != -1)
|
||||
else if (writelookup2[addr >> 12] != -1)
|
||||
{
|
||||
*(uint16_t *)(writelookup2[addr2 >> 12] + addr2) = val;
|
||||
*(uint16_t *)(writelookup2[addr >> 12] + addr) = val;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (page_lookup[addr2>>12])
|
||||
if (page_lookup[addr>>12])
|
||||
{
|
||||
page_lookup[addr2>>12]->write_w(addr2, val, page_lookup[addr2>>12]);
|
||||
page_lookup[addr>>12]->write_w(addr, val, page_lookup[addr>>12]);
|
||||
return;
|
||||
}
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_write(addr2);
|
||||
if (addr2==0xFFFFFFFF) return;
|
||||
addr = mmutranslate_write(addr);
|
||||
if (addr==0xFFFFFFFF) return;
|
||||
}
|
||||
|
||||
addr2 &= rammask;
|
||||
addr &= rammask;
|
||||
|
||||
/* if (addr2 >= 0xa0000 && addr2 < 0xc0000)
|
||||
pclog("writememwl %08X %02X\n", addr2, val);*/
|
||||
|
||||
if (_mem_write_w[addr2 >> 14])
|
||||
if (_mem_write_w[addr >> 14])
|
||||
{
|
||||
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
|
||||
if (_mem_write_b[addr2 >> 14])
|
||||
if (_mem_write_b[addr >> 14])
|
||||
{
|
||||
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[(addr2 + 1) >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[(addr + 1) >> 14](addr + 1, val >> 8, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
// pclog("Bad writememwl %08X %04X\n", addr2, val);
|
||||
// pclog("Bad writememwl %08X %04X\n", addr, val);
|
||||
}
|
||||
|
||||
uint32_t readmemll(uint32_t seg, uint32_t addr)
|
||||
uint32_t readmemll(uint32_t addr)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
if (addr & 3)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (addr2 & 3)
|
||||
{
|
||||
if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
|
||||
if (!cpu_cyrix_alignment || (addr & 7) > 4)
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2&0xFFF)>0xFFC)
|
||||
if ((addr&0xFFF)>0xFFC)
|
||||
{
|
||||
if (cr0>>31)
|
||||
{
|
||||
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr2+3) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr+3) == 0xffffffff) return 0xffffffff;
|
||||
}
|
||||
return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
|
||||
return readmemwl(addr)|(readmemwl(addr+2)<<16);
|
||||
}
|
||||
else if (readlookup2[addr2 >> 12] != -1)
|
||||
return *(uint32_t *)(readlookup2[addr2 >> 12] + addr2);
|
||||
else if (readlookup2[addr >> 12] != -1)
|
||||
return *(uint32_t *)(readlookup2[addr >> 12] + addr);
|
||||
}
|
||||
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_read(addr2);
|
||||
if (addr2==0xFFFFFFFF) return 0xFFFFFFFF;
|
||||
addr = mmutranslate_read(addr);
|
||||
if (addr==0xFFFFFFFF) return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
addr2&=rammask;
|
||||
addr&=rammask;
|
||||
|
||||
if (_mem_read_l[addr2 >> 14]) return _mem_read_l[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]);
|
||||
if (_mem_read_l[addr >> 14]) return _mem_read_l[addr >> 14](addr, _mem_priv_r[addr >> 14]);
|
||||
|
||||
if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_w[addr2 >> 14](addr2 + 2, _mem_priv_r[addr2 >> 14]) << 16);
|
||||
if (_mem_read_w[addr >> 14]) return _mem_read_w[addr >> 14](addr, _mem_priv_r[addr >> 14]) | (_mem_read_w[addr >> 14](addr + 2, _mem_priv_r[addr >> 14]) << 16);
|
||||
|
||||
if (_mem_read_b[addr2 >> 14]) return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[addr2 >> 14](addr2 + 1, _mem_priv_r[addr2 >> 14]) << 8) | (_mem_read_b[addr2 >> 14](addr2 + 2, _mem_priv_r[addr2 >> 14]) << 16) | (_mem_read_b[addr2 >> 14](addr2 + 3, _mem_priv_r[addr2 >> 14]) << 24);
|
||||
if (_mem_read_b[addr >> 14]) return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]) | (_mem_read_b[addr >> 14](addr + 1, _mem_priv_r[addr >> 14]) << 8) | (_mem_read_b[addr >> 14](addr + 2, _mem_priv_r[addr >> 14]) << 16) | (_mem_read_b[addr >> 14](addr + 3, _mem_priv_r[addr >> 14]) << 24);
|
||||
|
||||
// pclog("Bad readmemll %08X\n", addr2);
|
||||
// pclog("Bad readmemll %08X\n", addr);
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
void writememll(uint32_t seg, uint32_t addr, uint32_t val)
|
||||
void writememll(uint32_t addr, uint32_t val)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
if (addr & 3)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return;
|
||||
}
|
||||
if (addr2 & 3)
|
||||
{
|
||||
if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
|
||||
if (!cpu_cyrix_alignment || (addr & 7) > 4)
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFFC)
|
||||
if ((addr & 0xFFF) > 0xFFC)
|
||||
{
|
||||
if (cr0>>31)
|
||||
{
|
||||
if (mmutranslate_write(addr2) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr2+3) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr+3) == 0xffffffff) return;
|
||||
}
|
||||
writememwl(seg,addr,val);
|
||||
writememwl(seg,addr+2,val>>16);
|
||||
writememwl(addr,val);
|
||||
writememwl(addr+2,val>>16);
|
||||
return;
|
||||
}
|
||||
else if (writelookup2[addr2 >> 12] != -1)
|
||||
else if (writelookup2[addr >> 12] != -1)
|
||||
{
|
||||
*(uint32_t *)(writelookup2[addr2 >> 12] + addr2) = val;
|
||||
*(uint32_t *)(writelookup2[addr >> 12] + addr) = val;
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (page_lookup[addr2>>12])
|
||||
if (page_lookup[addr>>12])
|
||||
{
|
||||
page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
|
||||
page_lookup[addr>>12]->write_l(addr, val, page_lookup[addr>>12]);
|
||||
return;
|
||||
}
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_write(addr2);
|
||||
if (addr2==0xFFFFFFFF) return;
|
||||
addr = mmutranslate_write(addr);
|
||||
if (addr==0xFFFFFFFF) return;
|
||||
}
|
||||
|
||||
addr2&=rammask;
|
||||
addr&=rammask;
|
||||
|
||||
/* if (addr >= 0xa0000 && addr < 0xc0000)
|
||||
pclog("writememll %08X %08X\n", addr, val);*/
|
||||
|
||||
if (_mem_write_l[addr2 >> 14])
|
||||
if (_mem_write_l[addr >> 14])
|
||||
{
|
||||
_mem_write_l[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_l[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
if (_mem_write_w[addr2 >> 14])
|
||||
if (_mem_write_w[addr >> 14])
|
||||
{
|
||||
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
if (_mem_write_b[addr2 >> 14])
|
||||
if (_mem_write_b[addr >> 14])
|
||||
{
|
||||
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 3, val >> 24, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 1, val >> 8, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 3, val >> 24, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
// pclog("Bad writememll %08X %08X\n", addr2, val);
|
||||
// pclog("Bad writememll %08X %08X\n", addr, val);
|
||||
}
|
||||
|
||||
uint64_t readmemql(uint32_t seg, uint32_t addr)
|
||||
uint64_t readmemql(uint32_t addr)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (addr2 & 7)
|
||||
if (addr & 7)
|
||||
{
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFF8)
|
||||
if ((addr & 0xFFF) > 0xFF8)
|
||||
{
|
||||
if (cr0>>31)
|
||||
{
|
||||
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr2+7) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr+7) == 0xffffffff) return 0xffffffff;
|
||||
}
|
||||
return readmemll(seg,addr)|((uint64_t)readmemll(seg,addr+4)<<32);
|
||||
return readmemll(addr)|((uint64_t)readmemll(addr+4)<<32);
|
||||
}
|
||||
else if (readlookup2[addr2 >> 12] != -1)
|
||||
return *(uint64_t *)(readlookup2[addr2 >> 12] + addr2);
|
||||
else if (readlookup2[addr >> 12] != -1)
|
||||
return *(uint64_t *)(readlookup2[addr >> 12] + addr);
|
||||
}
|
||||
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_read(addr2);
|
||||
if (addr2==0xFFFFFFFF) return 0xFFFFFFFF;
|
||||
addr = mmutranslate_read(addr);
|
||||
if (addr==0xFFFFFFFF) return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
addr2&=rammask;
|
||||
addr&=rammask;
|
||||
|
||||
if (_mem_read_l[addr2 >> 14])
|
||||
return _mem_read_l[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) |
|
||||
((uint64_t)_mem_read_l[addr2 >> 14](addr2 + 4, _mem_priv_r[addr2 >> 14]) << 32);
|
||||
if (_mem_read_l[addr >> 14])
|
||||
return _mem_read_l[addr >> 14](addr, _mem_priv_r[addr >> 14]) |
|
||||
((uint64_t)_mem_read_l[addr >> 14](addr + 4, _mem_priv_r[addr >> 14]) << 32);
|
||||
|
||||
return readmemll(seg,addr) | ((uint64_t)readmemll(seg,addr+4)<<32);
|
||||
return readmemll(addr) | ((uint64_t)readmemll(addr+4)<<32);
|
||||
}
|
||||
|
||||
void writememql(uint32_t seg, uint32_t addr, uint64_t val)
|
||||
void writememql(uint32_t addr, uint64_t val)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return;
|
||||
}
|
||||
if (addr2 & 7)
|
||||
if (addr & 7)
|
||||
{
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFF8)
|
||||
if ((addr & 0xFFF) > 0xFF8)
|
||||
{
|
||||
if (cr0>>31)
|
||||
{
|
||||
if (mmutranslate_write(addr2) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr2+7) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr+7) == 0xffffffff) return;
|
||||
}
|
||||
writememll(seg, addr, val);
|
||||
writememll(seg, addr+4, val >> 32);
|
||||
writememll(addr, val);
|
||||
writememll(addr+4, val >> 32);
|
||||
return;
|
||||
}
|
||||
else if (writelookup2[addr2 >> 12] != -1)
|
||||
else if (writelookup2[addr >> 12] != -1)
|
||||
{
|
||||
*(uint64_t *)(writelookup2[addr2 >> 12] + addr2) = val;
|
||||
*(uint64_t *)(writelookup2[addr >> 12] + addr) = val;
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (page_lookup[addr2>>12])
|
||||
if (page_lookup[addr>>12])
|
||||
{
|
||||
page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
|
||||
page_lookup[addr2>>12]->write_l(addr2 + 4, val >> 32, page_lookup[addr2>>12]);
|
||||
page_lookup[addr>>12]->write_l(addr, val, page_lookup[addr>>12]);
|
||||
page_lookup[addr>>12]->write_l(addr + 4, val >> 32, page_lookup[addr>>12]);
|
||||
return;
|
||||
}
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_write(addr2);
|
||||
if (addr2==0xFFFFFFFF) return;
|
||||
addr = mmutranslate_write(addr);
|
||||
if (addr==0xFFFFFFFF) return;
|
||||
}
|
||||
|
||||
addr2&=rammask;
|
||||
addr&=rammask;
|
||||
|
||||
if (_mem_write_l[addr2 >> 14])
|
||||
if (_mem_write_l[addr >> 14])
|
||||
{
|
||||
_mem_write_l[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_l[addr2 >> 14](addr2+4, val >> 32, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_l[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_l[addr >> 14](addr+4, val >> 32, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
if (_mem_write_w[addr2 >> 14])
|
||||
if (_mem_write_w[addr >> 14])
|
||||
{
|
||||
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 4, val >> 32, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 6, val >> 48, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 4, val >> 32, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 6, val >> 48, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
if (_mem_write_b[addr2 >> 14])
|
||||
if (_mem_write_b[addr >> 14])
|
||||
{
|
||||
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 3, val >> 24, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 4, val >> 32, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 5, val >> 40, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 6, val >> 48, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 7, val >> 56, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 1, val >> 8, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 3, val >> 24, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 4, val >> 32, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 5, val >> 40, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 6, val >> 48, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 7, val >> 56, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
// pclog("Bad writememql %08X %08X\n", addr2, val);
|
||||
// pclog("Bad writememql %08X %08X\n", addr, val);
|
||||
}
|
||||
|
||||
uint8_t mem_readb_phys(uint32_t addr)
|
||||
|
|
|
|||
|
|
@ -14,9 +14,11 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
|
||||
uint8_t dst; \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
dst = geteab(); if (cpu_state.abrt) return 1; \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
seteab(operation); if (cpu_state.abrt) return 1; \
|
||||
seteab(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 0); \
|
||||
|
|
@ -38,7 +40,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
|
||||
uint8_t dst; \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
dst = geteab(); if (cpu_state.abrt) return 1; \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
seteab(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
|
|
@ -63,7 +67,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
uint16_t dst; \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
seteaw(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
|
|
@ -87,7 +93,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
uint16_t dst; \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
seteaw(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
|
|
@ -112,7 +120,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
|
||||
uint32_t dst; \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
dst = geteal(); if (cpu_state.abrt) return 1; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
seteal(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
|
|
@ -136,7 +146,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
|
||||
uint32_t dst; \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
dst = geteal(); if (cpu_state.abrt) return 1; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
seteal(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
|
|
@ -151,6 +163,8 @@
|
|||
uint8_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
dst = getr8(cpu_reg); \
|
||||
src = geteab(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
|
|
@ -164,6 +178,8 @@
|
|||
uint8_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
dst = getr8(cpu_reg); \
|
||||
src = geteab(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
|
|
@ -178,6 +194,8 @@
|
|||
uint16_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
dst = cpu_state.regs[cpu_reg].w; \
|
||||
src = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
|
|
@ -191,6 +209,8 @@
|
|||
uint16_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
dst = cpu_state.regs[cpu_reg].w; \
|
||||
src = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
|
|
@ -205,6 +225,8 @@
|
|||
uint32_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
dst = cpu_state.regs[cpu_reg].l; \
|
||||
src = geteal(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
|
|
@ -218,6 +240,8 @@
|
|||
uint32_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
dst = cpu_state.regs[cpu_reg].l; \
|
||||
src = geteal(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
|
|
@ -275,6 +299,8 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(dst, getr8(cpu_reg));
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -286,6 +312,8 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(dst, getr8(cpu_reg));
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -298,6 +326,8 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(dst, cpu_state.regs[cpu_reg].w);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -309,6 +339,8 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(dst, cpu_state.regs[cpu_reg].w);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -321,6 +353,8 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(dst, cpu_state.regs[cpu_reg].l);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -332,6 +366,8 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(dst, cpu_state.regs[cpu_reg].l);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -344,7 +380,9 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteab(); if (cpu_state.abrt) return 1;
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(getr8(cpu_reg), src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
|
||||
|
|
@ -354,7 +392,9 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteab(); if (cpu_state.abrt) return 1;
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(getr8(cpu_reg), src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
|
||||
|
|
@ -365,7 +405,9 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(cpu_state.regs[cpu_reg].w, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
|
||||
|
|
@ -375,7 +417,9 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(cpu_state.regs[cpu_reg].w, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
|
||||
|
|
@ -386,7 +430,9 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
|
||||
|
|
@ -396,7 +442,9 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
|
||||
|
|
@ -434,6 +482,8 @@ static int opTEST_b_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
|
|
@ -446,6 +496,8 @@ static int opTEST_b_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
|
|
@ -459,6 +511,8 @@ static int opTEST_w_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
|
|
@ -471,6 +525,8 @@ static int opTEST_w_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
|
|
@ -484,6 +540,8 @@ static int opTEST_l_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
|
|
@ -496,6 +554,8 @@ static int opTEST_l_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
|
|
@ -588,6 +648,8 @@ static int op80_a16(uint32_t fetchdat)
|
|||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(b, 8);
|
||||
if ((rmdat & 0x38) == 0x38)
|
||||
|
|
@ -602,6 +664,8 @@ static int op80_a32(uint32_t fetchdat)
|
|||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(b, 8);
|
||||
if ((rmdat & 0x38) == 0x38)
|
||||
|
|
@ -616,6 +680,8 @@ static int op81_w_a16(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(w, 16);
|
||||
if ((rmdat & 0x38) == 0x38)
|
||||
|
|
@ -630,6 +696,8 @@ static int op81_w_a32(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(w, 16);
|
||||
if ((rmdat & 0x38) == 0x38)
|
||||
|
|
@ -644,6 +712,8 @@ static int op81_l_a16(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(l, 32);
|
||||
if ((rmdat & 0x38) == 0x38)
|
||||
|
|
@ -658,6 +728,8 @@ static int op81_l_a32(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(l, 32);
|
||||
if ((rmdat & 0x38) == 0x38)
|
||||
|
|
@ -673,6 +745,8 @@ static int op83_w_a16(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
|
@ -688,6 +762,8 @@ static int op83_w_a32(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
|
@ -704,6 +780,8 @@ static int op83_l_a16(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
|
@ -719,6 +797,8 @@ static int op83_l_a32(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
if (AL == temp) seteab(getr8(cpu_reg));
|
||||
else AL = temp;
|
||||
|
|
@ -26,6 +27,7 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
if (AL == temp) seteab(getr8(cpu_reg));
|
||||
else AL = temp;
|
||||
|
|
@ -45,6 +47,7 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
|
||||
else AX = temp;
|
||||
|
|
@ -63,6 +66,7 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
|
||||
else AX = temp;
|
||||
|
|
@ -82,6 +86,7 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
|
||||
else EAX = temp;
|
||||
|
|
@ -100,6 +105,7 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
|
||||
else EAX = temp;
|
||||
|
|
@ -119,6 +125,7 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
|
|||
return 0;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal();
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
if (EAX == temp && EDX == temp_hi)
|
||||
|
|
@ -150,6 +157,7 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
|
|||
return 0;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal();
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
if (EAX == temp && EDX == temp_hi)
|
||||
|
|
@ -182,6 +190,7 @@ static int opXADD_b_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setadd8(temp, getr8(cpu_reg));
|
||||
|
|
@ -199,6 +208,7 @@ static int opXADD_b_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setadd8(temp, getr8(cpu_reg));
|
||||
|
|
@ -217,6 +227,7 @@ static int opXADD_w_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[cpu_reg].w);
|
||||
|
|
@ -234,6 +245,7 @@ static int opXADD_w_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[cpu_reg].w);
|
||||
|
|
@ -252,6 +264,7 @@ static int opXADD_l_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[cpu_reg].l);
|
||||
|
|
@ -269,6 +282,7 @@ static int opXADD_l_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[cpu_reg].l);
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ static int opBT_w_r_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
|
|
@ -18,6 +19,7 @@ static int opBT_w_r_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
|
|
@ -33,6 +35,7 @@ static int opBT_l_r_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
|
|
@ -48,6 +51,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
|
|
@ -66,6 +70,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint16_t temp; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
|
|
@ -85,6 +91,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint16_t temp; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
|
|
@ -104,6 +112,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint32_t temp; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
|
|
@ -123,6 +133,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint32_t temp; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
|
|
@ -147,7 +159,9 @@ static int opBA_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
temp = geteaw();
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
|
|
@ -189,7 +203,9 @@ static int opBA_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
temp = geteaw();
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
|
|
@ -232,7 +248,9 @@ static int opBA_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
temp = geteal();
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
|
|
@ -274,7 +292,9 @@ static int opBA_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
temp = geteal();
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@ static int opBSF_w_a16(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
|
||||
|
|
@ -40,6 +42,8 @@ static int opBSF_w_a32(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
|
||||
|
|
@ -55,6 +59,8 @@ static int opBSF_l_a16(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
|
||||
|
|
@ -70,6 +76,8 @@ static int opBSF_l_a32(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
|
||||
|
|
@ -86,6 +94,8 @@ static int opBSR_w_a16(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
|
||||
|
|
@ -101,6 +111,8 @@ static int opBSR_w_a32(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
|
||||
|
|
@ -116,6 +128,8 @@ static int opBSR_l_a16(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
|
||||
|
|
@ -131,6 +145,8 @@ static int opBSR_l_a32(uint32_t fetchdat)
|
|||
int instr_cycles;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd16nc(temp, 1);
|
||||
|
|
@ -111,6 +113,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
||||
break;
|
||||
case 0x08: /*DEC w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub16nc(temp, 1);
|
||||
|
|
@ -118,6 +122,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(cpu_state.pc);
|
||||
cpu_state.pc = new_pc;
|
||||
|
|
@ -128,6 +134,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -137,6 +145,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -146,6 +156,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -156,6 +168,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x30: /*PUSH w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -181,6 +195,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd16nc(temp, 1);
|
||||
|
|
@ -188,6 +204,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
||||
break;
|
||||
case 0x08: /*DEC w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub16nc(temp, 1);
|
||||
|
|
@ -195,6 +213,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(cpu_state.pc);
|
||||
cpu_state.pc = new_pc;
|
||||
|
|
@ -205,6 +225,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -214,6 +236,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -223,6 +247,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -233,6 +259,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x30: /*PUSH w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -259,6 +287,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd32nc(temp, 1);
|
||||
|
|
@ -266,6 +296,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
|
||||
break;
|
||||
case 0x08: /*DEC l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub32nc(temp, 1);
|
||||
|
|
@ -273,6 +305,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(cpu_state.pc);
|
||||
cpu_state.pc = new_pc;
|
||||
|
|
@ -283,6 +317,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -292,6 +328,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -301,6 +339,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -311,6 +351,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x30: /*PUSH l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -336,6 +378,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd32nc(temp, 1);
|
||||
|
|
@ -343,6 +387,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
|
||||
break;
|
||||
case 0x08: /*DEC l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub32nc(temp, 1);
|
||||
|
|
@ -350,6 +396,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(cpu_state.pc); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
|
|
@ -360,6 +408,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -369,6 +419,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -378,6 +430,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -388,6 +442,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_FLUSH();
|
||||
break;
|
||||
case 0x30: /*PUSH l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(temp);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 1);
|
||||
|
|
|
|||
|
|
@ -50,6 +50,8 @@ static int opINCDEC_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp=geteab(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (rmdat&0x38)
|
||||
|
|
@ -71,6 +73,8 @@ static int opINCDEC_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp=geteab(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (rmdat&0x38)
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@ static int opF6_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
{
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
}
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -68,11 +69,15 @@ static int opF6_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
|
||||
break;
|
||||
case 0x10: /*NOT b*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteab(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
||||
break;
|
||||
case 0x18: /*NEG b*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteab(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub8(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
|
|
@ -156,6 +161,8 @@ static int opF6_a32(uint32_t fetchdat)
|
|||
int8_t temps;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
|
|
@ -168,11 +175,15 @@ static int opF6_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
|
||||
break;
|
||||
case 0x10: /*NOT b*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteab(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
||||
break;
|
||||
case 0x18: /*NEG b*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteab(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub8(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
|
|
@ -259,6 +270,8 @@ static int opF7_w_a16(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
|
|
@ -271,11 +284,15 @@ static int opF7_w_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
|
||||
break;
|
||||
case 0x10: /*NOT w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
||||
break;
|
||||
case 0x18: /*NEG w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub16(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
|
|
@ -353,6 +370,8 @@ static int opF7_w_a32(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
|
|
@ -365,11 +384,15 @@ static int opF7_w_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
|
||||
break;
|
||||
case 0x10: /*NOT w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
||||
break;
|
||||
case 0x18: /*NEG w*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub16(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
|
|
@ -446,6 +469,8 @@ static int opF7_l_a16(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -459,11 +484,15 @@ static int opF7_l_a16(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 5, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
|
||||
break;
|
||||
case 0x10: /*NOT l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteal(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
|
||||
break;
|
||||
case 0x18: /*NEG l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteal(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub32(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
|
|
@ -516,6 +545,8 @@ static int opF7_l_a32(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -529,11 +560,15 @@ static int opF7_l_a32(uint32_t fetchdat)
|
|||
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 5, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
|
||||
break;
|
||||
case 0x10: /*NOT l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteal(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
|
||||
break;
|
||||
case 0x18: /*NEG l*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteal(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub32(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
|
|
@ -625,6 +660,7 @@ static int opBOUND_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -644,6 +680,7 @@ static int opBOUND_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -664,6 +701,7 @@ static int opBOUND_l_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -683,6 +721,7 @@ static int opBOUND_l_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
src.q = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1; \
|
||||
CLOCK_CYCLES(2); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -293,7 +293,8 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
MMX_REG src;
|
||||
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
cpu_state.MM[cpu_reg].w[0] *= src.w[0];
|
||||
|
|
@ -321,6 +322,7 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
|||
{
|
||||
MMX_REG src;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
cpu_state.MM[cpu_reg].w[0] *= src.w[0];
|
||||
|
|
@ -349,6 +351,7 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
|||
{
|
||||
MMX_REG src;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
|
|
@ -376,6 +379,7 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
|||
{
|
||||
MMX_REG src;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
|
|
|
|||
|
|
@ -12,7 +12,8 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint32_t dst;
|
||||
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
cpu_state.MM[cpu_reg].l[0] = dst;
|
||||
cpu_state.MM[cpu_reg].l[1] = 0;
|
||||
|
|
@ -35,7 +36,8 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint32_t dst;
|
||||
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
cpu_state.MM[cpu_reg].l[0] = dst;
|
||||
cpu_state.MM[cpu_reg].l[1] = 0;
|
||||
|
|
@ -57,6 +59,7 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
@ -75,6 +78,7 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
@ -96,6 +100,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint64_t dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
cpu_state.MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
@ -116,6 +121,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint64_t dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
cpu_state.MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
@ -135,6 +141,7 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].q); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
@ -153,6 +160,7 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].q); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0;
|
||||
cpu_state.MM[cpu_reg].l[1] = src;
|
||||
|
||||
|
|
@ -32,7 +33,8 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint32_t src;
|
||||
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0;
|
||||
cpu_state.MM[cpu_reg].l[1] = src;
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
shift = readmemb(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0; \
|
||||
CLOCK_CYCLES(2); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -182,6 +182,7 @@ static int opMOV_b_imm_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON((rmdat & 0x38) != 0);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = readmemb(cs,cpu_state.pc); cpu_state.pc++; if (cpu_state.abrt) return 1;
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(temp);
|
||||
|
|
@ -194,6 +195,7 @@ static int opMOV_b_imm_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON((rmdat & 0x38) != 0);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = getbyte(); if (cpu_state.abrt) return 1;
|
||||
seteab(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
|
|
@ -206,6 +208,7 @@ static int opMOV_w_imm_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON((rmdat & 0x38) != 0);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = getword(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
|
|
@ -217,6 +220,7 @@ static int opMOV_w_imm_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON((rmdat & 0x38) != 0);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = getword(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
|
|
@ -228,6 +232,7 @@ static int opMOV_l_imm_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON((rmdat & 0x38) != 0);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = getlong(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
|
|
@ -239,6 +244,7 @@ static int opMOV_l_imm_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON((rmdat & 0x38) != 0);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = getlong(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
|
|
@ -251,6 +257,7 @@ static int opMOV_AL_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint8_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, addr, addr);
|
||||
temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
|
|
@ -262,6 +269,7 @@ static int opMOV_AL_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t addr = getlong();
|
||||
uint8_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, addr, addr);
|
||||
temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
|
|
@ -273,6 +281,7 @@ static int opMOV_AX_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint16_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, addr, addr+1);
|
||||
temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
|
|
@ -284,6 +293,7 @@ static int opMOV_AX_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t addr = getlong();
|
||||
uint16_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, addr, addr+1);
|
||||
temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
|
|
@ -295,6 +305,7 @@ static int opMOV_EAX_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint32_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, addr, addr+3);
|
||||
temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
|
|
@ -306,6 +317,7 @@ static int opMOV_EAX_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t addr = getlong();
|
||||
uint32_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, addr, addr+3);
|
||||
temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
|
|
@ -317,6 +329,7 @@ static int opMOV_EAX_a32(uint32_t fetchdat)
|
|||
static int opMOV_a16_AL(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
writememb(cpu_state.ea_seg->base, addr, AL);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
|
||||
|
|
@ -325,6 +338,7 @@ static int opMOV_a16_AL(uint32_t fetchdat)
|
|||
static int opMOV_a32_AL(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
writememb(cpu_state.ea_seg->base, addr, AL);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
PREFETCH_RUN(2, 5, -1, 0,0,1,0, 1);
|
||||
|
|
@ -333,6 +347,7 @@ static int opMOV_a32_AL(uint32_t fetchdat)
|
|||
static int opMOV_a16_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
writememw(cpu_state.ea_seg->base, addr, AX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
|
||||
|
|
@ -341,6 +356,7 @@ static int opMOV_a16_AX(uint32_t fetchdat)
|
|||
static int opMOV_a32_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
writememw(cpu_state.ea_seg->base, addr, AX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
PREFETCH_RUN(2, 5, -1, 0,0,1,0, 1);
|
||||
|
|
@ -349,6 +365,7 @@ static int opMOV_a32_AX(uint32_t fetchdat)
|
|||
static int opMOV_a16_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
writememl(cpu_state.ea_seg->base, addr, EAX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
PREFETCH_RUN(2, 3, -1, 0,0,0,1, 0);
|
||||
|
|
@ -357,6 +374,7 @@ static int opMOV_a16_EAX(uint32_t fetchdat)
|
|||
static int opMOV_a32_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
writememl(cpu_state.ea_seg->base, addr, EAX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
PREFETCH_RUN(2, 5, -1, 0,0,0,1, 1);
|
||||
|
|
@ -407,7 +425,10 @@ static int opLEA_l_a32(uint32_t fetchdat)
|
|||
static int opXLAT_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = (BX + AL)&0xFFFF;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
|
||||
|
|
@ -416,7 +437,10 @@ static int opXLAT_a16(uint32_t fetchdat)
|
|||
static int opXLAT_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = EBX + AL;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
|
||||
|
|
@ -434,6 +458,7 @@ static int opMOV_b_r_a16(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
|
|
@ -452,6 +477,7 @@ static int opMOV_b_r_a32(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
|
|
@ -470,6 +496,7 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
|
|
@ -488,6 +515,7 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
|
|
@ -506,6 +534,7 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
|
|
@ -524,6 +553,7 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
|
|||
}
|
||||
else
|
||||
{
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
|
|
@ -544,6 +574,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint8_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
|
|
@ -564,6 +595,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint8_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
|
|
@ -584,6 +616,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint16_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
|
@ -604,6 +637,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint16_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
|
@ -624,6 +658,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint32_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
|
|
@ -644,6 +679,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
uint32_t temp;
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
|
|
@ -664,6 +700,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
else \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1); \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
|
|
@ -682,6 +719,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
else \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1); \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
|
|
@ -700,6 +738,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
else \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3); \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
|
|
@ -719,6 +758,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
static int opMOV_w_seg_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ES*/
|
||||
|
|
@ -31,7 +33,9 @@ static int opMOV_w_seg_a16(uint32_t fetchdat)
|
|||
static int opMOV_w_seg_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ES*/
|
||||
|
|
@ -62,7 +66,9 @@ static int opMOV_w_seg_a32(uint32_t fetchdat)
|
|||
static int opMOV_l_seg_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ES*/
|
||||
|
|
@ -98,7 +104,9 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
|
|||
static int opMOV_l_seg_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ES*/
|
||||
|
|
@ -137,7 +145,8 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
|
|||
uint16_t new_seg;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_seg=geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -177,7 +186,8 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
|
|||
uint16_t new_seg;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
new_seg=geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -220,6 +230,7 @@ static int opLDS_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -235,6 +246,7 @@ static int opLDS_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -251,6 +263,7 @@ static int opLDS_l_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -267,6 +280,7 @@ static int opLDS_l_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -283,6 +297,7 @@ static int opLSS_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -298,6 +313,7 @@ static int opLSS_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -314,6 +330,7 @@ static int opLSS_l_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -330,6 +347,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -346,6 +364,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t addr, seg; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1; \
|
||||
|
|
@ -362,6 +381,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t addr, seg; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1; \
|
||||
|
|
@ -379,6 +399,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t seg; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1; \
|
||||
|
|
@ -396,6 +417,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t seg; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1; \
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@ static int opMOVZX_w_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
|
||||
|
|
@ -15,6 +17,8 @@ static int opMOVZX_w_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
|
||||
|
|
@ -27,6 +31,8 @@ static int opMOVZX_l_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
|
|
@ -39,6 +45,8 @@ static int opMOVZX_l_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
|
|
@ -51,6 +59,8 @@ static int opMOVZX_w_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
||||
|
|
@ -63,6 +73,8 @@ static int opMOVZX_w_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
||||
|
|
@ -75,6 +87,8 @@ static int opMOVZX_l_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
|
|
@ -87,6 +101,8 @@ static int opMOVZX_l_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
|
|
@ -100,6 +116,8 @@ static int opMOVSX_w_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
if (temp & 0x80)
|
||||
|
|
@ -114,6 +132,8 @@ static int opMOVSX_w_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
if (temp & 0x80)
|
||||
|
|
@ -128,6 +148,8 @@ static int opMOVSX_l_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x80)
|
||||
|
|
@ -142,6 +164,8 @@ static int opMOVSX_l_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x80)
|
||||
|
|
@ -156,6 +180,8 @@ static int opMOVSX_l_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x8000)
|
||||
|
|
@ -170,6 +196,8 @@ static int opMOVSX_l_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x8000)
|
||||
|
|
|
|||
|
|
@ -4,7 +4,9 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
|
|||
int16_t tempw, tempw2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getword(); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -24,7 +26,9 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
|
|||
int16_t tempw, tempw2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getword(); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -45,7 +49,9 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
|
|||
int32_t templ, templ2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getlong(); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -65,7 +71,9 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
|
|||
int32_t templ, templ2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getlong(); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -86,7 +94,9 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
|
|||
int16_t tempw, tempw2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (tempw2 & 0x80) tempw2 |= 0xff00;
|
||||
|
|
@ -107,7 +117,9 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
|
|||
int16_t tempw, tempw2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (tempw2 & 0x80) tempw2 |= 0xff00;
|
||||
|
|
@ -129,6 +141,9 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
|
|||
int32_t templ, templ2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (templ2 & 0x80) templ2 |= 0xffffff00;
|
||||
|
|
@ -149,6 +164,9 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
|
|||
int32_t templ, templ2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (templ2 & 0x80) templ2 |= 0xffffff00;
|
||||
|
|
@ -171,6 +189,9 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
|
|||
int32_t templ;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[cpu_reg].w * (int32_t)(int16_t)geteaw();
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
|
||||
|
|
@ -187,6 +208,9 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
|
|||
int32_t templ;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[cpu_reg].w * (int32_t)(int16_t)geteaw();
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
|
||||
|
|
@ -204,6 +228,9 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[cpu_reg].l * (int64_t)(int32_t)geteal();
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
|
||||
|
|
@ -220,6 +247,9 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[cpu_reg].l * (int64_t)(int32_t)geteal();
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@ static int opARPL_a16(uint32_t fetchdat)
|
|||
|
||||
NOTRM
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
pclog("ARPL_a16\n");
|
||||
temp_seg = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
|
|
@ -27,7 +29,9 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
|
||||
NOTRM
|
||||
fetch_ea_32(fetchdat);
|
||||
pclog("ARPL_a32\n");
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
pclog("ARPL_a32\n");
|
||||
temp_seg = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
flags_rebuild();
|
||||
|
|
@ -53,6 +57,8 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
\
|
||||
NOTRM \
|
||||
fetch_ea(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
\
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
|
|
@ -103,6 +109,8 @@ opLAR(l_a32, fetch_ea_32, 1, 1)
|
|||
\
|
||||
NOTRM \
|
||||
fetch_ea(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
\
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
|
|
@ -163,11 +171,15 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*SLDT*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(ldt.seg);
|
||||
CLOCK_CYCLES(4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
|
||||
break;
|
||||
case 0x08: /*STR*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(tr.seg);
|
||||
CLOCK_CYCLES(4);
|
||||
PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
|
||||
|
|
@ -179,6 +191,8 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
|
|||
x86gpf(NULL,0);
|
||||
return 1;
|
||||
}
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
addr = (sel & ~7) + gdt.base;
|
||||
limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
|
||||
|
|
@ -205,6 +219,8 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
|
|||
x86gpf(NULL,0);
|
||||
break;
|
||||
}
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
addr = (sel & ~7) + gdt.base;
|
||||
limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
|
||||
|
|
@ -228,6 +244,8 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
|
|||
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 0:1,2,0,0, ea32);
|
||||
break;
|
||||
case 0x20: /*VERR*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
flags &= ~Z_FLAG;
|
||||
|
|
@ -248,6 +266,8 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
|
|||
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
|
||||
break;
|
||||
case 0x28: /*VERW*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
flags &= ~Z_FLAG;
|
||||
|
|
@ -300,6 +320,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*SGDT*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(gdt.limit);
|
||||
base = gdt.base; //is32 ? gdt.base : (gdt.base & 0xffffff);
|
||||
if (is286)
|
||||
|
|
@ -309,6 +331,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
PREFETCH_RUN(7, 2, rmdat, 0,0,1,1, ea32);
|
||||
break;
|
||||
case 0x08: /*SIDT*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(idt.limit);
|
||||
base = idt.base;
|
||||
if (is286)
|
||||
|
|
@ -324,6 +348,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
x86gpf(NULL,0);
|
||||
break;
|
||||
}
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
// pclog("LGDT %08X:%08X\n", easeg, eaaddr);
|
||||
limit = geteaw();
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -341,6 +367,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
x86gpf(NULL,0);
|
||||
break;
|
||||
}
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
// pclog("LIDT %08X:%08X\n", easeg, eaaddr);
|
||||
limit = geteaw();
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -353,6 +381,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
break;
|
||||
|
||||
case 0x20: /*SMSW*/
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (is486) seteaw(msw);
|
||||
else if (is386) seteaw(msw | 0xFF00);
|
||||
else seteaw(msw | 0xFFF0);
|
||||
|
|
@ -366,6 +396,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
x86gpf(NULL, 0);
|
||||
break;
|
||||
}
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (msw & 1) tempw |= 1;
|
||||
if (is386)
|
||||
|
|
@ -391,6 +423,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
|
|||
x86gpf(NULL, 0);
|
||||
break;
|
||||
}
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
mmu_invalidate(ds + cpu_state.eaaddr);
|
||||
CLOCK_CYCLES(12);
|
||||
PREFETCH_RUN(12, 2, rmdat, 0,0,0,0, ea32);
|
||||
|
|
|
|||
|
|
@ -9,7 +9,8 @@ static int opREP_INSB_ ## size(uint32_t fetchdat)
|
|||
{ \
|
||||
uint8_t temp; \
|
||||
\
|
||||
check_io_perm(DX); \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
check_io_perm(DX); \
|
||||
temp = inb(DX); \
|
||||
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
|
|
@ -36,6 +37,7 @@ static int opREP_INSW_ ## size(uint32_t fetchdat)
|
|||
{ \
|
||||
uint16_t temp; \
|
||||
\
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
temp = inw(DX); \
|
||||
|
|
@ -64,6 +66,7 @@ static int opREP_INSL_ ## size(uint32_t fetchdat)
|
|||
{ \
|
||||
uint32_t temp; \
|
||||
\
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
check_io_perm(DX+2); \
|
||||
|
|
@ -93,7 +96,9 @@ static int opREP_OUTSB_ ## size(uint32_t fetchdat)
|
|||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
uint8_t temp; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
check_io_perm(DX); \
|
||||
outb(DX, temp); \
|
||||
if (flags & D_FLAG) SRC_REG--; \
|
||||
|
|
@ -117,7 +122,9 @@ static int opREP_OUTSW_ ## size(uint32_t fetchdat)
|
|||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
uint16_t temp; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
outw(DX, temp); \
|
||||
|
|
@ -142,7 +149,9 @@ static int opREP_OUTSL_ ## size(uint32_t fetchdat)
|
|||
\
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
uint32_t temp; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
check_io_perm(DX); \
|
||||
check_io_perm(DX+1); \
|
||||
check_io_perm(DX+2); \
|
||||
|
|
@ -170,6 +179,11 @@ static int opREP_MOVSB_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
} \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
uint8_t temp; \
|
||||
|
|
@ -203,6 +217,11 @@ static int opREP_MOVSW_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
} \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
|
|
@ -236,6 +255,11 @@ static int opREP_MOVSL_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
{ \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
} \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
|
|
@ -271,6 +295,8 @@ static int opREP_STOSB_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
|
||||
|
|
@ -299,6 +325,8 @@ static int opREP_STOSW_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG+1); \
|
||||
|
|
@ -327,6 +355,8 @@ static int opREP_STOSL_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
SEG_CHECK_WRITE(&_es); \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG+3); \
|
||||
|
|
@ -356,6 +386,8 @@ static int opREP_LODSB_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
AL = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
|
|
@ -383,6 +415,8 @@ static int opREP_LODSW_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
|
|
@ -410,6 +444,8 @@ static int opREP_LODSL_ ## size(uint32_t fetchdat)
|
|||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
|
||||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
if (CNT_REG > 0) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
while (CNT_REG > 0) \
|
||||
{ \
|
||||
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
|
||||
|
|
@ -441,8 +477,11 @@ static int opREP_CMPSB_ ## size(uint32_t fetchdat)
|
|||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
|
||||
uint8_t temp2 = readmemb(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
uint8_t temp, temp2; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
SEG_CHECK_READ(&_es); \
|
||||
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
|
||||
temp2 = readmemb(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
|
||||
else { DEST_REG++; SRC_REG++; } \
|
||||
|
|
@ -468,8 +507,11 @@ static int opREP_CMPSW_ ## size(uint32_t fetchdat)
|
|||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
|
||||
uint16_t temp2 = readmemw(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
uint16_t temp, temp2; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
SEG_CHECK_READ(&_es); \
|
||||
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
|
||||
temp2 = readmemw(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
|
||||
else { DEST_REG += 2; SRC_REG += 2; } \
|
||||
|
|
@ -495,8 +537,11 @@ static int opREP_CMPSL_ ## size(uint32_t fetchdat)
|
|||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
|
||||
uint32_t temp2 = readmeml(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
uint32_t temp, temp2; \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
SEG_CHECK_READ(&_es); \
|
||||
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
|
||||
temp2 = readmeml(es, DEST_REG); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
|
||||
else { DEST_REG += 4; SRC_REG += 4; } \
|
||||
|
|
@ -523,6 +568,8 @@ static int opREP_SCASB_ ## size(uint32_t fetchdat)
|
|||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
SEG_CHECK_READ(&_es); \
|
||||
while ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint8_t temp = readmemb(es, DEST_REG); if (cpu_state.abrt) break;\
|
||||
|
|
@ -554,6 +601,8 @@ static int opREP_SCASW_ ## size(uint32_t fetchdat)
|
|||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
SEG_CHECK_READ(&_es); \
|
||||
while ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
|
||||
|
|
@ -585,6 +634,8 @@ static int opREP_SCASL_ ## size(uint32_t fetchdat)
|
|||
if (trap) \
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
|
||||
tempz = FV; \
|
||||
if ((CNT_REG > 0) && (FV == tempz)) \
|
||||
SEG_CHECK_READ(&_es); \
|
||||
while ((CNT_REG > 0) && (FV == tempz)) \
|
||||
{ \
|
||||
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
static int opSET ## condition ## _a16(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
seteab((cond_ ## condition) ? 1 : 0); \
|
||||
CLOCK_CYCLES(4); \
|
||||
return cpu_state.abrt; \
|
||||
|
|
@ -10,6 +12,8 @@
|
|||
static int opSET ## condition ## _a32(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
seteab((cond_ ## condition) ? 1 : 0); \
|
||||
CLOCK_CYCLES(4); \
|
||||
return cpu_state.abrt; \
|
||||
|
|
|
|||
|
|
@ -281,6 +281,8 @@ static int opC0_a16(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
PREFETCH_PREFIX();
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -294,6 +296,8 @@ static int opC0_a32(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
PREFETCH_PREFIX();
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -307,6 +311,8 @@ static int opC1_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
PREFETCH_PREFIX();
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -320,6 +326,8 @@ static int opC1_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
PREFETCH_PREFIX();
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -333,6 +341,8 @@ static int opC1_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
PREFETCH_PREFIX();
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -346,6 +356,8 @@ static int opC1_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
PREFETCH_PREFIX();
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -360,6 +372,8 @@ static int opD0_a16(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c, 0);
|
||||
return 0;
|
||||
|
|
@ -371,6 +385,8 @@ static int opD0_a32(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c, 1);
|
||||
return 0;
|
||||
|
|
@ -382,6 +398,8 @@ static int opD1_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c, 0);
|
||||
return 0;
|
||||
|
|
@ -393,6 +411,8 @@ static int opD1_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c, 1);
|
||||
return 0;
|
||||
|
|
@ -404,6 +424,8 @@ static int opD1_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c, 0);
|
||||
return 0;
|
||||
|
|
@ -415,6 +437,8 @@ static int opD1_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c, 1);
|
||||
return 0;
|
||||
|
|
@ -427,6 +451,8 @@ static int opD2_a16(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = CL & 31;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c, 0);
|
||||
|
|
@ -439,6 +465,8 @@ static int opD2_a32(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = CL & 31;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c, 1);
|
||||
|
|
@ -451,6 +479,8 @@ static int opD3_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = CL & 31;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c, 0);
|
||||
|
|
@ -463,6 +493,8 @@ static int opD3_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = CL & 31;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c, 1);
|
||||
|
|
@ -475,6 +507,8 @@ static int opD3_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = CL & 31;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c, 0);
|
||||
|
|
@ -487,6 +521,8 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
c = CL & 31;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c, 1);
|
||||
|
|
@ -552,6 +588,8 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
int count; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
count = getbyte() & 31; \
|
||||
operation(); \
|
||||
\
|
||||
|
|
@ -564,6 +602,8 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
int count; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
count = CL & 31; \
|
||||
operation(); \
|
||||
\
|
||||
|
|
@ -576,6 +616,8 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
int count; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
count = getbyte() & 31; \
|
||||
operation(); \
|
||||
\
|
||||
|
|
@ -588,6 +630,8 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
int count; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (cpu_mod != 3) \
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg); \
|
||||
count = CL & 31; \
|
||||
operation(); \
|
||||
\
|
||||
|
|
|
|||
|
|
@ -236,6 +236,8 @@ static int opPOPW_a16(uint32_t fetchdat)
|
|||
temp = POP_W(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(temp);
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
|
|
@ -255,6 +257,8 @@ static int opPOPW_a32(uint32_t fetchdat)
|
|||
temp = POP_W(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteaw(temp);
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
|
|
@ -275,6 +279,8 @@ static int opPOPL_a16(uint32_t fetchdat)
|
|||
temp = POP_L(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteal(temp);
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
|
|
@ -294,6 +300,8 @@ static int opPOPL_a32(uint32_t fetchdat)
|
|||
temp = POP_L(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
seteal(temp);
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,6 +1,10 @@
|
|||
static int opMOVSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
|
|
@ -10,7 +14,11 @@ static int opMOVSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opMOVSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
|
|
@ -21,7 +29,11 @@ static int opMOVSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opMOVSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
|
||||
else { DI += 2; SI += 2; }
|
||||
|
|
@ -31,7 +43,11 @@ static int opMOVSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opMOVSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
|
||||
else { EDI += 2; ESI += 2; }
|
||||
|
|
@ -42,7 +58,11 @@ static int opMOVSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opMOVSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
|
||||
else { DI += 4; SI += 4; }
|
||||
|
|
@ -52,7 +72,11 @@ static int opMOVSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opMOVSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
|
||||
else { EDI += 4; ESI += 4; }
|
||||
|
|
@ -64,8 +88,12 @@ static int opMOVSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opCMPSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src = readmemb(cpu_state.ea_seg->base, SI);
|
||||
uint8_t dst = readmemb(es, DI); if (cpu_state.abrt) return 1;
|
||||
uint8_t src, dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_READ(&_es);
|
||||
src = readmemb(cpu_state.ea_seg->base, SI);
|
||||
dst = readmemb(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub8(src, dst);
|
||||
if (flags & D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
|
|
@ -75,8 +103,12 @@ static int opCMPSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opCMPSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
uint8_t dst = readmemb(es, EDI); if (cpu_state.abrt) return 1;
|
||||
uint8_t src, dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_READ(&_es);
|
||||
src = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
dst = readmemb(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub8(src, dst);
|
||||
if (flags & D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
|
|
@ -87,8 +119,12 @@ static int opCMPSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opCMPSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src = readmemw(cpu_state.ea_seg->base, SI);
|
||||
uint16_t dst = readmemw(es, DI); if (cpu_state.abrt) return 1;
|
||||
uint16_t src, dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_READ(&_es);
|
||||
src = readmemw(cpu_state.ea_seg->base, SI);
|
||||
dst = readmemw(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub16(src, dst);
|
||||
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
|
||||
else { DI += 2; SI += 2; }
|
||||
|
|
@ -98,8 +134,12 @@ static int opCMPSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opCMPSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
uint16_t dst = readmemw(es, EDI); if (cpu_state.abrt) return 1;
|
||||
uint16_t src, dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_READ(&_es);
|
||||
src = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
dst = readmemw(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub16(src, dst);
|
||||
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
|
||||
else { EDI += 2; ESI += 2; }
|
||||
|
|
@ -110,8 +150,12 @@ static int opCMPSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opCMPSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = readmeml(cpu_state.ea_seg->base, SI);
|
||||
uint32_t dst = readmeml(es, DI); if (cpu_state.abrt) return 1;
|
||||
uint32_t src, dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_READ(&_es);
|
||||
src = readmeml(cpu_state.ea_seg->base, SI);
|
||||
dst = readmeml(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub32(src, dst);
|
||||
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
|
||||
else { DI += 4; SI += 4; }
|
||||
|
|
@ -121,8 +165,12 @@ static int opCMPSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opCMPSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
uint32_t dst = readmeml(es, EDI); if (cpu_state.abrt) return 1;
|
||||
uint32_t src, dst;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
SEG_CHECK_READ(&_es);
|
||||
src = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
dst = readmeml(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub32(src, dst);
|
||||
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
|
||||
else { EDI += 4; ESI += 4; }
|
||||
|
|
@ -133,6 +181,7 @@ static int opCMPSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSTOSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
writememb(es, DI, AL); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI--;
|
||||
else DI++;
|
||||
|
|
@ -142,6 +191,7 @@ static int opSTOSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSTOSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
writememb(es, EDI, AL); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
|
|
@ -152,6 +202,7 @@ static int opSTOSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSTOSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
writememw(es, DI, AX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI -= 2;
|
||||
else DI += 2;
|
||||
|
|
@ -161,6 +212,7 @@ static int opSTOSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSTOSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
writememw(es, EDI, AX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI -= 2;
|
||||
else EDI += 2;
|
||||
|
|
@ -171,6 +223,7 @@ static int opSTOSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSTOSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
writememl(es, DI, EAX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI -= 4;
|
||||
else DI += 4;
|
||||
|
|
@ -180,6 +233,7 @@ static int opSTOSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSTOSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
writememl(es, EDI, EAX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI -= 4;
|
||||
else EDI += 4;
|
||||
|
|
@ -191,7 +245,10 @@ static int opSTOSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opLODSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
if (flags & D_FLAG) SI--;
|
||||
else SI++;
|
||||
|
|
@ -201,7 +258,10 @@ static int opLODSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opLODSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
if (flags & D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
|
|
@ -212,7 +272,10 @@ static int opLODSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opLODSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
if (flags & D_FLAG) SI -= 2;
|
||||
else SI += 2;
|
||||
|
|
@ -222,7 +285,10 @@ static int opLODSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opLODSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
if (flags & D_FLAG) ESI -= 2;
|
||||
else ESI += 2;
|
||||
|
|
@ -233,7 +299,10 @@ static int opLODSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opLODSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
if (flags & D_FLAG) SI -= 4;
|
||||
else SI += 4;
|
||||
|
|
@ -243,7 +312,10 @@ static int opLODSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opLODSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
if (flags & D_FLAG) ESI -= 4;
|
||||
else ESI += 4;
|
||||
|
|
@ -255,7 +327,10 @@ static int opLODSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSCASB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(es, DI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(&_es);
|
||||
temp = readmemb(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub8(AL, temp);
|
||||
if (flags & D_FLAG) DI--;
|
||||
else DI++;
|
||||
|
|
@ -265,7 +340,10 @@ static int opSCASB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSCASB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(es, EDI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(&_es);
|
||||
temp = readmemb(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub8(AL, temp);
|
||||
if (flags & D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
|
|
@ -276,7 +354,10 @@ static int opSCASB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSCASW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(es, DI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(&_es);
|
||||
temp = readmemw(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub16(AX, temp);
|
||||
if (flags & D_FLAG) DI -= 2;
|
||||
else DI += 2;
|
||||
|
|
@ -286,7 +367,10 @@ static int opSCASW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSCASW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(es, EDI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(&_es);
|
||||
temp = readmemw(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub16(AX, temp);
|
||||
if (flags & D_FLAG) EDI -= 2;
|
||||
else EDI += 2;
|
||||
|
|
@ -297,7 +381,10 @@ static int opSCASW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSCASL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(es, DI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(&_es);
|
||||
temp = readmeml(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub32(EAX, temp);
|
||||
if (flags & D_FLAG) DI -= 4;
|
||||
else DI += 4;
|
||||
|
|
@ -307,7 +394,10 @@ static int opSCASL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSCASL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(es, EDI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(&_es);
|
||||
temp = readmeml(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub32(EAX, temp);
|
||||
if (flags & D_FLAG) EDI -= 4;
|
||||
else EDI += 4;
|
||||
|
|
@ -319,6 +409,8 @@ static int opSCASL_a32(uint32_t fetchdat)
|
|||
static int opINSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
check_io_perm(DX);
|
||||
temp = inb(DX);
|
||||
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -331,6 +423,8 @@ static int opINSB_a16(uint32_t fetchdat)
|
|||
static int opINSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
check_io_perm(DX);
|
||||
temp = inb(DX);
|
||||
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -344,6 +438,8 @@ static int opINSB_a32(uint32_t fetchdat)
|
|||
static int opINSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
temp = inw(DX);
|
||||
|
|
@ -357,6 +453,8 @@ static int opINSW_a16(uint32_t fetchdat)
|
|||
static int opINSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
temp = inw(DX);
|
||||
|
|
@ -371,6 +469,8 @@ static int opINSW_a32(uint32_t fetchdat)
|
|||
static int opINSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
|
@ -386,6 +486,8 @@ static int opINSL_a16(uint32_t fetchdat)
|
|||
static int opINSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_WRITE(&_es);
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
|
@ -401,7 +503,10 @@ static int opINSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opOUTSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
if (flags & D_FLAG) SI--;
|
||||
else SI++;
|
||||
|
|
@ -412,7 +517,10 @@ static int opOUTSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opOUTSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint8_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
if (flags & D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
|
|
@ -424,7 +532,10 @@ static int opOUTSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opOUTSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
if (flags & D_FLAG) SI -= 2;
|
||||
|
|
@ -436,7 +547,10 @@ static int opOUTSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opOUTSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint16_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
if (flags & D_FLAG) ESI -= 2;
|
||||
|
|
@ -449,7 +563,10 @@ static int opOUTSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opOUTSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
|
@ -463,7 +580,10 @@ static int opOUTSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opOUTSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
uint32_t temp;
|
||||
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
static int opXCHG_b_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
|
|
@ -12,7 +15,10 @@ static int opXCHG_b_a16(uint32_t fetchdat)
|
|||
static int opXCHG_b_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
|
|
@ -24,7 +30,10 @@ static int opXCHG_b_a32(uint32_t fetchdat)
|
|||
static int opXCHG_w_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
|
@ -35,7 +44,10 @@ static int opXCHG_w_a16(uint32_t fetchdat)
|
|||
static int opXCHG_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
|
@ -47,7 +59,10 @@ static int opXCHG_w_a32(uint32_t fetchdat)
|
|||
static int opXCHG_l_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
|
|
@ -58,7 +73,10 @@ static int opXCHG_l_a16(uint32_t fetchdat)
|
|||
static int opXCHG_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod != 3)
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ static int opFADD ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
if ((cpu_state.npxc >> 10) & 3) \
|
||||
fesetround(rounding_modes[(cpu_state.npxc >> 10) & 3]); \
|
||||
|
|
@ -19,6 +20,7 @@ static int opFCOM ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.npxs &= ~(C0|C2|C3); \
|
||||
cpu_state.npxs |= x87_compare(ST(0), (double)use_var); \
|
||||
|
|
@ -30,6 +32,7 @@ static int opFCOMP ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.npxs &= ~(C0|C2|C3); \
|
||||
cpu_state.npxs |= x87_compare(ST(0), (double)use_var); \
|
||||
|
|
@ -42,6 +45,7 @@ static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
x87_div(ST(0), ST(0), use_var); \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
|
|
@ -53,6 +57,7 @@ static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
x87_div(ST(0), use_var, ST(0)); \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
|
|
@ -64,6 +69,7 @@ static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
ST(0) *= use_var; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
|
|
@ -75,6 +81,7 @@ static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
ST(0) -= use_var; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
|
|
@ -86,6 +93,7 @@ static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
SEG_CHECK_READ(cpu_state.ea_seg); \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
ST(0) = use_var - ST(0); \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ static int opFILDiw_a16(uint32_t fetchdat)
|
|||
int16_t temp;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", (double)temp);
|
||||
|
|
@ -15,6 +16,7 @@ static int opFILDiw_a32(uint32_t fetchdat)
|
|||
int16_t temp;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", (double)temp);
|
||||
|
|
@ -28,6 +30,7 @@ static int opFISTiw_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
|
|
@ -41,6 +44,7 @@ static int opFISTiw_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
|
|
@ -55,6 +59,7 @@ static int opFISTPiw_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
|
|
@ -69,6 +74,7 @@ static int opFISTPiw_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
|
|
@ -84,6 +90,7 @@ static int opFILDiq_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
|
|
@ -99,6 +106,7 @@ static int opFILDiq_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
|
|
@ -116,6 +124,7 @@ static int FBSTP_a16(uint32_t fetchdat)
|
|||
int c;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FBSTP %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempd = ST(0);
|
||||
if (tempd < 0.0)
|
||||
|
|
@ -142,6 +151,7 @@ static int FBSTP_a32(uint32_t fetchdat)
|
|||
int c;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FBSTP %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempd = ST(0);
|
||||
if (tempd < 0.0)
|
||||
|
|
@ -168,6 +178,7 @@ static int FISTPiq_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
|
||||
temp64 = cpu_state.MM[cpu_state.TOP].q;
|
||||
|
|
@ -183,6 +194,7 @@ static int FISTPiq_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
|
||||
temp64 = cpu_state.MM[cpu_state.TOP].q;
|
||||
|
|
@ -199,6 +211,7 @@ static int opFILDil_a16(uint32_t fetchdat)
|
|||
int32_t templ;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %i\n", (double)templ, templ, templ);
|
||||
|
|
@ -211,6 +224,7 @@ static int opFILDil_a32(uint32_t fetchdat)
|
|||
int32_t templ;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %i\n", (double)templ, templ, templ);
|
||||
|
|
@ -224,6 +238,7 @@ static int opFISTil_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
|
|
@ -237,6 +252,7 @@ static int opFISTil_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
|
|
@ -251,6 +267,7 @@ static int opFISTPil_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
|
|
@ -265,6 +282,7 @@ static int opFISTPil_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
|
|
@ -280,6 +298,7 @@ static int opFLDe_a16(uint32_t fetchdat)
|
|||
double t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t=x87_ld80(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t);
|
||||
|
|
@ -292,6 +311,7 @@ static int opFLDe_a32(uint32_t fetchdat)
|
|||
double t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t=x87_ld80(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t);
|
||||
|
|
@ -304,6 +324,7 @@ static int opFSTPe_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
x87_st80(ST(0)); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
|
|
@ -314,6 +335,7 @@ static int opFSTPe_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
x87_st80(ST(0)); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
|
|
@ -326,6 +348,7 @@ static int opFLDd_a16(uint32_t fetchdat)
|
|||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.i = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t.d);
|
||||
|
|
@ -338,6 +361,7 @@ static int opFLDd_a32(uint32_t fetchdat)
|
|||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.i = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t.d);
|
||||
|
|
@ -351,6 +375,7 @@ static int opFSTd_a16(uint32_t fetchdat)
|
|||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i);
|
||||
|
|
@ -362,6 +387,7 @@ static int opFSTd_a32(uint32_t fetchdat)
|
|||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i);
|
||||
|
|
@ -374,6 +400,7 @@ static int opFSTPd_a16(uint32_t fetchdat)
|
|||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
|
|
@ -387,6 +414,7 @@ static int opFSTPd_a32(uint32_t fetchdat)
|
|||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
|
|
@ -401,6 +429,7 @@ static int opFLDs_a16(uint32_t fetchdat)
|
|||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.i = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", ts.s);
|
||||
|
|
@ -413,6 +442,7 @@ static int opFLDs_a32(uint32_t fetchdat)
|
|||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.i = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", ts.s);
|
||||
|
|
@ -426,6 +456,7 @@ static int opFSTs_a16(uint32_t fetchdat)
|
|||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i);
|
||||
|
|
@ -437,6 +468,7 @@ static int opFSTs_a32(uint32_t fetchdat)
|
|||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i);
|
||||
|
|
@ -449,6 +481,7 @@ static int opFSTPs_a16(uint32_t fetchdat)
|
|||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -461,6 +494,7 @@ static int opFSTPs_a32(uint32_t fetchdat)
|
|||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i); if (cpu_state.abrt) return 1;
|
||||
|
|
|
|||
|
|
@ -127,6 +127,7 @@ static int opFSTOR_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
FSTOR();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -134,6 +135,7 @@ static int opFSTOR_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
FSTOR();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -287,6 +289,7 @@ static int opFSAVE_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
FSAVE();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -294,6 +297,7 @@ static int opFSAVE_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
FSAVE();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -302,6 +306,7 @@ static int opFSTSW_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw((cpu_state.npxs & 0xC7FF) | (cpu_state.TOP << 11));
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -311,6 +316,7 @@ static int opFSTSW_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw((cpu_state.npxs & 0xC7FF) | (cpu_state.TOP << 11));
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -698,6 +704,7 @@ static int opFLDENV_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
FLDENV();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -705,6 +712,7 @@ static int opFLDENV_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
FLDENV();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -714,6 +722,7 @@ static int opFLDCW_a16(uint32_t fetchdat)
|
|||
uint16_t tempw;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempw = geteaw();
|
||||
if (cpu_state.abrt) return 1;
|
||||
|
|
@ -727,6 +736,7 @@ static int opFLDCW_a32(uint32_t fetchdat)
|
|||
uint16_t tempw;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_READ(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempw = geteaw();
|
||||
if (cpu_state.abrt) return 1;
|
||||
|
|
@ -784,6 +794,7 @@ static int opFSTENV_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
FSTENV();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -791,6 +802,7 @@ static int opFSTENV_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
FSTENV();
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
@ -799,6 +811,7 @@ static int opFSTCW_a16(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw(cpu_state.npxc);
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -808,6 +821,7 @@ static int opFSTCW_a32(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw(cpu_state.npxc);
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
|
|||
Loading…
Reference in a new issue