Perform NULL segment checks upfront in opcode handlers, rather than on every memory access.
This removes the need to pass the segment to readmem*l()/writemem*l().
This commit is contained in:
SarahW
parent
648aa0e3e8
commit
0f0a1c3223
31 changed files with 976 additions and 325 deletions
340
src/mem.c
340
src/mem.c
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@ -295,7 +295,6 @@ uint32_t mmutranslatereal(uint32_t addr, int rw)
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if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && ((CPL == 3 && !cpl_override) || cr0&WP_FLAG)))
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{
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// if (!nopageerrors) pclog("Page not present! %08X %08X %02X %02X %i %08X %04X:%08X %04X:%08X %i %i %i\n",addr,temp,opcode,opcode2,frame,rmdat32, CS,pc,SS,ESP,ins,CPL,rw);
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// dumpregs();
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// exit(-1);
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// if (addr == 0x815F6E90) output = 3;
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@ -498,15 +497,9 @@ void writemembl(uint32_t addr, uint8_t val)
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// else pclog("Bad writemembl %08X %02X %04X:%08X\n", addr, val, CS, pc);
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}
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uint8_t readmemb386l(uint32_t seg, uint32_t addr)
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uint8_t readmemb386l(uint32_t addr)
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{
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if (seg==-1)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! rb %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return -1;
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}
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mem_logical_addr = addr = addr + seg;
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mem_logical_addr = addr;
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/* if (readlookup2[mem_logical_addr >> 12] != 0xFFFFFFFF)
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{
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return ram[readlookup2[mem_logical_addr >> 12] + (mem_logical_addr & 0xFFF)];
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@ -525,16 +518,9 @@ uint8_t readmemb386l(uint32_t seg, uint32_t addr)
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return 0xFF;
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}
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void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
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void writememb386l(uint32_t addr, uint8_t val)
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{
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if (seg==-1)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! wb %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return;
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}
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mem_logical_addr = addr = addr + seg;
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mem_logical_addr = addr;
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if (page_lookup[addr>>12])
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{
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page_lookup[addr>>12]->write_b(addr, val, page_lookup[addr>>12]);
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@ -555,352 +541,308 @@ void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
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// else pclog("Bad writememb386l %08X %02X %04X:%08X\n", addr, val, CS, pc);
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}
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uint16_t readmemwl(uint32_t seg, uint32_t addr)
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uint16_t readmemwl(uint32_t addr)
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{
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uint32_t addr2 = mem_logical_addr = seg + addr;
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mem_logical_addr = addr;
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if (seg==-1)
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if (addr & 1)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! rw %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return -1;
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}
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if (addr2 & 1)
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{
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if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
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if (!cpu_cyrix_alignment || (addr & 7) == 7)
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cycles -= timing_misaligned;
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if ((addr2 & 0xFFF) > 0xFFE)
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if ((addr & 0xFFF) > 0xFFE)
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{
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if (cr0 >> 31)
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{
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if (mmutranslate_read(addr2) == 0xffffffff) return 0xffff;
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if (mmutranslate_read(addr2+1) == 0xffffffff) return 0xffff;
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if (mmutranslate_read(addr) == 0xffffffff) return 0xffff;
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if (mmutranslate_read(addr+1) == 0xffffffff) return 0xffff;
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}
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if (is386) return readmemb386l(seg,addr)|(readmemb386l(seg,addr+1)<<8);
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else return readmembl(seg+addr)|(readmembl(seg+addr+1)<<8);
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if (is386) return readmemb386l(addr)|(readmemb386l(addr+1)<<8);
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else return readmembl(addr)|(readmembl(addr+1)<<8);
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}
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else if (readlookup2[addr2 >> 12] != -1)
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return *(uint16_t *)(readlookup2[addr2 >> 12] + addr2);
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else if (readlookup2[addr >> 12] != -1)
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return *(uint16_t *)(readlookup2[addr >> 12] + addr);
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}
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if (cr0>>31)
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{
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addr2 = mmutranslate_read(addr2);
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if (addr2==0xFFFFFFFF) return 0xFFFF;
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addr = mmutranslate_read(addr);
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if (addr==0xFFFFFFFF) return 0xFFFF;
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}
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addr2 &= rammask;
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addr &= rammask;
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if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]);
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if (_mem_read_w[addr >> 14]) return _mem_read_w[addr >> 14](addr, _mem_priv_r[addr >> 14]);
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if (_mem_read_b[addr2 >> 14])
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{
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if (AT) return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[(addr2 + 1) >> 14](addr2 + 1, _mem_priv_r[addr2 >> 14]) << 8);
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else return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[(seg + ((addr + 1) & 0xffff)) >> 14](seg + ((addr + 1) & 0xffff), _mem_priv_r[addr2 >> 14]) << 8);
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}
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// pclog("Bad readmemwl %08X\n", addr2);
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if (_mem_read_b[addr >> 14])
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return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]) | (_mem_read_b[(addr + 1) >> 14](addr + 1, _mem_priv_r[addr >> 14]) << 8);
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// pclog("Bad readmemwl %08X\n", addr);
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return 0xffff;
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}
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void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
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void writememwl(uint32_t addr, uint16_t val)
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{
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uint32_t addr2 = mem_logical_addr = seg + addr;
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mem_logical_addr = addr;
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if (seg==-1)
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if (addr & 1)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! ww %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return;
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}
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if (addr2 & 1)
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{
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if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
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if (!cpu_cyrix_alignment || (addr & 7) == 7)
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cycles -= timing_misaligned;
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if ((addr2 & 0xFFF) > 0xFFE)
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if ((addr & 0xFFF) > 0xFFE)
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{
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if (cr0 >> 31)
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{
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if (mmutranslate_write(addr2) == 0xffffffff) return;
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if (mmutranslate_write(addr2+1) == 0xffffffff) return;
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if (mmutranslate_write(addr) == 0xffffffff) return;
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if (mmutranslate_write(addr+1) == 0xffffffff) return;
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}
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if (is386)
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{
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writememb386l(seg,addr,val);
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writememb386l(seg,addr+1,val>>8);
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writememb386l(addr,val);
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writememb386l(addr+1,val>>8);
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}
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else
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{
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writemembl(seg+addr,val);
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writemembl(seg+addr+1,val>>8);
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writemembl(addr,val);
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writemembl(addr+1,val>>8);
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}
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return;
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}
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else if (writelookup2[addr2 >> 12] != -1)
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else if (writelookup2[addr >> 12] != -1)
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{
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*(uint16_t *)(writelookup2[addr2 >> 12] + addr2) = val;
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*(uint16_t *)(writelookup2[addr >> 12] + addr) = val;
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return;
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}
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}
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if (page_lookup[addr2>>12])
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if (page_lookup[addr>>12])
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{
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page_lookup[addr2>>12]->write_w(addr2, val, page_lookup[addr2>>12]);
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page_lookup[addr>>12]->write_w(addr, val, page_lookup[addr>>12]);
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return;
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}
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if (cr0>>31)
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{
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addr2 = mmutranslate_write(addr2);
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if (addr2==0xFFFFFFFF) return;
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addr = mmutranslate_write(addr);
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if (addr==0xFFFFFFFF) return;
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}
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addr2 &= rammask;
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addr &= rammask;
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/* if (addr2 >= 0xa0000 && addr2 < 0xc0000)
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pclog("writememwl %08X %02X\n", addr2, val);*/
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if (_mem_write_w[addr2 >> 14])
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if (_mem_write_w[addr >> 14])
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{
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_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
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_mem_write_w[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
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return;
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}
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if (_mem_write_b[addr2 >> 14])
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if (_mem_write_b[addr >> 14])
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{
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_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
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_mem_write_b[(addr2 + 1) >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
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_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
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_mem_write_b[(addr + 1) >> 14](addr + 1, val >> 8, _mem_priv_w[addr >> 14]);
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return;
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}
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// pclog("Bad writememwl %08X %04X\n", addr2, val);
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// pclog("Bad writememwl %08X %04X\n", addr, val);
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}
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uint32_t readmemll(uint32_t seg, uint32_t addr)
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uint32_t readmemll(uint32_t addr)
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{
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uint32_t addr2 = mem_logical_addr = seg + addr;
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mem_logical_addr = addr;
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if (seg==-1)
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if (addr & 3)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return -1;
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}
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if (addr2 & 3)
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{
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if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
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if (!cpu_cyrix_alignment || (addr & 7) > 4)
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cycles -= timing_misaligned;
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if ((addr2&0xFFF)>0xFFC)
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if ((addr&0xFFF)>0xFFC)
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{
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if (cr0>>31)
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{
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if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
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if (mmutranslate_read(addr2+3) == 0xffffffff) return 0xffffffff;
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if (mmutranslate_read(addr) == 0xffffffff) return 0xffffffff;
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if (mmutranslate_read(addr+3) == 0xffffffff) return 0xffffffff;
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}
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return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
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return readmemwl(addr)|(readmemwl(addr+2)<<16);
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}
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else if (readlookup2[addr2 >> 12] != -1)
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return *(uint32_t *)(readlookup2[addr2 >> 12] + addr2);
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else if (readlookup2[addr >> 12] != -1)
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return *(uint32_t *)(readlookup2[addr >> 12] + addr);
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}
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if (cr0>>31)
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{
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addr2 = mmutranslate_read(addr2);
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if (addr2==0xFFFFFFFF) return 0xFFFFFFFF;
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addr = mmutranslate_read(addr);
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if (addr==0xFFFFFFFF) return 0xFFFFFFFF;
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}
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addr2&=rammask;
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addr&=rammask;
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if (_mem_read_l[addr2 >> 14]) return _mem_read_l[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]);
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if (_mem_read_l[addr >> 14]) return _mem_read_l[addr >> 14](addr, _mem_priv_r[addr >> 14]);
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if (_mem_read_w[addr2 >> 14]) return _mem_read_w[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_w[addr2 >> 14](addr2 + 2, _mem_priv_r[addr2 >> 14]) << 16);
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if (_mem_read_w[addr >> 14]) return _mem_read_w[addr >> 14](addr, _mem_priv_r[addr >> 14]) | (_mem_read_w[addr >> 14](addr + 2, _mem_priv_r[addr >> 14]) << 16);
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if (_mem_read_b[addr2 >> 14]) return _mem_read_b[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) | (_mem_read_b[addr2 >> 14](addr2 + 1, _mem_priv_r[addr2 >> 14]) << 8) | (_mem_read_b[addr2 >> 14](addr2 + 2, _mem_priv_r[addr2 >> 14]) << 16) | (_mem_read_b[addr2 >> 14](addr2 + 3, _mem_priv_r[addr2 >> 14]) << 24);
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if (_mem_read_b[addr >> 14]) return _mem_read_b[addr >> 14](addr, _mem_priv_r[addr >> 14]) | (_mem_read_b[addr >> 14](addr + 1, _mem_priv_r[addr >> 14]) << 8) | (_mem_read_b[addr >> 14](addr + 2, _mem_priv_r[addr >> 14]) << 16) | (_mem_read_b[addr >> 14](addr + 3, _mem_priv_r[addr >> 14]) << 24);
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// pclog("Bad readmemll %08X\n", addr2);
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// pclog("Bad readmemll %08X\n", addr);
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return 0xffffffff;
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}
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void writememll(uint32_t seg, uint32_t addr, uint32_t val)
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void writememll(uint32_t addr, uint32_t val)
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{
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uint32_t addr2 = mem_logical_addr = seg + addr;
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mem_logical_addr = addr;
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if (seg==-1)
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if (addr & 3)
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{
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x86gpf("NULL segment", 0);
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printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
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return;
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}
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if (addr2 & 3)
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{
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if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
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if (!cpu_cyrix_alignment || (addr & 7) > 4)
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cycles -= timing_misaligned;
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if ((addr2 & 0xFFF) > 0xFFC)
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if ((addr & 0xFFF) > 0xFFC)
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{
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if (cr0>>31)
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{
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if (mmutranslate_write(addr2) == 0xffffffff) return;
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if (mmutranslate_write(addr2+3) == 0xffffffff) return;
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if (mmutranslate_write(addr) == 0xffffffff) return;
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if (mmutranslate_write(addr+3) == 0xffffffff) return;
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}
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writememwl(seg,addr,val);
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writememwl(seg,addr+2,val>>16);
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writememwl(addr,val);
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writememwl(addr+2,val>>16);
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return;
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}
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else if (writelookup2[addr2 >> 12] != -1)
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else if (writelookup2[addr >> 12] != -1)
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{
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*(uint32_t *)(writelookup2[addr2 >> 12] + addr2) = val;
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*(uint32_t *)(writelookup2[addr >> 12] + addr) = val;
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return;
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}
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}
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if (page_lookup[addr2>>12])
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if (page_lookup[addr>>12])
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{
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page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
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page_lookup[addr>>12]->write_l(addr, val, page_lookup[addr>>12]);
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return;
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}
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if (cr0>>31)
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{
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addr2 = mmutranslate_write(addr2);
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if (addr2==0xFFFFFFFF) return;
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addr = mmutranslate_write(addr);
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if (addr==0xFFFFFFFF) return;
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}
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addr2&=rammask;
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addr&=rammask;
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/* if (addr >= 0xa0000 && addr < 0xc0000)
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pclog("writememll %08X %08X\n", addr, val);*/
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if (_mem_write_l[addr2 >> 14])
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if (_mem_write_l[addr >> 14])
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{
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_mem_write_l[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
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_mem_write_l[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
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return;
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}
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if (_mem_write_w[addr2 >> 14])
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if (_mem_write_w[addr >> 14])
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{
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_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
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_mem_write_w[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
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_mem_write_w[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
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_mem_write_w[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
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return;
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}
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if (_mem_write_b[addr2 >> 14])
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if (_mem_write_b[addr >> 14])
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{
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_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
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_mem_write_b[addr2 >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
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_mem_write_b[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
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_mem_write_b[addr2 >> 14](addr2 + 3, val >> 24, _mem_priv_w[addr2 >> 14]);
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_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
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_mem_write_b[addr >> 14](addr + 1, val >> 8, _mem_priv_w[addr >> 14]);
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_mem_write_b[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
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_mem_write_b[addr >> 14](addr + 3, val >> 24, _mem_priv_w[addr >> 14]);
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return;
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}
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// pclog("Bad writememll %08X %08X\n", addr2, val);
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// pclog("Bad writememll %08X %08X\n", addr, val);
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}
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uint64_t readmemql(uint32_t seg, uint32_t addr)
|
||||
uint64_t readmemql(uint32_t addr)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (addr2 & 7)
|
||||
if (addr & 7)
|
||||
{
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFF8)
|
||||
if ((addr & 0xFFF) > 0xFF8)
|
||||
{
|
||||
if (cr0>>31)
|
||||
{
|
||||
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr2+7) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr) == 0xffffffff) return 0xffffffff;
|
||||
if (mmutranslate_read(addr+7) == 0xffffffff) return 0xffffffff;
|
||||
}
|
||||
return readmemll(seg,addr)|((uint64_t)readmemll(seg,addr+4)<<32);
|
||||
return readmemll(addr)|((uint64_t)readmemll(addr+4)<<32);
|
||||
}
|
||||
else if (readlookup2[addr2 >> 12] != -1)
|
||||
return *(uint64_t *)(readlookup2[addr2 >> 12] + addr2);
|
||||
else if (readlookup2[addr >> 12] != -1)
|
||||
return *(uint64_t *)(readlookup2[addr >> 12] + addr);
|
||||
}
|
||||
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_read(addr2);
|
||||
if (addr2==0xFFFFFFFF) return 0xFFFFFFFF;
|
||||
addr = mmutranslate_read(addr);
|
||||
if (addr==0xFFFFFFFF) return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
addr2&=rammask;
|
||||
addr&=rammask;
|
||||
|
||||
if (_mem_read_l[addr2 >> 14])
|
||||
return _mem_read_l[addr2 >> 14](addr2, _mem_priv_r[addr2 >> 14]) |
|
||||
((uint64_t)_mem_read_l[addr2 >> 14](addr2 + 4, _mem_priv_r[addr2 >> 14]) << 32);
|
||||
if (_mem_read_l[addr >> 14])
|
||||
return _mem_read_l[addr >> 14](addr, _mem_priv_r[addr >> 14]) |
|
||||
((uint64_t)_mem_read_l[addr >> 14](addr + 4, _mem_priv_r[addr >> 14]) << 32);
|
||||
|
||||
return readmemll(seg,addr) | ((uint64_t)readmemll(seg,addr+4)<<32);
|
||||
return readmemll(addr) | ((uint64_t)readmemll(addr+4)<<32);
|
||||
}
|
||||
|
||||
void writememql(uint32_t seg, uint32_t addr, uint64_t val)
|
||||
void writememql(uint32_t addr, uint64_t val)
|
||||
{
|
||||
uint32_t addr2 = mem_logical_addr = seg + addr;
|
||||
mem_logical_addr = addr;
|
||||
|
||||
if (seg==-1)
|
||||
{
|
||||
x86gpf("NULL segment", 0);
|
||||
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
|
||||
return;
|
||||
}
|
||||
if (addr2 & 7)
|
||||
if (addr & 7)
|
||||
{
|
||||
cycles -= timing_misaligned;
|
||||
if ((addr2 & 0xFFF) > 0xFF8)
|
||||
if ((addr & 0xFFF) > 0xFF8)
|
||||
{
|
||||
if (cr0>>31)
|
||||
{
|
||||
if (mmutranslate_write(addr2) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr2+7) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr) == 0xffffffff) return;
|
||||
if (mmutranslate_write(addr+7) == 0xffffffff) return;
|
||||
}
|
||||
writememll(seg, addr, val);
|
||||
writememll(seg, addr+4, val >> 32);
|
||||
writememll(addr, val);
|
||||
writememll(addr+4, val >> 32);
|
||||
return;
|
||||
}
|
||||
else if (writelookup2[addr2 >> 12] != -1)
|
||||
else if (writelookup2[addr >> 12] != -1)
|
||||
{
|
||||
*(uint64_t *)(writelookup2[addr2 >> 12] + addr2) = val;
|
||||
*(uint64_t *)(writelookup2[addr >> 12] + addr) = val;
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (page_lookup[addr2>>12])
|
||||
if (page_lookup[addr>>12])
|
||||
{
|
||||
page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
|
||||
page_lookup[addr2>>12]->write_l(addr2 + 4, val >> 32, page_lookup[addr2>>12]);
|
||||
page_lookup[addr>>12]->write_l(addr, val, page_lookup[addr>>12]);
|
||||
page_lookup[addr>>12]->write_l(addr + 4, val >> 32, page_lookup[addr>>12]);
|
||||
return;
|
||||
}
|
||||
if (cr0>>31)
|
||||
{
|
||||
addr2 = mmutranslate_write(addr2);
|
||||
if (addr2==0xFFFFFFFF) return;
|
||||
addr = mmutranslate_write(addr);
|
||||
if (addr==0xFFFFFFFF) return;
|
||||
}
|
||||
|
||||
addr2&=rammask;
|
||||
addr&=rammask;
|
||||
|
||||
if (_mem_write_l[addr2 >> 14])
|
||||
if (_mem_write_l[addr >> 14])
|
||||
{
|
||||
_mem_write_l[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_l[addr2 >> 14](addr2+4, val >> 32, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_l[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_l[addr >> 14](addr+4, val >> 32, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
if (_mem_write_w[addr2 >> 14])
|
||||
if (_mem_write_w[addr >> 14])
|
||||
{
|
||||
_mem_write_w[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 4, val >> 32, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr2 >> 14](addr2 + 6, val >> 48, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_w[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 4, val >> 32, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_w[addr >> 14](addr + 6, val >> 48, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
if (_mem_write_b[addr2 >> 14])
|
||||
if (_mem_write_b[addr >> 14])
|
||||
{
|
||||
_mem_write_b[addr2 >> 14](addr2, val, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 1, val >> 8, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 2, val >> 16, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 3, val >> 24, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 4, val >> 32, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 5, val >> 40, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 6, val >> 48, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr2 >> 14](addr2 + 7, val >> 56, _mem_priv_w[addr2 >> 14]);
|
||||
_mem_write_b[addr >> 14](addr, val, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 1, val >> 8, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 2, val >> 16, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 3, val >> 24, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 4, val >> 32, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 5, val >> 40, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 6, val >> 48, _mem_priv_w[addr >> 14]);
|
||||
_mem_write_b[addr >> 14](addr + 7, val >> 56, _mem_priv_w[addr >> 14]);
|
||||
return;
|
||||
}
|
||||
// pclog("Bad writememql %08X %08X\n", addr2, val);
|
||||
// pclog("Bad writememql %08X %08X\n", addr, val);
|
||||
}
|
||||
|
||||
uint8_t mem_readb_phys(uint32_t addr)
|
||||
|
|
|
|||
Loading…
Reference in a new issue