Reorganised FPU emulation.
This commit is contained in:
TomW
parent
0aa0887c58
commit
087f412d3f
12 changed files with 2670 additions and 1436 deletions
738
src/x87_ops_misc.h
Normal file
738
src/x87_ops_misc.h
Normal file
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@ -0,0 +1,738 @@
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static int opFSTSW_AX(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FSTSW\n");
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AX = npxs;
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cycles -= 3;
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return 0;
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}
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static int opFNOP(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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cycles -= 4;
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return 0;
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}
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static int opFCLEX(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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npxs &= 0xff00;
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cycles -= 4;
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return 0;
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}
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static int opFINIT(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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npxc = 0x37F;
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npxs = 0;
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tag = 0xFFFF;
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TOP = 0;
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cycles -= 17;
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return 0;
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}
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static int opFFREE(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FFREE\n");
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tag |= (3 << (((TOP + fetchdat) & 7) << 1));
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cycles -= 3;
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return 0;
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}
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static int opFST(uint32_t fetchdat)
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{
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int temp;
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FP_ENTER();
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pc++;
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if (fplog) pclog("FST\n");
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ST(fetchdat & 7) = ST(0);
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temp = (tag >> ((TOP & 7) << 1)) & 3;
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tag &= ~(3 << (((TOP + fetchdat) & 7) << 1));
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tag |= (temp << (((TOP + fetchdat) & 7) << 1));
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cycles -= 3;
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return 0;
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}
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static int opFSTP(uint32_t fetchdat)
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{
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int temp;
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FP_ENTER();
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pc++;
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if (fplog) pclog("FSTP\n");
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ST(fetchdat & 7) = ST(0);
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temp = (tag >> ((TOP & 7) << 1)) & 3;
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tag &= ~(3 << (((TOP + fetchdat) & 7) << 1));
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tag |= (temp << (((TOP + fetchdat) & 7) << 1));
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x87_pop();
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cycles -= 3;
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return 0;
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}
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static void FSTOR()
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{
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switch ((cr0 & 1) | (op32 & 0x100))
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{
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case 0x000: /*16-bit real mode*/
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case 0x001: /*16-bit protected mode*/
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npxc = readmemw(easeg, eaaddr);
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npxs = readmemw(easeg, eaaddr+2);
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tag = readmemw(easeg, eaaddr+4);
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TOP = (npxs >> 11) & 7;
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eaaddr += 14;
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break;
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case 0x100: /*32-bit real mode*/
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case 0x101: /*32-bit protected mode*/
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npxc = readmemw(easeg, eaaddr);
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npxs = readmemw(easeg, eaaddr+4);
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tag = readmemw(easeg, eaaddr+8);
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TOP = (npxs >> 11) & 7;
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eaaddr += 28;
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break;
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}
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x87_ldmmx(&MM[0]); ST(0)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[1]); ST(1)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[2]); ST(2)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[3]); ST(3)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[4]); ST(4)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[5]); ST(5)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[6]); ST(6)=x87_ld80(); eaaddr += 10;
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x87_ldmmx(&MM[7]); ST(7)=x87_ld80();
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ismmx = 0;
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/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
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something like this is needed*/
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if (MM[0].w[4] == 0xffff && MM[1].w[4] == 0xffff && MM[2].w[4] == 0xffff && MM[3].w[4] == 0xffff &&
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MM[4].w[4] == 0xffff && MM[5].w[4] == 0xffff && MM[6].w[4] == 0xffff && MM[7].w[4] == 0xffff &&
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!TOP && !tag)
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ismmx = 1;
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cycles -= (cr0 & 1) ? 34 : 44;
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if (fplog) pclog("FRSTOR %08X:%08X %i %i %04X\n", easeg, eaaddr, ismmx, TOP, tag);
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}
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static int opFSTOR_a16(uint32_t fetchdat)
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{
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FP_ENTER();
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fetch_ea_16(fetchdat);
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FSTOR();
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return abrt;
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}
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static int opFSTOR_a32(uint32_t fetchdat)
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{
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FP_ENTER();
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fetch_ea_32(fetchdat);
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FSTOR();
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return abrt;
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}
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static void FSAVE()
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{
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if (fplog) pclog("FSAVE %08X:%08X %i\n", easeg, eaaddr, ismmx);
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npxs = (npxs & ~(7 << 11)) | (TOP << 11);
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switch ((cr0&1)|(op32&0x100))
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{
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case 0x000: /*16-bit real mode*/
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writememw(easeg,eaaddr,npxc);
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writememw(easeg,eaaddr+2,npxs);
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writememw(easeg,eaaddr+4,tag);
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writememw(easeg,eaaddr+6,x87_pc_off);
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writememw(easeg,eaaddr+10,x87_op_off);
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eaaddr+=14;
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if (ismmx)
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{
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x87_stmmx(MM[0]); eaaddr+=10;
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x87_stmmx(MM[1]); eaaddr+=10;
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x87_stmmx(MM[2]); eaaddr+=10;
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x87_stmmx(MM[3]); eaaddr+=10;
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x87_stmmx(MM[4]); eaaddr+=10;
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x87_stmmx(MM[5]); eaaddr+=10;
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x87_stmmx(MM[6]); eaaddr+=10;
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x87_stmmx(MM[7]);
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}
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else
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{
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x87_st80(ST(0)); eaaddr+=10;
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x87_st80(ST(1)); eaaddr+=10;
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x87_st80(ST(2)); eaaddr+=10;
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x87_st80(ST(3)); eaaddr+=10;
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x87_st80(ST(4)); eaaddr+=10;
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x87_st80(ST(5)); eaaddr+=10;
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x87_st80(ST(6)); eaaddr+=10;
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x87_st80(ST(7));
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}
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break;
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case 0x001: /*16-bit protected mode*/
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writememw(easeg,eaaddr,npxc);
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writememw(easeg,eaaddr+2,npxs);
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writememw(easeg,eaaddr+4,tag);
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writememw(easeg,eaaddr+6,x87_pc_off);
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writememw(easeg,eaaddr+8,x87_pc_seg);
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writememw(easeg,eaaddr+10,x87_op_off);
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writememw(easeg,eaaddr+12,x87_op_seg);
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eaaddr+=14;
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if (ismmx)
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{
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x87_stmmx(MM[0]); eaaddr+=10;
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x87_stmmx(MM[1]); eaaddr+=10;
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x87_stmmx(MM[2]); eaaddr+=10;
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x87_stmmx(MM[3]); eaaddr+=10;
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x87_stmmx(MM[4]); eaaddr+=10;
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x87_stmmx(MM[5]); eaaddr+=10;
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x87_stmmx(MM[6]); eaaddr+=10;
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x87_stmmx(MM[7]);
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}
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else
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{
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x87_st80(ST(0)); eaaddr+=10;
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x87_st80(ST(1)); eaaddr+=10;
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x87_st80(ST(2)); eaaddr+=10;
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x87_st80(ST(3)); eaaddr+=10;
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x87_st80(ST(4)); eaaddr+=10;
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x87_st80(ST(5)); eaaddr+=10;
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x87_st80(ST(6)); eaaddr+=10;
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x87_st80(ST(7));
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}
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break;
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case 0x100: /*32-bit real mode*/
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writememw(easeg,eaaddr,npxc);
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writememw(easeg,eaaddr+4,npxs);
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writememw(easeg,eaaddr+8,tag);
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writememw(easeg,eaaddr+12,x87_pc_off);
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writememw(easeg,eaaddr+20,x87_op_off);
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writememl(easeg,eaaddr+24,(x87_op_off>>16)<<12);
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eaaddr+=28;
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if (ismmx)
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{
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x87_stmmx(MM[0]); eaaddr+=10;
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x87_stmmx(MM[1]); eaaddr+=10;
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x87_stmmx(MM[2]); eaaddr+=10;
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x87_stmmx(MM[3]); eaaddr+=10;
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x87_stmmx(MM[4]); eaaddr+=10;
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x87_stmmx(MM[5]); eaaddr+=10;
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x87_stmmx(MM[6]); eaaddr+=10;
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x87_stmmx(MM[7]);
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}
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else
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{
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x87_st80(ST(0)); eaaddr+=10;
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x87_st80(ST(1)); eaaddr+=10;
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x87_st80(ST(2)); eaaddr+=10;
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x87_st80(ST(3)); eaaddr+=10;
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x87_st80(ST(4)); eaaddr+=10;
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x87_st80(ST(5)); eaaddr+=10;
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x87_st80(ST(6)); eaaddr+=10;
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x87_st80(ST(7));
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}
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break;
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case 0x101: /*32-bit protected mode*/
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writememw(easeg,eaaddr,npxc);
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writememw(easeg,eaaddr+4,npxs);
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writememw(easeg,eaaddr+8,tag);
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writememl(easeg,eaaddr+12,x87_pc_off);
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writememl(easeg,eaaddr+16,x87_pc_seg);
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writememl(easeg,eaaddr+20,x87_op_off);
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writememl(easeg,eaaddr+24,x87_op_seg);
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eaaddr+=28;
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if (ismmx)
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{
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x87_stmmx(MM[0]); eaaddr+=10;
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x87_stmmx(MM[1]); eaaddr+=10;
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x87_stmmx(MM[2]); eaaddr+=10;
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x87_stmmx(MM[3]); eaaddr+=10;
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x87_stmmx(MM[4]); eaaddr+=10;
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x87_stmmx(MM[5]); eaaddr+=10;
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x87_stmmx(MM[6]); eaaddr+=10;
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x87_stmmx(MM[7]);
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}
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else
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{
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x87_st80(ST(0)); eaaddr+=10;
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x87_st80(ST(1)); eaaddr+=10;
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x87_st80(ST(2)); eaaddr+=10;
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x87_st80(ST(3)); eaaddr+=10;
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x87_st80(ST(4)); eaaddr+=10;
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x87_st80(ST(5)); eaaddr+=10;
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x87_st80(ST(6)); eaaddr+=10;
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x87_st80(ST(7));
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}
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break;
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}
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cycles-=(cr0&1)?56:67;
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}
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static int opFSAVE_a16(uint32_t fetchdat)
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{
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FP_ENTER();
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fetch_ea_16(fetchdat);
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FSAVE();
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return abrt;
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}
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static int opFSAVE_a32(uint32_t fetchdat)
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{
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FP_ENTER();
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fetch_ea_32(fetchdat);
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FSAVE();
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return abrt;
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}
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static int opFSTSW_a16(uint32_t fetchdat)
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{
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FP_ENTER();
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fetch_ea_16(fetchdat);
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if (fplog) pclog("FSTSW %08X:%08X\n", easeg, eaaddr);
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seteaw((npxs & 0xC7FF) | (TOP << 11));
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cycles -= 3;
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return abrt;
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}
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static int opFSTSW_a32(uint32_t fetchdat)
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{
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FP_ENTER();
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fetch_ea_32(fetchdat);
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if (fplog) pclog("FSTSW %08X:%08X\n", easeg, eaaddr);
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seteaw((npxs & 0xC7FF) | (TOP << 11));
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cycles -= 3;
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return abrt;
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}
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static int opFLD(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLD %f\n", ST(fetchdat & 7));
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x87_push(ST(fetchdat&7));
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cycles -= 4;
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return 0;
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}
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static int opFXCH(uint32_t fetchdat)
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{
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double td;
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FP_ENTER();
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pc++;
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if (fplog) pclog("FXCH\n");
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td = ST(0);
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ST(0) = ST(fetchdat&7);
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ST(fetchdat&7) = td;
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cycles -= 4;
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return 0;
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}
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static int opFCHS(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FCHS\n");
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ST(0) = -ST(0);
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cycles -= 6;
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return 0;
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}
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static int opFABS(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FABS %f\n", ST(0));
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ST(0) = fabs(ST(0));
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cycles -= 3;
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return 0;
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}
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static int opFTST(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FTST\n");
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npxs &= ~(C0|C2|C3);
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if (ST(0) == 0.0) npxs |= C3;
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else if (ST(0) < 0.0) npxs |= C0;
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cycles -= 4;
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return 0;
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}
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static int opFXAM(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FXAM %i %f\n", ((tag>>((TOP&7)<<1))&3), ST(0));
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npxs &= ~(C0|C2|C3);
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if (((tag>>((TOP&7)<<1))&3)==3) npxs |= (C0|C3);
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else if (ST(0) == 0.0) npxs |= C3;
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else npxs |= C2;
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if (ST(0) < 0.0) npxs |= C1;
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cycles -= 8;
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return 0;
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}
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static int opFLD1(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLD1\n");
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x87_push(1.0);
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cycles -= 4;
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return 0;
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}
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static int opFLDL2T(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLDL2T\n");
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x87_push(3.3219280948873623);
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cycles -= 8;
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return 0;
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}
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static int opFLDL2E(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLDL2E\n");
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x87_push(1.4426950408889634);
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cycles -= 8;
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return 0;
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}
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static int opFLDPI(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLDPI\n");
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x87_push(3.141592653589793);
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cycles -= 8;
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return 0;
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}
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static int opFLDEG2(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLDEG2\n");
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x87_push(0.3010299956639812);
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cycles -= 8;
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return 0;
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}
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static int opFLDLN2(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLDLN2\n");
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x87_push(0.693147180559945);
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cycles -= 8;
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return 0;
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}
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static int opFLDZ(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
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if (fplog) pclog("FLDZ\n");
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x87_push(0.0);
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tag |= (1<<((TOP&7)<<1));
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cycles -= 4;
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return 0;
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}
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static int opF2XM1(uint32_t fetchdat)
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{
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FP_ENTER();
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pc++;
|
||||
if (fplog) pclog("F2XM1\n");
|
||||
ST(0) = pow(2.0, ST(0)) - 1.0;
|
||||
cycles -= 200;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFYL2X(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FYL2X\n");
|
||||
ST(1) = ST(1) * (log(ST(0)) / log(2.0));
|
||||
x87_pop();
|
||||
cycles -= 250;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFPTAN(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FPTAN\n");
|
||||
ST(0) = tan(ST(0));
|
||||
x87_push(1.0);
|
||||
npxs &= ~C2;
|
||||
cycles -= 235;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFPATAN(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FPATAN\n");
|
||||
ST(1) = atan2(ST(1), ST(0));
|
||||
x87_pop();
|
||||
cycles -= 250;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFDECSTP(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FDECSTP\n");
|
||||
TOP = (TOP - 1) & 7;
|
||||
cycles -= 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFINCSTP(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FDECSTP\n");
|
||||
TOP = (TOP + 1) & 7;
|
||||
cycles -= 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFPREM(uint32_t fetchdat)
|
||||
{
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FPREM %f %f ", ST(0), ST(1));
|
||||
temp64 = (int64_t)(ST(0) / ST(1));
|
||||
ST(0) = ST(0) - (ST(1) * (double)temp64);
|
||||
if (fplog) pclog("%f\n", ST(0));
|
||||
npxs &= ~(C0|C1|C2|C3);
|
||||
if (temp64 & 4) npxs|=C0;
|
||||
if (temp64 & 2) npxs|=C3;
|
||||
if (temp64 & 1) npxs|=C1;
|
||||
cycles -= 100;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFSQRT(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FSQRT\n");
|
||||
ST(0) = sqrt(ST(0));
|
||||
cycles -= 83;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFSINCOS(uint32_t fetchdat)
|
||||
{
|
||||
double td;
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FSINCOS\n");
|
||||
td = ST(0);
|
||||
ST(0) = sin(td);
|
||||
x87_push(cos(td));
|
||||
npxs &= ~C2;
|
||||
cycles -= 330;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFRNDINT(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FRNDINT %g ", ST(0));
|
||||
ST(0) = (double)x87_fround(ST(0));
|
||||
if (fplog) pclog("%g\n", ST(0));
|
||||
cycles -= 21;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFSCALE(uint32_t fetchdat)
|
||||
{
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FSCALE\n");
|
||||
temp64 = (int64_t)ST(1);
|
||||
ST(0) = ST(0) * pow(2.0, (double)temp64);
|
||||
cycles -= 30;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFSIN(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FSIN\n");
|
||||
ST(0) = sin(ST(0));
|
||||
npxs &= ~C2;
|
||||
cycles -= 300;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opFCOS(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
pc++;
|
||||
if (fplog) pclog("FCOS\n");
|
||||
ST(0) = cos(ST(0));
|
||||
npxs &= ~C2;
|
||||
cycles -= 300;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void FLDENV()
|
||||
{
|
||||
if (fplog) pclog("FLDENV %08X:%08X\n", easeg, eaaddr);
|
||||
switch ((cr0 & 1) | (op32 & 0x100))
|
||||
{
|
||||
case 0x000: /*16-bit real mode*/
|
||||
case 0x001: /*16-bit protected mode*/
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
npxs = readmemw(easeg, eaaddr+2);
|
||||
tag = readmemw(easeg, eaaddr+4);
|
||||
TOP = (npxs >> 11) & 7;
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
npxs = readmemw(easeg, eaaddr+4);
|
||||
tag = readmemw(easeg, eaaddr+8);
|
||||
TOP = (npxs >> 11) & 7;
|
||||
break;
|
||||
}
|
||||
cycles -= (cr0 & 1) ? 34 : 44;
|
||||
}
|
||||
|
||||
static int opFLDENV_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
FLDENV();
|
||||
return abrt;
|
||||
}
|
||||
static int opFLDENV_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
FLDENV();
|
||||
return abrt;
|
||||
}
|
||||
|
||||
static int opFLDCW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t tempw;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, eaaddr);
|
||||
tempw = geteaw();
|
||||
if (abrt) return 1;
|
||||
npxc = tempw;
|
||||
cycles -= 4;
|
||||
return 0;
|
||||
}
|
||||
static int opFLDCW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t tempw;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, eaaddr);
|
||||
tempw = geteaw();
|
||||
if (abrt) return 1;
|
||||
npxc = tempw;
|
||||
cycles -= 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void FSTENV()
|
||||
{
|
||||
if (fplog) pclog("FSTENV %08X:%08X\n", easeg, eaaddr);
|
||||
switch ((cr0 & 1) | (op32 & 0x100))
|
||||
{
|
||||
case 0x000: /*16-bit real mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememw(easeg,eaaddr+4,tag);
|
||||
writememw(easeg,eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,eaaddr+10,x87_op_off);
|
||||
break;
|
||||
case 0x001: /*16-bit protected mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememw(easeg,eaaddr+4,tag);
|
||||
writememw(easeg,eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,eaaddr+8,x87_pc_seg);
|
||||
writememw(easeg,eaaddr+10,x87_op_off);
|
||||
writememw(easeg,eaaddr+12,x87_op_seg);
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+4,npxs);
|
||||
writememw(easeg,eaaddr+8,tag);
|
||||
writememw(easeg,eaaddr+12,x87_pc_off);
|
||||
writememw(easeg,eaaddr+20,x87_op_off);
|
||||
writememl(easeg,eaaddr+24,(x87_op_off>>16)<<12);
|
||||
break;
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+4,npxs);
|
||||
writememw(easeg,eaaddr+8,tag);
|
||||
writememl(easeg,eaaddr+12,x87_pc_off);
|
||||
writememl(easeg,eaaddr+16,x87_pc_seg);
|
||||
writememl(easeg,eaaddr+20,x87_op_off);
|
||||
writememl(easeg,eaaddr+24,x87_op_seg);
|
||||
break;
|
||||
}
|
||||
cycles -= (cr0 & 1) ? 56 : 67;
|
||||
}
|
||||
|
||||
static int opFSTENV_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
FSTENV();
|
||||
return abrt;
|
||||
}
|
||||
static int opFSTENV_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
FSTENV();
|
||||
return abrt;
|
||||
}
|
||||
|
||||
static int opFSTCW_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, eaaddr);
|
||||
seteaw(npxc);
|
||||
cycles -= 3;
|
||||
return abrt;
|
||||
}
|
||||
static int opFSTCW_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, eaaddr);
|
||||
seteaw(npxc);
|
||||
cycles -= 3;
|
||||
return abrt;
|
||||
}
|
||||
Loading…
Reference in a new issue