First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions. Backend generation implemented for x86, x86-64, ARM and ARM64.
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SarahW
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46 changed files with 4134 additions and 17767 deletions
314
src/codegen_backend_arm_uops.c
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314
src/codegen_backend_arm_uops.c
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#ifdef __ARM_EABI__
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#include "ibm.h"
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#include "codegen.h"
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#include "codegen_backend.h"
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#include "codegen_backend_arm_defs.h"
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#include "codegen_ir_defs.h"
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static inline void codegen_addlong(codeblock_t *block, uint32_t val)
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{
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*(uint32_t *)&block->data[block_pos] = val;
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block_pos += 4;
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if (block_pos >= BLOCK_MAX)
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{
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fatal("codegen_addlong over! %i\n", block_pos);
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CPU_BLOCK_END();
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}
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}
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#define Rm(x) (x)
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#define Rd(x) ((x) << 12)
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#define Rn(x) ((x) << 16)
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#define DATA_OFFSET_UP (1 << 23)
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#define DATA_OFFSET_DOWN (0 << 23)
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#define COND_SHIFT 28
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#define COND_NE (0x1 << COND_SHIFT)
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#define COND_AL (0xe << COND_SHIFT)
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#define OPCODE_SHIFT 20
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#define OPCODE_ADD_IMM (0x28 << OPCODE_SHIFT)
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#define OPCODE_B (0xa0 << OPCODE_SHIFT)
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#define OPCODE_LDMIA_WB (0x8b << OPCODE_SHIFT)
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#define OPCODE_LDR_IMM (0x51 << OPCODE_SHIFT)
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#define OPCODE_MOV_IMM (0x3a << OPCODE_SHIFT)
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#define OPCODE_MOV_REG (0x1a << OPCODE_SHIFT)
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#define OPCODE_STMDB_WB (0x92 << OPCODE_SHIFT)
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#define OPCODE_STR_IMM (0x50 << OPCODE_SHIFT)
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#define OPCODE_STRB_IMM (0x54 << OPCODE_SHIFT)
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#define OPCODE_SUB_IMM (0x24 << OPCODE_SHIFT)
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#define OPCODE_TST_REG (0x11 << OPCODE_SHIFT)
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#define OPCODE_BLX 0xe12fff30
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#define B_OFFSET(x) (((x) >> 2) & 0xffffff)
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static int literal_offset = 0;
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void codegen_reset_literal_pool(codeblock_t *block)
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{
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literal_offset = 0;
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}
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int add_literal(codeblock_t *block, uint32_t data)
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{
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if (literal_offset >= 4096)
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fatal("add_literal - literal pool full\n");
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*(uint32_t *)&block->data[ARM_LITERAL_POOL_OFFSET + literal_offset] = data;
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literal_offset += 4;
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return literal_offset - 4;
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}
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static inline uint32_t arm_data_offset(int offset)
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{
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if (offset < -0xffc || offset > 0xffc)
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fatal("arm_data_offset out of range - %i\n", offset);
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if (offset >= 0)
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return offset | DATA_OFFSET_UP;
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return (-offset) | DATA_OFFSET_DOWN;
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}
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static inline int get_arm_imm(uint32_t imm_data, uint32_t *arm_imm)
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{
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int shift = 0;
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//pclog("get_arm_imm - imm_data=%08x\n", imm_data);
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if (!(imm_data & 0xffff))
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{
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shift += 16;
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imm_data >>= 16;
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}
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if (!(imm_data & 0xff))
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{
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shift += 8;
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imm_data >>= 8;
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}
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if (!(imm_data & 0xf))
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{
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shift += 4;
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imm_data >>= 4;
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}
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if (!(imm_data & 0x3))
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{
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shift += 2;
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imm_data >>= 2;
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}
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if (imm_data > 0xff) /*Note - should handle rotation round the word*/
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return 0;
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//pclog(" imm_data=%02x shift=%i\n", imm_data, shift);
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*arm_imm = imm_data | ((((32 - shift) >> 1) & 15) << 8);
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return 1;
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}
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static inline int in_range(void *addr, void *base)
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{
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int diff = (uintptr_t)addr - (uintptr_t)base;
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if (diff < -4095 || diff > 4095)
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return 0;
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return 1;
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}
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void host_arm_ADD_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if (!get_arm_imm(imm, &arm_imm))
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fatal("host_arm_ADD_IMM !check_arm_imm %08x\n", imm);
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codegen_addlong(block, COND_AL | OPCODE_ADD_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
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}
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void host_arm_BLX(codeblock_t *block, int addr_reg)
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{
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codegen_addlong(block, OPCODE_BLX | Rm(addr_reg));
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}
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void host_arm_BNE(codeblock_t *block, uintptr_t dest_addr)
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{
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uint32_t offset = (dest_addr - (uintptr_t)&block->data[block_pos]) - 8;
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if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000)
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fatal("host_arm_BNE - out of range %08x %i\n", offset, offset);
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codegen_addlong(block, COND_NE | OPCODE_B | B_OFFSET(offset));
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}
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void host_arm_LDMIA_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask)
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{
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codegen_addlong(block, COND_AL | OPCODE_LDMIA_WB | Rn(addr_reg) | reg_mask);
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}
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void host_arm_LDR_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
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{
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codegen_addlong(block, COND_AL | OPCODE_LDR_IMM | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
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}
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void host_arm_MOV_IMM(codeblock_t *block, int dst_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if (!get_arm_imm(imm, &arm_imm))
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fatal("host_arm_MOV_IMM !check_arm_imm %08x\n", imm);
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codegen_addlong(block, COND_AL | OPCODE_MOV_IMM | Rd(dst_reg) | arm_imm);
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}
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void host_arm_MOV_REG(codeblock_t *block, int dst_reg, int src_reg)
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{
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codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg));
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}
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void host_arm_STMDB_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask)
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{
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codegen_addlong(block, COND_AL | OPCODE_STMDB_WB | Rn(addr_reg) | reg_mask);
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}
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void host_arm_STR_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset)
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{
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codegen_addlong(block, COND_AL | OPCODE_STR_IMM | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
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}
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void host_arm_STRB_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset)
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{
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codegen_addlong(block, COND_AL | OPCODE_STRB_IMM | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
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}
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void host_arm_SUB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if (!get_arm_imm(imm, &arm_imm))
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fatal("host_arm_SUB_IMM !check_arm_imm %08x\n", imm);
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codegen_addlong(block, COND_AL | OPCODE_SUB_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
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}
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void host_arm_TST_REG(codeblock_t *block, int src_reg1, int src_reg2)
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{
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codegen_addlong(block, COND_AL | OPCODE_TST_REG | Rn(src_reg1) | Rm(src_reg2));
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}
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void host_arm_call(codeblock_t *block, void *dst_addr)
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{
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int offset = add_literal(block, (uintptr_t)dst_addr);
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host_arm_LDR_IMM(block, REG_R3, REG_LITERAL, offset);
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host_arm_BLX(block, REG_R3);
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}
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void host_arm_nop(codeblock_t *block)
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{
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host_arm_MOV_REG(block, REG_R0, REG_R0);
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}
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static int codegen_CALL_INSTRUCTION_FUNC(codeblock_t *block, uop_t *uop)
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{
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host_arm_call(block, uop->p);
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host_arm_TST_REG(block, REG_R0, REG_R0);
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host_arm_BNE(block, (uintptr_t)&block->data[BLOCK_EXIT_OFFSET]);
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
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{
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uint32_t arm_imm;
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if (get_arm_imm(uop->imm_data, &arm_imm))
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host_arm_MOV_IMM(block, REG_ARG0, uop->imm_data);
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else
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{
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int offset = add_literal(block, uop->imm_data);
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host_arm_LDR_IMM(block, REG_ARG0, REG_LITERAL, offset);
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}
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG1_IMM(codeblock_t *block, uop_t *uop)
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{
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uint32_t arm_imm;
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if (get_arm_imm(uop->imm_data, &arm_imm))
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host_arm_MOV_IMM(block, REG_ARG1, uop->imm_data);
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else
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{
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int offset = add_literal(block, uop->imm_data);
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host_arm_LDR_IMM(block, REG_ARG1, REG_LITERAL, offset);
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}
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG2_IMM(codeblock_t *block, uop_t *uop)
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{
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uint32_t arm_imm;
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if (get_arm_imm(uop->imm_data, &arm_imm))
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host_arm_MOV_IMM(block, REG_ARG2, uop->imm_data);
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else
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{
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int offset = add_literal(block, uop->imm_data);
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host_arm_LDR_IMM(block, REG_ARG2, REG_LITERAL, offset);
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}
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG3_IMM(codeblock_t *block, uop_t *uop)
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{
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uint32_t arm_imm;
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if (get_arm_imm(uop->imm_data, &arm_imm))
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host_arm_MOV_IMM(block, REG_ARG3, uop->imm_data);
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else
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{
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int offset = add_literal(block, uop->imm_data);
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host_arm_LDR_IMM(block, REG_ARG3, REG_LITERAL, offset);
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}
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return 0;
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}
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static int codegen_STORE_PTR_IMM(codeblock_t *block, uop_t *uop)
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{
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uint32_t arm_imm;
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if (get_arm_imm(uop->imm_data, &arm_imm))
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host_arm_MOV_IMM(block, REG_R0, uop->imm_data);
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else
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{
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int offset = add_literal(block, uop->imm_data);
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host_arm_LDR_IMM(block, REG_R0, REG_LITERAL, offset);
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}
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if (in_range(uop->p, &cpu_state))
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host_arm_STR_IMM(block, REG_R0, REG_CPUSTATE, (uintptr_t)uop->p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_STORE_PTR_IMM - not in range\n");
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return 0;
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}
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static int codegen_STORE_PTR_IMM_8(codeblock_t *block, uop_t *uop)
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{
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host_arm_MOV_IMM(block, REG_R0, uop->imm_data);
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if (in_range(uop->p, &cpu_state))
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host_arm_STRB_IMM(block, REG_R0, REG_CPUSTATE, (uintptr_t)uop->p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_STORE_PTR_IMM - not in range\n");
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return 0;
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}
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const uOpFn uop_handlers[UOP_MAX] =
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{
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[UOP_CALL_INSTRUCTION_FUNC & UOP_MASK] = codegen_CALL_INSTRUCTION_FUNC,
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[UOP_LOAD_FUNC_ARG_0_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG0_IMM,
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[UOP_LOAD_FUNC_ARG_1_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG1_IMM,
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[UOP_LOAD_FUNC_ARG_2_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG2_IMM,
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[UOP_LOAD_FUNC_ARG_3_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG3_IMM,
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[UOP_STORE_P_IMM & UOP_MASK] = codegen_STORE_PTR_IMM,
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[UOP_STORE_P_IMM_8 & UOP_MASK] = codegen_STORE_PTR_IMM_8
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};
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#endif
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