First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions. Backend generation implemented for x86, x86-64, ARM and ARM64.
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SarahW
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46 changed files with 4134 additions and 17767 deletions
300
src/codegen_backend_arm64_uops.c
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300
src/codegen_backend_arm64_uops.c
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#ifdef __aarch64__
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#include "ibm.h"
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#include "codegen.h"
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#include "codegen_backend.h"
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#include "codegen_backend_arm64_defs.h"
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#include "codegen_ir_defs.h"
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static inline void codegen_addlong(codeblock_t *block, uint32_t val)
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{
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*(uint32_t *)&block->data[block_pos] = val;
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block_pos += 4;
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if (block_pos >= BLOCK_MAX)
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{
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fatal("codegen_addlong over! %i\n", block_pos);
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CPU_BLOCK_END();
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}
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}
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#define Rt(x) (x)
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#define Rd(x) (x)
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#define Rn(x) ((x) << 5)
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#define Rt2(x) ((x) << 10)
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#define DATA_OFFSET_UP (1 << 23)
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#define DATA_OFFSET_DOWN (0 << 23)
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#define COND_SHIFT 28
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#define COND_NE (0x1 << COND_SHIFT)
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#define COND_AL (0xe << COND_SHIFT)
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#define OPCODE_SHIFT 24
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#define OPCODE_CBNZ (0xb5 << OPCODE_SHIFT)
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#define OPCODE_LDR_LITERAL_W (0x18 << OPCODE_SHIFT)
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#define OPCODE_LDR_LITERAL_X (0x58 << OPCODE_SHIFT)
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#define OPCODE_MOVK_W (0x0e5 << 23)
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#define OPCODE_MOVZ_W (0x0a5 << 23)
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#define OPCODE_LDP_POSTIDX_X (0x2a3 << 22)
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#define OPCODE_STP_PREIDX_X (0x2a6 << 22)
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#define OPCODE_STR_IMM_W (0x2e4 << 22)
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#define OPCODE_STRB_IMM (0x0e4 << 22)
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#define OPCODE_BLR (0xd63f0000)
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#define OPCODE_NOP (0xd503201f)
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#define OPCODE_RET (0xd65f0000)
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#define MOV_WIDE_HW(hw) (hw << 21)
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#define IMM7_X(imm_data) (((imm_data >> 3) & 0x7f) << 15)
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#define IMM16(imm_data) (imm_data << 5)
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#define OFFSET19(offset) (((offset >> 2) << 5) & 0x00ffffe0)
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#define OFFSET12_B(offset) (offset << 10)
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#define OFFSET12_W(offset) ((offset >> 2) << 10)
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static int literal_offset = 0;
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void codegen_reset_literal_pool(codeblock_t *block)
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{
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literal_offset = 0;
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}
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/*Returns true if offset fits into 19 bits*/
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static int offset_is_19bit(int offset)
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{
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if (offset >= (1 << (18+2)))
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return 0;
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if (offset < -(1 << (18+2)))
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return 0;
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return 1;
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}
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#define in_range7_x(offset) (((offset) >= -0x200) && ((offset) < (0x200)) && !((offset) & 7))
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#define in_range12_b(offset) (((offset) >= 0) && ((offset) < 0x1000))
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#define in_range12_w(offset) (((offset) >= 0) && ((offset) < 0x4000) && !((offset) & 3))
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int add_literal(codeblock_t *block, uint32_t data)
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{
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if (literal_offset >= 4096)
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fatal("add_literal - literal pool full\n");
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*(uint32_t *)&block->data[ARM_LITERAL_POOL_OFFSET + literal_offset] = data;
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literal_offset += 4;
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return literal_offset - 4;
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}
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int add_literal_q(codeblock_t *block, uint64_t data)
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{
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if (literal_offset & 4)
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literal_offset += 4;
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if (literal_offset >= 4096-4)
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fatal("add_literal - literal pool full\n");
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*(uint64_t *)&block->data[ARM_LITERAL_POOL_OFFSET + literal_offset] = data;
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literal_offset += 8;
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return literal_offset - 8;
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}
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static inline int imm_is_imm16(uint32_t imm_data)
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{
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if (!(imm_data & 0xffff0000) || !(imm_data & 0x0000ffff))
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return 1;
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return 0;
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}
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void host_arm64_BLR(codeblock_t *block, int addr_reg)
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{
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codegen_addlong(block, OPCODE_BLR | Rn(addr_reg));
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}
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void host_arm64_CBNZ(codeblock_t *block, int reg, uintptr_t dest)
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{
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int offset = dest - (uintptr_t)&block->data[block_pos];
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if (!offset_is_19bit(offset))
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fatal("host_arm64_CBNZ - offset out of range %x\n", offset);
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codegen_addlong(block, OPCODE_CBNZ | OFFSET19(offset) | Rt(reg));
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}
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void host_arm64_LDP_POSTIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset)
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{
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if (!in_range7_x(offset))
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fatal("host_arm64_LDP_POSTIDX out of range7 %i\n", offset);
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codegen_addlong(block, OPCODE_LDP_POSTIDX_X | IMM7_X(offset) | Rn(base_reg) | Rt(src_reg1) | Rt2(src_reg2));
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}
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void host_arm64_LDR_LITERAL_W(codeblock_t *block, int dest_reg, int literal_offset)
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{
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int offset = (ARM_LITERAL_POOL_OFFSET + literal_offset) - block_pos;
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if (!offset_is_19bit(offset))
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fatal("host_arm64_CBNZ - offset out of range %x\n", offset);
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codegen_addlong(block, OPCODE_LDR_LITERAL_W | OFFSET19(offset) | Rt(dest_reg));
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}
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void host_arm64_LDR_LITERAL_X(codeblock_t *block, int dest_reg, int literal_offset)
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{
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int offset = (ARM_LITERAL_POOL_OFFSET + literal_offset) - block_pos;
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if (!offset_is_19bit(offset))
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fatal("host_arm64_CBNZ - offset out of range %x\n", offset);
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codegen_addlong(block, OPCODE_LDR_LITERAL_X | OFFSET19(offset) | Rt(dest_reg));
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}
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void host_arm64_MOVZ_IMM(codeblock_t *block, int reg, uint32_t imm_data)
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{
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int hw;
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if (!imm_is_imm16(imm_data))
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fatal("MOVZ_IMM - imm not representable %08x\n", imm_data);
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hw = (imm_data & 0xffff0000) ? 1 : 0;
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if (hw)
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imm_data >>= 16;
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codegen_addlong(block, OPCODE_MOVZ_W | MOV_WIDE_HW(hw) | IMM16(imm_data) | Rd(reg));
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}
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void host_arm64_MOVK_IMM(codeblock_t *block, int reg, uint32_t imm_data)
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{
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int hw;
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if (!imm_is_imm16(imm_data))
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fatal("MOVK_IMM - imm not representable %08x\n", imm_data);
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hw = (imm_data & 0xffff0000) ? 1 : 0;
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if (hw)
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imm_data >>= 16;
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codegen_addlong(block, OPCODE_MOVK_W | MOV_WIDE_HW(hw) | IMM16(imm_data) | Rd(reg));
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}
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void host_arm64_NOP(codeblock_t *block)
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{
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codegen_addlong(block, OPCODE_NOP);
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}
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void host_arm64_RET(codeblock_t *block, int reg)
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{
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codegen_addlong(block, OPCODE_RET | Rn(reg));
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}
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void host_arm64_STP_PREIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset)
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{
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if (!in_range7_x(offset))
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fatal("host_arm64_STP_PREIDX out of range7 %i\n", offset);
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codegen_addlong(block, OPCODE_STP_PREIDX_X | IMM7_X(offset) | Rn(base_reg) | Rt(src_reg1) | Rt2(src_reg2));
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}
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void host_arm64_STR_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset)
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{
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if (!in_range12_w(offset))
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fatal("host_arm64_STR_IMM_W out of range12 %i\n", offset);
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codegen_addlong(block, OPCODE_STR_IMM_W | OFFSET12_W(offset) | Rn(base_reg) | Rt(dest_reg));
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}
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void host_arm64_STRB_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset)
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{
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if (!in_range12_b(offset))
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fatal("host_arm64_STRB_IMM out of range12 %i\n", offset);
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codegen_addlong(block, OPCODE_STRB_IMM | OFFSET12_B(offset) | Rn(base_reg) | Rt(dest_reg));
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}
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void host_arm64_call(codeblock_t *block, void *dst_addr)
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{
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int offset = add_literal_q(block, (uintptr_t)dst_addr);
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host_arm64_LDR_LITERAL_X(block, REG_X16, offset);
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host_arm64_BLR(block, REG_X16);
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}
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void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data)
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{
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if (imm_is_imm16(imm_data))
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host_arm64_MOVZ_IMM(block, reg, imm_data);
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else
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{
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host_arm64_MOVZ_IMM(block, reg, imm_data & 0xffff);
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host_arm64_MOVK_IMM(block, reg, imm_data & 0xffff0000);
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}
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}
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static int codegen_CALL_INSTRUCTION_FUNC(codeblock_t *block, uop_t *uop)
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{
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host_arm64_call(block, uop->p);
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host_arm64_CBNZ(block, REG_X0, (uintptr_t)&block->data[BLOCK_EXIT_OFFSET]);
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
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{
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host_arm64_mov_imm(block, REG_ARG0, uop->imm_data);
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG1_IMM(codeblock_t *block, uop_t *uop)
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{
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host_arm64_mov_imm(block, REG_ARG1, uop->imm_data);
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG2_IMM(codeblock_t *block, uop_t *uop)
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{
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host_arm64_mov_imm(block, REG_ARG2, uop->imm_data);
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return 0;
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}
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static int codegen_LOAD_FUNC_ARG3_IMM(codeblock_t *block, uop_t *uop)
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{
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host_arm64_mov_imm(block, REG_ARG3, uop->imm_data);
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return 0;
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}
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static int codegen_STORE_PTR_IMM(codeblock_t *block, uop_t *uop)
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{
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host_arm64_mov_imm(block, REG_W16, uop->imm_data);
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if (in_range12_w((uintptr_t)uop->p - (uintptr_t)&cpu_state))
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host_arm64_STR_IMM_W(block, REG_W16, REG_CPUSTATE, (uintptr_t)uop->p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_STORE_PTR_IMM - not in range\n");
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return 0;
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}
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static int codegen_STORE_PTR_IMM_8(codeblock_t *block, uop_t *uop)
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{
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host_arm64_mov_imm(block, REG_W16, uop->imm_data);
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if (in_range12_b((uintptr_t)uop->p - (uintptr_t)&cpu_state))
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host_arm64_STRB_IMM(block, REG_W16, REG_CPUSTATE, (uintptr_t)uop->p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_STORE_PTR_IMM - not in range\n");
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return 0;
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}
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const uOpFn uop_handlers[UOP_MAX] =
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{
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[UOP_CALL_INSTRUCTION_FUNC & UOP_MASK] = codegen_CALL_INSTRUCTION_FUNC,
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[UOP_LOAD_FUNC_ARG_0_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG0_IMM,
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[UOP_LOAD_FUNC_ARG_1_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG1_IMM,
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[UOP_LOAD_FUNC_ARG_2_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG2_IMM,
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[UOP_LOAD_FUNC_ARG_3_IMM & UOP_MASK] = codegen_LOAD_FUNC_ARG3_IMM,
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[UOP_STORE_P_IMM & UOP_MASK] = codegen_STORE_PTR_IMM,
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[UOP_STORE_P_IMM_8 & UOP_MASK] = codegen_STORE_PTR_IMM_8
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};
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#endif
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