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<meta name="vsisbn" content="1576101746" />
<meta name="vstitle" content="Michael Abrash's Graphics Programming Black Book, Special Edition" />
<meta name="vsauthor" content="Michael Abrash" />
<meta name="vspublisher" content="The Coriolis Group" />
<meta name="vspubdate" content="07/01/97" />
<meta name="vscategory" content="Web and Software Development: Game Development,Web and Software Development: Graphics and Multimedia Development" />
<title>Michael Abrash's Graphics Programming Black Book Special Edition: Index</title>
<meta name="pages" content="1299-1342" />
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<h2 id="Heading1">Index</h2>
<dl>
<dd><big><b>Numbers</b></big></dd>
<dd>
1/z sorting
<dl>
<dd>abutting span sorting, 1229-1230</dd>
<dd><b>AddPolygonEdges</b> function, <b>1232-1233,</b> 1238</dd>
<dd>vs. BSP-order sorting, 1226-1227</dd>
<dd>calculating 1/z value, 1220-1222</dd>
<dd><b>ClearEdgeLists</b> function, <b>1236-1237</b></dd>
<dd><b>DrawSpans</b> function, <b>1236</b></dd>
<dd>independent span sorting, 1230, <b>1231-1238,</b> 1239-1241</dd>
<dd>intersecting span sorting, 1228-1229</dd>
<dd><b>PolyFacesViewer</b> function, <b>1232</b></dd>
<dd>reliability, 1227</dd>
<dd><b>ScanEdges</b> function, <b>1234-1236,</b> 1238-1239</dd>
<dd><b>UpdateWorld</b> function, 1237-1238</dd>
</dl>
</dd>
<dd>
3-D animation
<dl>
<dd><i>See also</i> Hidden surface removal; 3-D drawing; 3-D polygon rotation demo program; X-Sharp 3-D animation package.</dd>
<dd>
demo programs
<dl>
<dd>solid cube rotation program, <b>957-961,</b> 962-963, <b>964-966,</b> 967</dd>
<dd>3-D polygon rotation program, 939, <b>940-945,</b> 948-949</dd>
<dd>12-cube rotation program, 972, <b>973-984,</b> 985-987</dd>
</dl>
</dd>
<dd>depth sorting, 1000, <b>1001-1002</b></dd>
<dd>
rotation
<dl>
<dd><b>ConcatXforms</b> function, <b>944</b></dd>
<dd>matrix representation, 938-939</dd>
<dd>multiple axes of rotation, 948</dd>
<dd><b>XformVec</b> function, <b>943</b></dd>
</dl>
</dd>
<dd>rounding vs. truncation, 1002-1003</dd>
<dd>translation of objects, 937-938</dd>
</dl>
</dd>
<dd>
3-D clipping
<dl>
<dd>arithmetic imprecision, handling, 1240</dd>
<dd>line segments, clipping to planes, 1195-1197</dd>
<dd>overview, 1195</dd>
<dd>
polygon clipping
<dl>
<dd><b>BackRotateVector</b> function, <b>1203</b></dd>
<dd>clipping to frustum, 1200, <b>1201-1206,</b> 1206-1207</dd>
<dd><b>ClipToFrustum</b> function, <b>1204</b></dd>
<dd><b>ClipToPlane</b> function, <b>1199</b></dd>
<dd>optimization, 1207</dd>
<dd>overview, 1197-1200</dd>
<dd><b>PolyFacesViewer</b> function, <b>1203</b></dd>
<dd><b>ProjectPolygon</b> function, <b>1201</b></dd>
<dd><b>SetUpFrustum</b> function, <b>1204</b></dd>
<dd><b>SetWorldspace</b> function, <b>1204</b></dd>
<dd><b>TransformPoint</b> function, <b>1203</b></dd>
<dd><b>TransformPolygon</b> function, <b>1203</b></dd>
<dd><b>UpdateWorld</b> function, <b>1205</b></dd>
<dd>viewspace clipping, 1207</dd>
<dd><b>ZSortObjects</b> function, <b>1201</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd>
3-D drawing
<dl>
<dd><i>See also</i> BSP (Binary Space Partitioning) trees; Hidden surface removal; Polygons, filling; Shading; 3-D animation.</dd>
<dd>
backface removal
<dl>
<dd>BSP tree rendering, 1160-1161</dd>
<dd>calculations, 955-957</dd>
<dd>motivation for, 954-955</dd>
<dd>and sign of dot product, 1140</dd>
<dd>solid cube rotation demo program, <b>957-961,</b> 962-963, <b>964-966,</b> 967</dd>
</dl>
</dd>
<dd>background surfaces, 1240</dd>
<dd>draw-buffers, and beam trees, 1187</dd>
<dd>and dynamic objects, 1100-1101</dd>
<dd>Gouraud shading, 1246-1250</dd>
<dd>
lighting
<dl>
<dd>Gouraud shading, 1246-1250</dd>
<dd>overlapping lights, 1247</dd>
<dd>perspective correctness, 1248-1250</dd>
<dd>rotational variance, 1249</dd>
<dd>surface-based lighting, 1250-1256, 1260-1262</dd>
<dd>viewing variance, 1249</dd>
</dl>
</dd>
<dd>moving models in 3-D drawings, 1212-1222</dd>
<dd>painter&rsquo;s algorithm, 1099, 1104-1105</dd>
<dd>perspective correctness problem, 1248-1250</dd>
<dd>portals, and beam trees, 1188</dd>
<dd>
projection
<dl>
<dd>dot products, 1141-1142</dd>
<dd>overview, 937, 948</dd>
</dl>
</dd>
<dd>raycast, subdividing, and beam trees, 1187</dd>
<dd>reference materials, 934-935</dd>
<dd>
rendering BSP trees
<dl>
<dd>clipping, 1158-1159</dd>
<dd><b>ClipWalls</b> function, <b>1152-1155,</b> 1158-1159</dd>
<dd><b>DrawWallsBackToFront</b> function, <b>1155-1156,</b> 1160-1161</dd>
<dd>overview, 1149</dd>
<dd>reference materials, 1157</dd>
<dd><b>TransformVertices</b> function, <b>1151-1152,</b> 1158</dd>
<dd><b>UpdateViewPos</b> function, <b>1151,</b> 1157</dd>
<dd><b>UpdateWorld</b> function, <b>1156-1157,</b> 1157</dd>
<dd>viewspace, transformation of objects to, 1158</dd>
<dd>wall orientation testing, 1160-1161</dd>
<dd><b>WallFacingViewer</b> function, <b>1150-1151,</b> 1161</dd>
</dl>
</dd>
<dd>span-based drawing, and beam trees, 1187</dd>
<dd>transformation of objects, 935-936</dd>
<dd>
triangle model drawing
<dl>
<dd>fast triangle drawing, 1263-1265</dd>
<dd>overview, 1262-1263</dd>
<dd>precision, 1265</dd>
<dd>subdivision rasterization, 1266-1267, <b>1267-1270</b></dd>
</dl>
</dd>
<dd>vertex-free surfaces, and beam trees, 1187</dd>
<dd>visibility determination, 1099-1106</dd>
<dd>
visible surface determination (VSD)
<dl>
<dd>beam trees, 1185-1189</dd>
<dd>culling to frustum, 1181-1184</dd>
<dd>overdraw problem, 1184-1185</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
3-D engine, Quake
<dl>
<dd>BSP trees, 1276-1277</dd>
<dd>lighting, 1282-1283</dd>
<dd>model overview, 1276-1277</dd>
<dd>portals, 1279-1280</dd>
<dd>potentially visible set (PVS), 1278-1279</dd>
<dd>rasterization, 1282</dd>
<dd>world, drawing, 1280-1281</dd>
</dl>
</dd>
<dd>
3-D math
<dl>
<dd>cross products, 1139-1140</dd>
<dd>
dot products
<dl>
<dd>calculating, 1135-1137</dd>
<dd>calculating light intensity, 1137</dd>
<dd>projection, 1141-1142</dd>
<dd>rotation, 1143-1144</dd>
<dd>sign of, 1140-1141</dd>
<dd>of unit vectors, 1136</dd>
<dd>of vectors, 1135-1136</dd>
</dl>
</dd>
<dd>
matrix math
<dl>
<dd>assembly routines, 992, <b>996-999</b></dd>
<dd>C-language implementations, <b>974-976</b></dd>
<dd>normal vectors, calculating, 955-956</dd>
<dd>rotation of 3-D objects, 938-939, <b>943-944,</b> 948</dd>
<dd>transformation, optimized, 1172-1173, <b>1173-1174</b></dd>
</dl>
</dd>
<dd>vector length, 1135</dd>
</dl>
</dd>
<dd>
3-D polygon rotation demo program
<dl>
<dd>matrix multiplication functions, <b>943-944,</b> 948</dd>
<dd>overview, 939</dd>
<dd>performance, 949</dd>
<dd>polygon filling with clipping support, <b>940-943</b></dd>
<dd>transformation and projection, <b>944-945,</b> 948</dd>
</dl>
</dd>
<dd>
3-D solid cube rotation demo program
<dl>
<dd>basic implementation, <b>957-961,</b> 962-963</dd>
<dd>incremental transformations, <b>964-966</b></dd>
<dd>object representation, 967</dd>
</dl>
</dd>
<dd>
8-bit bus cycle-eater
<dl>
<dd>286 and 386 processors, 210</dd>
<dd>
8088 processor
<dl>
<dd>effects on performance, 82</dd>
<dd>optimizing for, 83-85</dd>
<dd>overview, 79-82</dd>
<dd>and registers, 85</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
12-cube rotation demo program
<dl>
<dd>limitations of, 986</dd>
<dd>optimizations in, 985-986</dd>
<dd>performance, 986</dd>
<dd>X-Sharp animation package, 972, <b>973-984,</b> 984-985</dd>
</dl>
</dd>
<dd>
16-bit checksum program
<dl>
<dd><i>See also</i> TCP/IP checksum program.</dd>
<dd>assembly implementation, <b>10-12, 17-18</b></dd>
<dd>C language implementation, <b>8-9, 15-16</b></dd>
<dd>overview, 8</dd>
<dd>redesigning, 9</dd>
</dl>
</dd>
<dd>
16-color VGA modes
<dl>
<dd>color paging, 628-629</dd>
<dd>DAC (Digital/Analog Converter), 626-628</dd>
<dd>palette RAM, 626</dd>
</dl>
</dd>
<dd>24-byte hi/lo function, 292-293</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>32-bit division, 181-184, 1008</dd>
<dd>32-bit fixed-point arithmetic, optimizing, 1086-1089, <b>1090-1091,</b> 1092-1093</dd>
<dd>32-bit instructions, optimizing, 1091</dd>
<dd>
32-bit registers
<dl>
<dd><i>See also</i> Registers; VGA registers.</dd>
<dd>adding with <b>LEA,</b> 131</dd>
<dd><b>BSWAP</b> instruction, 252</dd>
<dd>multiplying with <b>LEA,</b> 132-133</dd>
<dd>386 processor, 222</dd>
<dd>time vs. space tradeoff, 187</dd>
<dd>using as two 16-bit registers, 253-254</dd>
</dl>
</dd>
<dd>
256-color modes
<dl>
<dd><i>See also</i> 320x400 256-color mode.</dd>
<dd>DAC settings, 629</dd>
<dd>mapping RGB model to, 1036, <b>1037-1038,</b> 1039</dd>
<dd>resolution, 360x480 256-color mode, 619-620</dd>
</dl>
</dd>
<dd>
286 processor
<dl>
<dd><b>CMP</b> instruction, 161, 306</dd>
<dd>code alignment, 215-218</dd>
<dd>cycle-eaters, 209-210</dd>
<dd>data alignment, 213-215</dd>
<dd>data transfer rates, 212</dd>
<dd>display adapter cycle-eater, 219-221</dd>
<dd>display memory wait states, 220</dd>
<dd>DRAM refresh cycle-eater, 219</dd>
<dd>effective address calculations, 129, 223-225</dd>
<dd>instruction fetching, 215-218</dd>
<dd><b>LEA</b> vs. <b>ADD</b> instructions, 130</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>memory access, performance, 223-225</dd>
<dd>new features, 221</dd>
<dd><b>POPF</b> instruction, and interrupts, 226</dd>
<dd>protected mode, 208-209</dd>
<dd>stack pointer alignment, 218-219</dd>
<dd>system wait states, 210-212</dd>
</dl>
</dd>
<dd>320x240 256-color mode. <i>See</i> Mode X.</dd>
<dd>
320x400 256-color mode
<dl>
<dd>advantages of, 590-591</dd>
<dd>display memory organization, 591-593</dd>
<dd>line drawing, 600</dd>
<dd>page flipping demo program, <b>600-605</b></dd>
<dd>performance, 599-600</dd>
<dd>pixel drawing demo program, <b>593-598,</b> 599-600</dd>
</dl>
</dd>
<dd>
360x480 256-color mode
<dl>
<dd>display memory, accessing, 621-622</dd>
<dd><b>Draw360x480Dot</b> subroutine, <b>613-614</b></dd>
<dd>drawing speed, 618</dd>
<dd>horizontal resolution, 620</dd>
<dd>line drawing demo program, <b>615-618,</b> 618-619</dd>
<dd>mode set routine (John Bridges), 609, <b>612,</b> 620-621</dd>
<dd>on VGA clones, 610-611</dd>
<dd><b>Read360x480Dot</b> subroutine, <b>614-615</b></dd>
<dd>256-color resolution, 619-620</dd>
<dd>vertical resolution, 619</dd>
</dl>
</dd>
<dd>386 native mode, 32-bit displacements, 187</dd>
<dd>
386 processor
<dl>
<dd>alignment, stack pointer, 218-219</dd>
<dd><b>CMP</b> instruction, 161, 306</dd>
<dd>cycle-eaters, 209-210</dd>
<dd>data alignment, 213, 218</dd>
<dd>and display adapter cycle-eater, 107</dd>
<dd>display adapter cycle-eater, 219-221</dd>
<dd>doubleword alignment, 218</dd>
<dd>DRAM refresh cycle-eater, 219</dd>
<dd>effective address calculations, 129, 223-225</dd>
<dd><b>LEA</b> instruction, 130-133, 172</dd>
<dd><b>LODSD</b> vs. <b>MOV/LEA</b> sequence, 171</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>memory access, performance, 223-225</dd>
<dd><b>MUL</b> and <b>IMUL</b> instructions, 173-174</dd>
<dd>multiplication operations, increasing speed of, 173-174</dd>
<dd>new instructions and features, 222</dd>
<dd>Pentium code, running on, 411</dd>
<dd>protected mode, 208-209</dd>
<dd>rotation instructions, clock cycles, 185-186</dd>
<dd>system wait states, 210-212</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>32-bit multiply and divide operations, 985</dd>
<dd>using 32-bit register as two 16-bit registers, 253-254</dd>
<dd><b>XCHG</b> vs. <b>MOV</b> instructions, 377, 832</dd>
</dl>
</dd>
<dd>386SX processor, 16-bit bus cycle-eater, 81</dd>
<dd>
486 processor
<dl>
<dd>AX register, setting to absolute value, 172</dd>
<dd>byte registers and lost cycles, 242-245</dd>
<dd>
<b>CMP</b> instruction
<dl>
<dd>operands, order of, 306</dd>
<dd>vs. <b>SCASW,</b> 161</dd>
</dl>
</dd>
<dd>copying bytes between registers, 172</dd>
<dd>and display adapter cycle-eater, 107</dd>
<dd>indexed addressing, 237-238</dd>
<dd>
internal cache
<dl>
<dd>effect on code timing, 246</dd>
<dd>optimization, 236</dd>
</dl>
</dd>
<dd><b>LAHF</b> and <b>SAHF</b> instructions, 148</dd>
<dd><b>LEA</b> instruction, vs. <b>ADD,</b> 131</dd>
<dd><b>LODSB</b> instruction, 304</dd>
<dd><b>LODSD</b> instruction, vs. <b>MOV/LEA</b> sequence, 171</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction, vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd><b>MOV</b> instruction, vs. <b>XCHG,</b> 377</dd>
<dd>n-bit vs. 1-bit shift and rotate instructions, 255-256</dd>
<dd>Pentium code, running on, 411</dd>
<dd>
pipelining
<dl>
<dd>address calculation, 238-240, 250</dd>
<dd>stack addressing, 241-242</dd>
</dl>
</dd>
<dd>rotation instructions, clock cycles, 185-186</dd>
<dd>stack-based variables, 184-184</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>timing code, 245-246</dd>
<dd>using 32-bit register as two 16-bit registers, 253-254</dd>
<dd><b>XCHG</b> instruction, vs. <b>MOV,</b> 377, 832</dd>
</dl>
</dd>
<dd>640x400 mode, mode set routine, <b>852-853</b></dd>
<dd>640x480 mode, page flipping, 836-837</dd>
<dd>8086 processor vs. 8088 processor, 79-81</dd>
<dd>
8088 processor
<dl>
<dd><b>CMP</b> instruction, 161, 306</dd>
<dd>
cycle-eaters
<dl>
<dd>8-bit bus cycle-eater, 79-85</dd>
<dd>display adapter cycle-eater, 101-108</dd>
<dd>DRAM refresh cycle-eater, 95-99</dd>
<dd>overview, 78-79, 80</dd>
<dd>prefetch queue cycle-eater, 86-94</dd>
<dd>wait states, 99-101</dd>
</dl>
</dd>
<dd>display memory access, 220</dd>
<dd>effective address calculation options, 129</dd>
<dd>vs. 8086 processor, 79-81</dd>
<dd><b>LAHF</b> and <b>SAHF</b> instructions, 148</dd>
<dd><b>LEA</b> vs. <b>ADD,</b> 130</dd>
<dd><b>LODSB</b> instruction, 304</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>memory variables, size of, 83-85</dd>
<dd>stack-based variables, placement of, 184-184</dd>
</dl>
</dd>
<dd>
8253 timer chip
<dl>
<dd>and DRAM refresh, 95</dd>
<dd>reference material, 72</dd>
<dd>resetting, 43</dd>
<dd>
system clock inaccuracies
<dl>
<dd>long-period Zen timer, 53, 54</dd>
<dd>Zen timer, 43, 45-46, 48</dd>
</dl>
</dd>
<dd>
timer 0
<dl>
<dd>operation, 44</dd>
<dd>stopping, 54, 65</dd>
</dl>
</dd>
<dd>timer modes, 44, 45</dd>
<dd>timer operation, 43-45</dd>
<dd>undocumented features, 54, 65</dd>
<dd><big><b>A</b></big></dd>
</dl>
</dd>
<dd>Absolute value, setting AX register, 171</dd>
<dd>Abstraction, and optimization, 330-332, 345-346</dd>
<dd>Abutting span sorting, 1229-1230</dd>
<dd>
AC (Attribute Controller), VGA
<dl>
<dd>addressing, 427-428</dd>
<dd>Color Select register, 628-629</dd>
<dd>Index register, 443, 555</dd>
<dd>Mode Control register, 575</dd>
<dd>
Mode register
<dl>
<dd>color paging, 628-629</dd>
<dd>256-color modes, 629</dd>
</dl>
</dd>
<dd>palette RAM registers, setting, 631-632</dd>
<dd>Pel Panning register, 574</dd>
<dd>registers, setting and reading, 583</dd>
<dd>screen blanking demo program, <b>556-557</b></dd>
</dl>
</dd>
<dd>Active edge table (AET), 744</dd>
<dd>Adapters, display. <i>See</i> Display adapter cycle-eater.</dd>
<dd>
<b>ADD</b> instruction
<dl>
<dd>and Carry flag, 147-148</dd>
<dd>vs. <b>INC,</b> 147-148, 219</dd>
<dd>vs. <b>LEA,</b> 130, 170-171</dd>
</dl>
</dd>
<dd><b>AddDirtyRect</b> function, <b>867-869</b></dd>
<dd>Addition, using LEA, 130, 131</dd>
<dd><b>AddObject</b> function, <b>1001-1002</b></dd>
<dd><b>AddPolygonEdges</b> function, <b>1232-1233,</b> 1238</dd>
<dd>Addressable memory, protected mode, 221</dd>
<dd>
Addressing modes
<dl>
<dd>
486 processor
<dl>
<dd>indexed addressing, 237-238</dd>
<dd>32-bit addressing modes, 256-258</dd>
</dl>
</dd>
<dd>386 processor, 130-133, 222</dd>
<dd>VGA, internal indexing, 427-428</dd>
</dl>
</dd>
<dd>
Addressing pipeline penalty
<dl>
<dd><i>See also</i> Pipeline stalls.</dd>
<dd>486 processor, 238-240, 250</dd>
<dd>Pentium processor, 400-403</dd>
</dl>
</dd>
<dd>
<b>AdvanceAET</b> function
<dl>
<dd>complex polygons, <b>748-749</b></dd>
<dd>monotone-vertical polygons, <b>769</b></dd>
</dl>
</dd>
<dd>AET (active edge table), 744</dd>
<dd>
AGIs (Address Generation Interlocks), 400-403
<dl>
<dd><i>See also</i> Addressing pipeline penalty; Pipeline stalls.</dd>
</dl>
</dd>
<dd><i>Algorithms In C</i> (book), 192, 196</dd>
<dd>
Alignment
<dl>
<dd>
Pentium processor
<dl>
<dd>non-alignment penalties, 376</dd>
<dd>TCP/IP checksum program, 409</dd>
</dl>
</dd>
<dd><b>REP STOS</b> instruction, 735</dd>
<dd>386 processor, 218</dd>
<dd>
286 processor
<dl>
<dd>code alignment, 215-218</dd>
<dd>data alignment, 213-215</dd>
<dd>stack pointer alignment, 218-219</dd>
</dl>
</dd>
</dl>
</dd>
<dd>ALU and latch demo program, <b>453-457,</b> 458-460</dd>
<dd>
ALUs (Arithmetic Logic Units), VGA
<dl>
<dd>ALU and latch demo program, <b>453-457,</b> 458-460</dd>
<dd>logical functions, 458</dd>
<dd>operational modes, 458</dd>
<dd>overview, 451-452</dd>
</dl>
</dd>
<dd>Ambient shading, 1023, <b>1025-1027</b></dd>
<dd>
<b>AND</b> instruction, Pentium processor
<dl>
<dd>AGIs (Address Generation Interlocks), 401-402</dd>
<dd>vs. <b>TEST,</b> 377</dd>
</dl>
</dd>
<dd>
Animation
<dl>
<dd><i>See also</i> Animation demo programs; Mode X; 3-D animation.</dd>
<dd>apparent motion, 1064</dd>
<dd>ball animation demo program, <b>431-441</b></dd>
<dd>challenges in, 819-820</dd>
<dd>on PCs, 795-796</dd>
<dd>page flipping, flicker-free animation, 444-446</dd>
<dd>speed, importance of, 1064</dd>
</dl>
</dd>
<dd>
Animation demo programs
<dl>
<dd>Mode X animation, 924-925, <b>925-930</b></dd>
<dd>
page flipping animation
<dl>
<dd>assembly code, <b>825-830</b></dd>
<dd>C code, <b>820-825</b></dd>
<dd>split screen and page flipping, 830-837</dd>
</dl>
</dd>
<dd>
3-D polygon rotation
<dl>
<dd>matrix multiplication functions, <b>943-944,</b> 948</dd>
<dd>overview, 939</dd>
<dd>performance, 949</dd>
<dd>polygon filling with clipping support, <b>940-943</b></dd>
<dd>transformation and projection, <b>944-945,</b> 948</dd>
</dl>
</dd>
<dd>
3-D solid cube rotation demo program
<dl>
<dd>basic implementation, <b>957-961,</b> 962-963</dd>
<dd>incremental transformations, <b>964-966</b></dd>
<dd>object representation, 967</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
Animation techniques
<dl>
<dd>
bit-plane animation
<dl>
<dd>assembly implementation, <b>801-809,</b> 810</dd>
<dd>limitations, 811-813</dd>
<dd>page flipping, 814</dd>
<dd>palette registers, 799-801</dd>
<dd>principles, 796-798</dd>
<dd>shearing, 813</dd>
</dl>
</dd>
<dd>
dirty-rectangle animation
<dl>
<dd>C implementation, <b>847-851, 863-869</b></dd>
<dd>description, 844-845</dd>
<dd>ordering rectangles, 873</dd>
<dd>overlapping rectangles, 872-873</dd>
<dd>vs. page flipping, 846, 862</dd>
<dd>performance, 873</dd>
<dd>system memory buffer size, 851</dd>
<dd>writing to display memory, 856-857</dd>
</dl>
</dd>
<dd>internal animation, 872</dd>
<dd>masked images, 871-872</dd>
</dl>
</dd>
<dd>Antialiasing, Wu&rsquo;s algorithm, 776-779, <b>780-791,</b> 791-792</dd>
<dd>Apparent motion, in animation, 1064</dd>
<dd><b>AppendRotationX</b> function, <b>964, 975</b></dd>
<dd><b>AppendRotationY</b> function, <b>964-965, 975</b></dd>
<dd><b>AppendRotationZ</b> function, <b>965, 976</b></dd>
<dd>Appropriate technology, 775-776</dd>
<dd>Arithmetic flags. <i>See</i> Flags.</dd>
<dd>Arrays, sorting, 180-181</dd>
<dd>Aspect ratio, Mode X, 878</dd>
<dd>
Assemblers
<dl>
<dd>MASM (Microsoft Assembler), 187</dd>
<dd>optimizing assemblers, 71-72</dd>
<dd>TASM (Turbo Assembler), 71-72</dd>
</dl>
</dd>
<dd>
Assembly language optimization
<dl>
<dd><i>See also</i> Clock cycles; Local optimization; Optimization.</dd>
<dd>data, placing limitations on, 274</dd>
<dd>instruction size vs. execution time, 90-92, 93</dd>
<dd>multi-bit rotations, 23-24</dd>
<dd>objectives, 28</dd>
<dd>optimizing instructions, 23-24</dd>
<dd>programmer&rsquo;s responsibilities, 27-29</dd>
<dd>rearranging instructions, 418-419</dd>
<dd>reducing size of code, 416-418</dd>
<dd>stack addressing, 420</dd>
<dd>understanding data, importance of, 122</dd>
</dl>
</dd>
<dd>Assembly language programmers, vs. compilers, 154-155</dd>
<dd>Assembly language, transformation issues, 25-26</dd>
<dd>
AT computer
<dl>
<dd>display adapter cycle-eater, 107</dd>
<dd>286 processor, data transfer rates, 212</dd>
</dl>
</dd>
<dd>Attribute Controller, VGA. <i>See</i> AC (Attribute Controller), VGA.</dd>
<dd>Automatic variables, 184-185</dd>
<dd>AX register, setting to absolute value, 171</dd>
<dd><big><b>B</b></big></dd>
<dd>Backface culling. <i>See</i> Backface removal.</dd>
<dd>
Backface removal
<dl>
<dd><i>See also</i> Hidden surface removal; Visible surface determination.</dd>
<dd>BSP tree rendering, 1160-1161</dd>
<dd>calculations, 955-957</dd>
<dd>motivation for, 954-955</dd>
<dd>and sign of dot product, 1140</dd>
<dd>solid cube rotation demo program, <b>957-961,</b> 962-963, <b>964-966,</b> 967</dd>
</dl>
</dd>
<dd>Background surfaces, 1240</dd>
<dd><b>BackRotateVector</b> function, <b>1203</b></dd>
<dd>Ball animation demo program, 431-441</dd>
<dd>Barrel shifter, VGA, 463-464</dd>
<dd>
Beam trees
<dl>
<dd>improvement, attempts at, 1187-1188</dd>
<dd>overview, 1185</dd>
<dd>performance, 1186</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
<dd>Benchmarks, reliability of, 729</dd>
<dd>Biased perceptions, and optimization, 1080, 1085</dd>
<dd>Big endian format, 252</dd>
<dd>BIOS. <i>See</i> EGA BIOS; VGA BIOS.</dd>
<dd>
Bit mask
<dl>
<dd>bitmapped text demo program, <b>466-469,</b> 470-471</dd>
<dd>and latches, 470</dd>
<dd>overview, 464-466</dd>
</dl>
</dd>
<dd>
Bit Mask register
<dl>
<dd>bit mask, controlling, 465</dd>
<dd>drawing solid text, 1040</dd>
<dd>setting inside a loop, 429</dd>
<dd>vs. write mode 3, 832, 844</dd>
</dl>
</dd>
<dd>BitMan, 1039-1041, <b>1042-1044</b></dd>
<dd>Bitmap organization, Mode X, 882-883</dd>
<dd>
Bitmapped text
<dl>
<dd>demo program using bit mask, <b>466-469,</b> 470-471</dd>
<dd>reference material, 471</dd>
</dl>
</dd>
<dd>Bitmapped text demo program, <b>466-469,</b> 470-471</dd>
<dd>
Bitmaps
<dl>
<dd>chunky, converting to planar, 504-505, <b>505-508</b></dd>
<dd>relocating, 516-517</dd>
<dd>transient color effects, 509</dd>
</dl>
</dd>
<dd>
Bit-plane animation
<dl>
<dd>assembly implementation, <b>801-809,</b> 810</dd>
<dd>limitations, 811-813</dd>
<dd>overview, 796</dd>
<dd>page flipping, 814</dd>
<dd>palette registers, 799-801</dd>
<dd>principles, 796-798</dd>
<dd>shearing, 813</dd>
</dl>
</dd>
<dd>&ldquo;Black box&rdquo; approach, and future of programming, 725-726</dd>
<dd>Blocks. <i>See</i> Restartable blocks.</dd>
<dd>Borders (overscan), 555-556</dd>
<dd><b>BOUND</b> instruction, 221</dd>
<dd>
Boundary pixels, polygons
<dl>
<dd>rules for selecting, 712</dd>
<dd>texture mapping, 1049-1052, 1065-1066, <b>1067</b></dd>
</dl>
</dd>
<dd>Bounding volumes, 1184</dd>
<dd>
Boyer-Moore algorithm
<dl>
<dd>assembly implementations, <b>271-274, 274-277</b></dd>
<dd>C language implementation, <b>269</b></dd>
<dd>overview, 263-265</dd>
<dd>performance, 266-268</dd>
<dd>test-bed program, <b>270</b></dd>
</dl>
</dd>
<dd>Branch prediction, Pentium processor, 377-378</dd>
<dd>
Branching instructions
<dl>
<dd><i>See also</i> Branch prediction.</dd>
<dd>
286 and 386 processors
<dl>
<dd>non-word-alignment penalty, 216</dd>
<dd>and prefetch queue cycle-eater, 210</dd>
</dl>
</dd>
<dd>eliminating, 312-313</dd>
<dd>
Pentium processor
<dl>
<dd>branches within loops, 378</dd>
<dd>pairing in U-pipe, 405</dd>
</dl>
</dd>
<dd>x86 family CPUs, performance, 140</dd>
</dl>
</dd>
<dd>
Bresenham&rsquo;s line-drawing algorithm
<dl>
<dd>
basic algorithm
<dl>
<dd>assembly implementation, 655-656, <b>671-677</b></dd>
<dd>C language implementation, <b>661-665,</b> 665-671</dd>
<dd>description, 657-660</dd>
<dd>strengths and weaknesses, 660-661</dd>
</dl>
</dd>
<dd>
run-length slice algorithm
<dl>
<dd>assembly implementation, <b>698-704</b></dd>
<dd>C-language implementations, <b>688-692, 692-693</b></dd>
<dd>description, 683-684</dd>
<dd>implementation details, 685-687</dd>
<dd>integer-based implementation, 685-687</dd>
<dd>potential optimizations, 705</dd>
</dl>
</dd>
</dl>
</dd>
<dd>Bresenham&rsquo;s run-length slice algorithm. <i>See</i> Run-length slice algorithm.</dd>
<dd>
Bridges, John
<dl>
<dd>mode set routine, 360x480 256-color mode, 609, <b>612,</b> 620-621</dd>
<dd>256-color modes, undocumented, 879</dd>
</dl>
</dd>
<dd>Brute-force solutions, 193</dd>
<dd>
BSP (Binary Space Partitioning) trees
<dl>
<dd>2-D line representation, 1120</dd>
<dd>3-D rendering, 1162</dd>
<dd>
beam trees
<dl>
<dd>improvement, attempts at, 1187-1188</dd>
<dd>overview, 1185</dd>
<dd>performance, 1186</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
<dd>
BSP compiler
<dl>
<dd><b>BuildBSPTree</b> function, <b>1125-1127</b></dd>
<dd><b>SelectBSPTree</b> function, <b>1124-1125</b></dd>
</dl>
</dd>
<dd><b>BuildBSPTree</b> function, <b>1125-1127</b></dd>
<dd>building, 1101-1104</dd>
<dd><b>BuildTree</b> function, <b>1112</b></dd>
<dd>data recursion vs. code recursion, 1108-1113</dd>
<dd>description, 1098-1099, 1119</dd>
<dd>and dynamic objects, 1100-1101</dd>
<dd>edge sorting for hidden surface removal, 1220, 1226</dd>
<dd>inorder traversal, 1107-1113</dd>
<dd>leaves, storing polygons in, 1181</dd>
<dd>multiple BSP trees, sorting, 1227</dd>
<dd>optimizations, 1128-1129</dd>
<dd>performance, 1100, 1111-1113</dd>
<dd>
potentially visible set (PVS)
<dl>
<dd>precalculating, 1188-1189</dd>
<dd>world, drawing, 1280-1281</dd>
</dl>
</dd>
<dd>reference materials, 1114</dd>
<dd>
rendering recursively
<dl>
<dd>backface removal, 1160-1161</dd>
<dd>clipping, 1158-1159</dd>
<dd><b>ClipWalls</b> function, <b>1152-1155,</b> 1158-1159</dd>
<dd><b>DrawWallsBackToFront</b> function, <b>1155-1156,</b> 1160-1161</dd>
<dd>overview, 1149</dd>
<dd>reference materials, 1157</dd>
<dd><b>TransformVertices</b> function, <b>1151-1152,</b> 1158</dd>
<dd><b>UpdateViewPos</b> function, <b>1151,</b> 1157</dd>
<dd><b>UpdateWorld</b> function, <b>1156-1157,</b> 1157</dd>
<dd>viewspace, transformation of objects to, 1158</dd>
<dd>wall orientation testing, 1160-1161</dd>
<dd><b>WallFacingViewer</b> function, <b>1150-1151,</b> 1161</dd>
</dl>
</dd>
<dd><b>SelectBSPTree</b> function, <b>1124-1125</b></dd>
<dd>splitting heuristic, 1128-1129</dd>
<dd>
3-D engine, Quake
<dl>
<dd>overview, 1276-1277</dd>
<dd>potentially visible set (PVS) management, 1278-1279</dd>
</dl>
</dd>
<dd>
visible surface determination (VSD)
<dl>
<dd>beam trees, 1185-1189</dd>
<dd>culling to frustum, 1181-1184</dd>
<dd>overdraw problem, 1184-1185</dd>
<dd>painter&rsquo;s algorithm, 1099-1106</dd>
<dd>polygon culling, 1181-1184</dd>
<dd>PVS, precalculating, 1188-1189</dd>
</dl>
</dd>
<dd><b>WalkBSPTree</b> function, <b>1106</b></dd>
<dd><b>WalkTree</b> function, 1109-1110</dd>
</dl>
</dd>
<dd>
BSP compiler
<dl>
<dd><b>BuildBSPTree</b> function, <b>1125-1127</b></dd>
<dd>overview, 1123</dd>
<dd><b>SelectBSPTree</b> function, <b>1124-1125</b></dd>
</dl>
</dd>
<dd>BSP models, Quake 3-D engine, 1284</dd>
<dd>
<b>BSWAP</b> instruction, 486 processor
<dl>
<dd>32-bit registers, using as two 16-bit registers, 253-254</dd>
<dd>rotating pixel bits, 252</dd>
</dl>
</dd>
<dd>Bubble sort, 755</dd>
<dd>
Buffer-filling routine, optimizations
<dl>
<dd>rearranging instructions, 418-419</dd>
<dd>reducing size of code, 416-418</dd>
<dd>stack addressing, 420</dd>
</dl>
</dd>
<dd>
Buffers, internal
<dl>
<dd>in 16-bit checksum program, 15-16</dd>
<dd>in search engine, 114-115</dd>
</dl>
</dd>
<dd><b>BuildBSPTree</b> function, <b>1125-1127</b></dd>
<dd><b>BuildGET</b> function, <b>768-769</b></dd>
<dd><b>BuildGETStructure</b> function, <b>747-748</b></dd>
<dd><b>BuildMaps</b> function, <b>353-355</b></dd>
<dd><b>BuildTree</b> function, <b>1112</b></dd>
<dd>
Bus access
<dl>
<dd>8088 processor, 81, 99-101</dd>
<dd>Pentium processor, 377</dd>
</dl>
</dd>
<dd>Byte registers, 486 processor, 242-245</dd>
<dd>Byte-<b>OUT</b> instruction, 429</dd>
<dd>Byte-per-pixel mode. <i>See</i> Mode X.</dd>
<dd><big><b>C</b></big></dd>
<dd>
C library functions
<dl>
<dd><b>getc()</b> function, 12, 14</dd>
<dd><b>memchr()</b> function, 116</dd>
<dd><b>memcmp()</b> function, 116</dd>
<dd><b>memcpy()</b> function, 1147-1148</dd>
<dd><b>memset()</b> function, 727</dd>
<dd>optimization, 15</dd>
<dd><b>read()</b> function, 12, 121</dd>
<dd><b>strstr()</b> function, 115</dd>
</dl>
</dd>
<dd>Cache, internal. <i>See</i> Internal cache.</dd>
<dd>Cache lines, Pentium processor, 374</dd>
<dd>Calculations, redundant, and optimization, 682-683</dd>
<dd><i>Calculus and Analytic Geometry</i> (book), 1135</dd>
<dd>
<b>CALL</b> instruction
<dl>
<dd>486 processor, 241-242</dd>
<dd>Pentium processor, 404</dd>
</dl>
</dd>
<dd>
Carmack, John
<dl>
<dd>and id Software, 1118</dd>
<dd>overdraw, 1184-1186</dd>
<dd>subdivision rasterization, 1266-1267, <b>1267-1270</b></dd>
</dl>
</dd>
<dd>
Carry flag
<dl>
<dd><b>DEC</b> instruction, 148</dd>
<dd><b>INC</b> vs. <b>ADD</b> instructions, 147-148</dd>
<dd>LOOP instruction, 148</dd>
<dd>rotating bits through, 185</dd>
<dd>in word count program (David Stafford), 317-319</dd>
</dl>
</dd>
<dd>Cats, shipping via air freight, 697-698</dd>
<dd><b>Cellmap</b> class, <b>325-329, 333-335, 341-345</b></dd>
<dd>Cellmap wrapping, Game of Life, 331-332, <b>333-335, 336,</b> 337-338</dd>
<dd><b>Cell_state</b> method, <b>327, 334, 344</b></dd>
<dd>
CGA (Color/Graphics Adapter)
<dl>
<dd>display adapter cycle-eater, 104</dd>
<dd>VGA compatibility with, 430</dd>
</dl>
</dd>
<dd>
Challenges
<dl>
<dd>
Game of Life
<dl>
<dd>rules, 346, 350</dd>
<dd>3-cell-per-word implementation (David Stafford), 351-352, <b>353-363,</b> 363-365</dd>
</dl>
</dd>
<dd><b>ScanBuffer</b> routine, 305, 307-319</dd>
</dl>
</dd>
<dd>Change list, in Game of Life, 363-366</dd>
<dd>Chaplin, Michael, 776</dd>
<dd>Character/attribute map, VGA mode 3, 517</dd>
<dd>Chartreuse moose story, 399</dd>
<dd>Checksum programs. <i>See</i> 16-bit checksum program; TCP/IP checksum program.</dd>
<dd>Chunky bitmap conversion demo program, <b>505-508</b></dd>
<dd>Chunky bitmaps, converting to planar, 504-505, <b>505-508</b></dd>
<dd>Circular linked lists, 288-292</dd>
<dd><b>Clear_cell</b> method, <b>327, 334, 343</b></dd>
<dd><b>ClearEdgeLists</b> function, <b>1236-1237</b></dd>
<dd>Clements, Willem, <b>313-315</b></dd>
<dd>Client-server architecture, and QuakeWorld, 1291</dd>
<dd>
Clipping
<dl>
<dd><i>See also</i> Hidden surface removal (HSR); Visible surface determination (VSD).</dd>
<dd>arithmetic imprecision, handling, 1240</dd>
<dd>in BSP tree rendering, 1158-1159</dd>
<dd>line segments, clipping to planes, 1195-1197</dd>
<dd>masked copying, Mode X, 923</dd>
<dd>overview, 1195</dd>
<dd>
polygon clipping
<dl>
<dd><b>BackRotateVector</b> function, <b>1203</b></dd>
<dd>clipping to frustum, 1200, <b>1201-1206,</b> 1206-1207</dd>
<dd><b>ClipToFrustum</b> function, 1204</dd>
<dd><b>ClipToPlane</b> function, 1199</dd>
<dd>optimization, 1207</dd>
<dd>overview, 1197-1200</dd>
<dd><b>PolyFacesViewer</b> function, <b>1203</b></dd>
<dd><b>ProjectPolygon</b> function, <b>1201</b></dd>
<dd><b>SetUpFrustum</b> function, <b>1204</b></dd>
<dd><b>SetWorldspace</b> function, <b>1204</b></dd>
<dd><b>TransformPoint</b> function, <b>1203</b></dd>
<dd><b>TransformPolygon</b> function, <b>1203</b></dd>
<dd><b>UpdateViewPos</b> function, <b>1202</b></dd>
<dd><b>UpdateWorld</b> function, <b>1205</b></dd>
<dd>viewspace clipping, 1207</dd>
<dd><b>ZSortObjects</b> function, <b>1201</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd><b>ClipToFrustum</b> function, <b>1204</b></dd>
<dd><b>ClipToPlane</b> function, <b>1199</b></dd>
<dd>
Clock cycles
<dl>
<dd><i>See also</i> Cycle-eaters.</dd>
<dd>address calculation pipeline, 238-240</dd>
<dd>branch prediction, 377-378</dd>
<dd>byte registers and lost cycles, 242-245</dd>
<dd>cross product floating point optimization, 1171, 1172</dd>
<dd>and data alignment, 213-215</dd>
<dd>data transfer rates, 81, 82</dd>
<dd>dot product floating point optimization, 1170</dd>
<dd>dual-pipe execution, 405</dd>
<dd>
effective address calculations
<dl>
<dd>286 and 386 processors, 223-225</dd>
<dd>Pentium processor, 375-376</dd>
</dl>
</dd>
<dd>
8088 processor
<dl>
<dd>data transfer rates, 81, 82</dd>
<dd>memory access, 82, 83-85</dd>
</dl>
</dd>
<dd>floating point instructions, 1167-1170</dd>
<dd>
486 processor
<dl>
<dd>address calculation pipeline, 238-240, 250</dd>
<dd>byte registers and lost cycles, 242-245</dd>
<dd>indexed addressing, 237-238</dd>
<dd>stack addressing, 241-242</dd>
<dd>32-bit addressing modes, 256-258</dd>
</dl>
</dd>
<dd><b>FXCH</b> instruction, 1170</dd>
<dd>indexed addressing, 237-238</dd>
<dd>instruction execution times, 86-93</dd>
<dd>lockstep execution, 390-394, 400-403</dd>
<dd>matrix transformation optimization, 1173</dd>
<dd>memory access, 82, 83-85</dd>
<dd>non-alignment penalties, 376</dd>
<dd>non-word-alignment penalty, 217</dd>
<dd>1/z value of planes, calculating, 1221</dd>
<dd><b>OUT</b> instructions, 843, 1082-1083</dd>
<dd>
Pentium processor
<dl>
<dd>branch prediction, 377-378</dd>
<dd>cross product floating point optimization, 1171, <b>1172</b></dd>
<dd>dot product floating point optimization, 1170</dd>
<dd>effective address calculations, 375-376</dd>
<dd>floating point instructions, 1167-1168</dd>
<dd><b>FXCH</b> instruction, 1170</dd>
<dd>initial pipe, effect of, 405</dd>
<dd>lockstep execution, 390-394, 400-403</dd>
<dd>matrix transformation optimization, 1173</dd>
<dd>non-alignment penalties, 376</dd>
<dd>pipelining, 1168-1170</dd>
<dd>prefix bytes, 376, 395, 407</dd>
</dl>
</dd>
<dd>prefix bytes, 376, 395, 407</dd>
<dd>vs. program size, 28</dd>
<dd>projection, floating point optimization, 1174</dd>
<dd>stack addressing, 241-242</dd>
<dd>string instructions, 82</dd>
<dd>system wait states, 211</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>386 processor, effective address calculation, 223-225</dd>
<dd>
286 processor
<dl>
<dd>effective address calculation, 223-225</dd>
<dd>system wait states, 211</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
<b>CMP</b> instruction
<dl>
<dd>operands, order of, 306</dd>
<dd>vs. <b>SCASW,</b> 161</dd>
</dl>
</dd>
<dd><b>CMPXCHG8B</b> instruction, Pentium processor, 378</dd>
<dd>
Code alignment
<dl>
<dd>386 processor, 218</dd>
<dd>286 processor, 215-218</dd>
</dl>
</dd>
<dd>Code generator, for Game of Life (David Stafford), 351-352, 353-363, 363-365</dd>
<dd>
Code recursion
<dl>
<dd>vs. data recursion, 1108-1110</dd>
<dd>Euclid&rsquo;s algorithm, 198-199</dd>
</dl>
</dd>
<dd>Collision detection demo program, <b>531-534</b></dd>
<dd>
Color
<dl>
<dd>adapter-dependent mapping, 1036</dd>
<dd>color perception research, 1035</dd>
<dd>reflective vs. emissive, 1035</dd>
</dl>
</dd>
<dd>Color Compare register, 531</dd>
<dd>
Color cycling
<dl>
<dd>bit-by-bit loading of DAC, 650-651</dd>
<dd>demo program, 643, <b>644-648,</b> 648-649</dd>
<dd>interleaved loading of DAC, 649-650</dd>
<dd>loading DAC, 640-643</dd>
<dd>overview, 639-640</dd>
<dd>using page flipping, 650</dd>
<dd>using subset of DAC, 649</dd>
</dl>
</dd>
<dd>Color cycling demo program, 643, <b>644-648,</b> 648-649</dd>
<dd>Color Don&rsquo;t Care register, 534</dd>
<dd>Color Don&rsquo;t Care register demo program, <b>535-537,</b> 535</dd>
<dd>Color mapping demo program, EGA, <b>551-555</b></dd>
<dd>Color models. <i>See</i> RGB (red, green, blue) color model.</dd>
<dd>Color paging, 628-629</dd>
<dd>
Color path, VGA
<dl>
<dd>color paging, 628-629</dd>
<dd>DAC (Digital/Analog Converter), 626-628</dd>
<dd>palette RAM, 626</dd>
</dl>
</dd>
<dd>Color planes. <i>See</i> Planes, VGA.</dd>
<dd>Color Select register, 628-629</dd>
<dd>
Color selection
<dl>
<dd>
EGA
<dl>
<dd>overscan, 555-556</dd>
<dd>palette registers, 548-551, <b>551-555</b></dd>
<dd>screen blanking, <b>556-557</b></dd>
</dl>
</dd>
<dd>VGA, 557</dd>
</dl>
</dd>
<dd><b>ColorBarsUp</b> subroutine, <b>604</b></dd>
<dd>Color-forcing demo program, <b>474-476</b></dd>
<dd>Color-patterned lines demo program, <b>509-515</b></dd>
<dd>Compiled DLLs, Quake 2, 1293</dd>
<dd>
Compiler-based optimization
<dl>
<dd>cautions for use of, 9</dd>
<dd>data recursion vs. code recursion, 1112-1113</dd>
<dd>in <b>FindIDAverage</b> function, <b>159</b></dd>
</dl>
</dd>
<dd>
Compilers
<dl>
<dd>vs. assembly language programmers, 154-155</dd>
<dd>avoiding thinking like, 152, 154-155</dd>
<dd>bitblt compiler for Game of Life (David Stafford), 351-352, <b>353-363,</b> 363-365</dd>
<dd>handling of segments, 154</dd>
</dl>
</dd>
<dd>
Complex polygons
<dl>
<dd>defined, 710, 742</dd>
<dd>edges, keeping track of, 742-744, 753, 755, 756</dd>
<dd>polygon-filling programs, <b>745-752, 754</b></dd>
</dl>
</dd>
<dd><i>Computational Geometry, An Introduction</i> (book), 759-760</dd>
<dd><i>Computer Graphics: Principles and Practice</i> (book), 660, 934, 1121</dd>
<dd><i>Computer Graphics</i> (book), 1135, 1157</dd>
<dd>
<b>ConcatXforms</b> function
<dl>
<dd>assembly implementation, <b>997-999, 1019-1022</b></dd>
<dd>C-language implementation, <b>944, 976</b></dd>
</dl>
</dd>
<dd><b>CONSTANT_TO_INDEXED_REGISTER</b> macro, <b>594</b></dd>
<dd>
Coordinate systems
<dl>
<dd>left-handed, 1140</dd>
<dd>right-handed, 935-937</dd>
</dl>
</dd>
<dd><b>Copy_cells</b> method, 327, 333</dd>
<dd><b>CopyDirtyRectangles</b> function, 850</dd>
<dd><b>CopyDirtyRectangleToScreen</b> function, <b>866-867</b></dd>
<dd>
Copying
<dl>
<dd>bytes between registers, 172</dd>
<dd>pixels, using latches (Mode X), <b>905-907,</b> 908,</dd>
</dl>
</dd>
<dd><b>871</b></dd>
<dd><b>CopyScreenToScreenMaskedX</b> subroutine, 918, <b>919-921</b></dd>
<dd><b>CopyScreenToScreenX</b> subroutine, <b>905-907,</b> 908</dd>
<dd><b>CopySystemToScreenMaskedX</b> subroutine, <b>916-918</b></dd>
<dd><b>CopySystemToScreenX</b> subroutine, 908, <b>909-911</b></dd>
<dd><b>CosSin</b> subroutine, <b>994-996,</b> 999, <b>1013-1015</b></dd>
<dd><b>Count_neighbors</b> method, <b>334-335</b></dd>
<dd>CPU reads from VGA memory, 526</dd>
<dd><b>CPUID</b> instruction, Pentium processor, 378</dd>
<dd><b>CreateAlignedMaskedImage</b> function, 922-923</dd>
<dd>
Cross products
<dl>
<dd>calculating, 955-956, 1139-1140</dd>
<dd>floating point optimization, 1171, 1172</dd>
</dl>
</dd>
<dd>CRT Controller, VGA. <i>See</i> CRTC (CRT Controller), VGA.</dd>
<dd>
CRTC (CRT Controller), VGA
<dl>
<dd>addressing, 427-428</dd>
<dd>Line Compare register, 565</dd>
<dd>Overflow register, 565</dd>
<dd>shearing, 813-814</dd>
<dd>start address registers, setting, 583</dd>
</dl>
</dd>
<dd>
Cycle-eaters
<dl>
<dd>
286 and 386 processors
<dl>
<dd>data alignment cycle-eater,</dd>
<dd>display adapter cycle-eater, 219-221</dd>
<dd>DRAM refresh cycle-eater, 219</dd>
<dd>overview, 209-210</dd>
<dd>prefetch queue cycle-eater, 211-212</dd>
<dd>system wait states, 210-212</dd>
</dl>
</dd>
<dd>
data alignment cycle-eater
<dl>
<dd>386 processor, 218</dd>
<dd>286 processor, 213-215</dd>
</dl>
</dd>
<dd>
display adapter cycle-eater
<dl>
<dd>286 and 386 processors, 219-221</dd>
<dd>8088 processor, 101-108</dd>
</dl>
</dd>
<dd>
DRAM refresh cycle-eater
<dl>
<dd>286 and 386 processors, 219</dd>
<dd>8088 processor, 95-99, 108</dd>
</dl>
</dd>
<dd>8-bit bus cycle-eater, 79-85, 108</dd>
<dd>
8088 processor
<dl>
<dd>display adapter cycle-eater, 101-108</dd>
<dd>DRAM refresh cycle-eater, 95-99, 108</dd>
<dd>8-bit bus cycle-eater, 79-85, 108</dd>
<dd>prefetch queue cycle-eater, 86-94, 108</dd>
<dd>wait states, 99-101</dd>
</dl>
</dd>
<dd>
overview
<dl>
<dd>286 and 386 processors, 209-210</dd>
<dd>8088 processor, 78-79, 80</dd>
</dl>
</dd>
<dd>
prefetch queue cycle-eater
<dl>
<dd>286 and 386 processors, 211-212</dd>
<dd>8088 processor, 86-94, 108</dd>
</dl>
</dd>
<dd>system wait states, 210-212</dd>
<dd>wait states, 99-101</dd>
</dl>
</dd>
<dd>Cycles. <i>See</i> Clock cycles; Cycle-eaters.</dd>
<dd><big><b>D</b></big></dd>
<dd>
DAC (Digital/Analog Converter)
<dl>
<dd>
color cycling
<dl>
<dd>bit-by-bit loading, 650-651</dd>
<dd>color cycling demo program, 643, <b>644-648,</b> 648-649</dd>
<dd>interleaved loading, 649-650</dd>
<dd>problems, 640-643</dd>
<dd>using subset of, 649</dd>
</dl>
</dd>
<dd>Data register, 642-643</dd>
<dd>index wrapping, 651</dd>
<dd>
loading
<dl>
<dd>bit-by-bit loading, 650-651</dd>
<dd>directly, 642-643</dd>
<dd>interleaved loading, 649-650</dd>
<dd>via VGA BIOS, 641-642, 648</dd>
<dd>and Write Index register, 642-643, 651</dd>
</dl>
</dd>
<dd>Mask register, blanking screen, 651</dd>
<dd>Read Index register, 651-652</dd>
<dd>reading, 651-652</dd>
<dd>setting registers, 630, 631-632</dd>
<dd>in VGA color path, 626-628</dd>
<dd>
Write Index register
<dl>
<dd>DAC index wrapping, 651</dd>
<dd>loading DAC, 642-643</dd>
</dl>
</dd>
</dl>
</dd>
<dd>DAC registers demo program, 632-635</dd>
<dd>
Data alignment cycle-eater
<dl>
<dd>386 processor, 218</dd>
<dd>286 processor, 213-215</dd>
</dl>
</dd>
<dd>
Data bus, 8-bit
<dl>
<dd><i>See also</i> 8-bit bus cycle-eater.</dd>
</dl>
</dd>
<dd>Data manipulation instructions, and flags, 147</dd>
<dd>
Data recursion
<dl>
<dd>vs. code recursion, 1108</dd>
<dd>Euclid&rsquo;s algorithm, 200</dd>
<dd>inorder tree traversal, 1108, <b>1109-1110,</b> 1110</dd>
</dl>
</dd>
<dd>Data register, loading DAC, 642-643</dd>
<dd>
Data Rotate register
<dl>
<dd>barrel shifter, controlling, 463</dd>
<dd>vs. CPU-based rotations, 489</dd>
<dd>effect on ALUs, 452</dd>
</dl>
</dd>
<dd>
Data rotation, VGA
<dl>
<dd>barrel shifter, 463-464</dd>
<dd>bit mask, 464-471</dd>
<dd>CPU vs. Data Rotate register, 489</dd>
</dl>
</dd>
<dd>
Data transfer rates
<dl>
<dd>display adapters, 220</dd>
<dd>8088 processor vs. 8086 processor, 81, 82</dd>
<dd>286 processor, 212</dd>
</dl>
</dd>
<dd>
DDA (digital differential analyzer) texture mapping
<dl>
<dd>assembly implementation, <b>1069-1073,</b> 1074</dd>
<dd>C implementation, <b>1053-1058</b></dd>
<dd>disadvantages, 1052-1053, 1059</dd>
<dd><b>DrawTexturedPolygon,</b> 1055-1056</dd>
<dd>hardware dependence, 1053</dd>
<dd>multiple adjacent polygons, 1068</dd>
<dd>optimized implementation, <b>1069-1073,</b> 1074</dd>
<dd>orientation independence, 1065-1067, <b>1067</b></dd>
<dd>performance, 1074</dd>
<dd><b>ScanOutLine</b> function, <b>1058-1059, 1067, 1069-1073,</b> 1074</dd>
<dd><b>SetUpEdge</b> function, <b>1057-1058</b></dd>
<dd>StepEdge function, 1056-1057</dd>
<dd>techniques, 1048-1051</dd>
</dl>
</dd>
<dd><i>DDJ Essential Books on Graphics Programming</i> (CD), 1157</dd>
<dd>
<b>DEC</b> instruction
<dl>
<dd>and Carry flag, 148</dd>
<dd>memory accesses, 83</dd>
<dd>vs. <b>SUB,</b> 219</dd>
</dl>
</dd>
<dd><b>DEC/JNZ</b> sequence, 139</dd>
<dd>
Delay sequences
<dl>
<dd>loading palette RAM or DAC registers, 632</dd>
<dd>VGA programming, 558</dd>
</dl>
</dd>
<dd><b>DeleteNodeAfter</b> function, <b>284</b></dd>
<dd>Depth sorting of nonconvex objects, 1000, <b>1001-1002</b></dd>
<dd>Diffuse shading, 1023-1025, <b>1025-1027</b></dd>
<dd>Digital differential analyzer. <i>See</i> DDA (digital differential analyzer).</dd>
<dd>Direct far jumps, 186</dd>
<dd>Direct memory access. <i>See</i> DMA.</dd>
<dd>Directed lighting, and shading, 1023, 1028</dd>
<dd>
Directives
<dl>
<dd><b>EVEN,</b> 214</dd>
<dd><b>NOSMART,</b> 72</dd>
</dl>
</dd>
<dd>
Dirty-rectangle animation
<dl>
<dd>demo program, C implementation, <b>847-851, 863-869</b></dd>
<dd>description, 844-845</dd>
<dd>ordering rectangles, 873</dd>
<dd>overlapping rectangles, 872-873</dd>
<dd>vs. page flipping, 846, 862</dd>
<dd>performance, 873</dd>
<dd>system memory buffer size, 851</dd>
<dd>writing to display memory, 856-857</dd>
</dl>
</dd>
<dd>Disk caches, 19</dd>
<dd>
Display adapter cycle-eater
<dl>
<dd>286 and 386 processors, 219-221</dd>
<dd>data transfer rates, 220</dd>
<dd>
8088 processor
<dl>
<dd>graphics routines, impact on, 106</dd>
<dd>optimizing for, 107</dd>
<dd>overview, 101-104</dd>
<dd>performance, impact on, 104</dd>
<dd>read/write/modify operations, 107</dd>
<dd>wait states, 99-101</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
Display memory
<dl>
<dd><i>See also</i> Bit mask; Displaymemory access.</dd>
<dd>
Mode X
<dl>
<dd>copying between memory locations, <b>905-907,</b> 908</dd>
<dd>copying from system memory, 908, <b>909-911</b></dd>
<dd>masked copy from system memory, <b>916-918,</b> 916</dd>
<dd>masked copying between locations, 918-919, <b>919-921</b></dd>
<dd>memory allocation, 903-904</dd>
</dl>
</dd>
<dd>running code from, 104</dd>
<dd>start address, changing, 857</dd>
<dd>
VGA
<dl>
<dd>access times, 842-844</dd>
<dd>360x480 256-color mode, 621-622</dd>
<dd>320 x 400 256-color mode, 591-593, 605</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
Display memory access
<dl>
<dd><i>See also</i> Display memory; Memory access.</dd>
<dd>display adapter cycle-eater, 101-103, 105, 107</dd>
<dd>and string instructions, 107</dd>
<dd>VGA access times, 842-844</dd>
<dd>wait states, 101-103, 220, 733</dd>
</dl>
</dd>
<dd>Display memory planes. <i>See</i> Planes, VGA.</dd>
<dd><b>DIV</b> instruction, 32-bit division, 181-184, 1008</dd>
<dd>Divide By Zero interrupt, 181</dd>
<dd>Divide-by-N timer mode, 45</dd>
<dd>Division, 32-bit, 181-184, 1008</dd>
<dd>DMA (direct memory access), and DRAM refresh, 95</dd>
<dd>&ldquo;Don&rsquo;t care&rdquo; planes, 535</dd>
<dd>
DOS function calls
<dl>
<dd>overhead, 9</dd>
<dd>and restartable blocks, 123</dd>
</dl>
</dd>
<dd>
Dot products
<dl>
<dd>calculating, 1135-1137</dd>
<dd>calculating light intensity, 1137</dd>
<dd>floating point optimization, 1170, <b>1171</b></dd>
<dd>line segments, clipping to planes, 1196-1197</dd>
<dd>projection, 1141-1142</dd>
<dd>rotation, 1143-1144</dd>
<dd>sign of, 1140-1141</dd>
<dd>of unit vectors, 1136</dd>
<dd>of vectors, 1135-1136</dd>
</dl>
</dd>
<dd>Double-DDA texture mapping. <i>See</i> DDA (digital differential analyzer) texture mapping.</dd>
<dd><b>D_PolysetRecursiveTriangle</b> function, <b>1267-1270</b></dd>
<dd><i>Dr. Dobbs Journal,</i> 1190</dd>
<dd>
DRAM (dynamic RAM) refresh cycle-eater
<dl>
<dd>286 and 386 processors, 219</dd>
<dd>
8088 processor
<dl>
<dd>impact on performance, 97-98</dd>
<dd>optimizing for, 98-99</dd>
<dd>overview, 95-97</dd>
<dd>vs. wait states, 100</dd>
</dl>
</dd>
<dd>and 8253 timer chip, 95</dd>
<dd>and Zen timer, 99</dd>
</dl>
</dd>
<dd><b>Draw360x480Dot</b> subroutine, <b>613-614</b></dd>
<dd><b>DrawBackground</b> function, <b>928</b></dd>
<dd>Draw-buffers, and beam trees, 1187</dd>
<dd><b>DrawBumperList</b> function, <b>823</b></dd>
<dd><b>DrawEntities</b> function, <b>849, 866</b></dd>
<dd><b>DrawGridCross</b> subroutine, <b>808</b></dd>
<dd><b>DrawGridVert</b> subroutine, <b>808-809</b></dd>
<dd>
<b>DrawHorizontalLineList</b> function
<dl>
<dd>monotone-vertical polygons, filling, <b>765</b></dd>
<dd>
non-overlapping convex polygon
<dl>
<dd>assembly implementation, <b>734</b></dd>
<dd>C implementation, <b>717,</b> 720-721</dd>
<dd>using memset() function, 727, <b>729</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd><b>DrawHorizontalLineList</b> subroutine, <b>941-943</b></dd>
<dd>
<b>DrawHorizontalLineSeg</b> function
<dl>
<dd>assembly implementation, <b>754</b></dd>
<dd>C implementation, <b>750-751</b></dd>
</dl>
</dd>
<dd><b>DrawHorizontalRun</b> function, <b>692</b></dd>
<dd><b>DrawImage</b> subroutine, <b>828</b></dd>
<dd>
Drawing
<dl>
<dd><i>See also</i> Line-drawing algorithms; Lines; 3-D drawing.</dd>
<dd>fill patterns, using latches, 453</dd>
<dd>
pixel drawing
<dl>
<dd><b>EVGADot</b> function, <b>661-662,</b> 669-670</dd>
<dd>optimization, 1074, 1086</dd>
<dd>painter&rsquo;s algorithm and overdraw problem, 1184</dd>
</dl>
</dd>
<dd>single-color drawing with write mode 3, 831-832</dd>
<dd>speeding up, 727-729</dd>
<dd>
text
<dl>
<dd>bitmapped text using bit mask, <b>466-469,</b> 470-471</dd>
<dd>bitmapped text using write mode 3, <b>484-489,</b> 489-490, <b>490-496</b></dd>
<dd>solid text using latches, 1039-1041, <b>1042-1044</b></dd>
<dd>using write mode 0, 832-833</dd>
</dl>
</dd>
</dl>
</dd>
<dd><b>DrawLine</b> function, <b>785</b></dd>
<dd><b>DrawMasked</b> subroutine, <b>870</b></dd>
<dd><b>DrawObject</b> subroutine, <b>809-810</b></dd>
<dd><b>Draw_pixel</b> function, <b>328, 330</b></dd>
<dd><b>DrawPObject</b> function, <b>978-979, 1025-1027</b></dd>
<dd><b>DrawRect</b> subroutine, <b>826-827</b></dd>
<dd><b>DrawSpans</b> function, <b>1236</b></dd>
<dd><b>DrawSplitScreen</b> function, <b>824</b></dd>
<dd><b>DrawTextString</b> subroutine, <b>1043-1044</b></dd>
<dd><b>DrawTexturedPolygon</b> function, <b>1055-1056</b></dd>
<dd><b>DrawVerticalRun</b> function, <b>692</b></dd>
<dd><b>DrawVisibleFaces</b> function, <b>961</b></dd>
<dd>
<b>DrawWuLine</b> function
<dl>
<dd>assembly implementation, <b>787-791</b></dd>
<dd>C implementation, <b>780-781</b></dd>
</dl>
</dd>
<dd>Duntemann, Jeff, 127-128</dd>
<dd>
Dynamic lighting
<dl>
<dd>in GLQuake, 1289-1290</dd>
<dd>in Quake 3-D engine, 1282-1283</dd>
</dl>
</dd>
<dd>Dynamic objects, and BSP trees, 1100-1101</dd>
<dd>Dynamic palette adjustment, 1039</dd>
<dd>Dynamic RAM. <i>See</i> DRAM (dynamic RAM) refresh.</dd>
<dd><big><b>E</b></big></dd>
<dd>
EA (effective address) calculations
<dl>
<dd>286 and 386 processors, 223-225</dd>
<dd>8088 processor, 129</dd>
<dd>
486 processor
<dl>
<dd>address calculation pipeline, 238-240</dd>
<dd>stack addressing, 241-242</dd>
</dl>
</dd>
<dd>Pentium processor, 375-376</dd>
<dd>320x400 256-color mode, 599-600</dd>
</dl>
</dd>
<dd>EBP register, 257</dd>
<dd>
Edge tracing
<dl>
<dd>overview, 711-713</dd>
<dd>
<b>ScanEdge</b> function
<dl>
<dd>assembly implementation, <b>735-738,</b> 735</dd>
<dd>floating-point C implementation, <b>716-717</b></dd>
<dd>integer-based C implementation, <b>730-732</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd>Edge triggered devices, 316</dd>
<dd>Edges vs. spans, sorted span hidden surface removal, 1215-1220</dd>
<dd>EGA BIOS, video function 10H, 550-551, 555</dd>
<dd>
EGA (Enhanced Graphics Adapter)
<dl>
<dd>color mapping, 548-551, <b>551-555</b></dd>
<dd>and display adapter cycle-eater, 104-108</dd>
<dd>mode 10H, 515-517, <b>518-521</b></dd>
<dd>palette registers, 549-550</dd>
<dd>registers, and high-level languages, 548</dd>
<dd>screens, capturing and restoring, 541-542, <b>543-547,</b> 547-548</dd>
<dd>
split screens
<dl>
<dd>EGA bug, 573-574</dd>
<dd>horizontal panning, 574-575, <b>575-582,</b> 583</dd>
<dd>overview, 563-565</dd>
<dd>registers, setting, 573</dd>
<dd>safety of, 585</dd>
<dd>split screen demo program, 565, <b>566-572,</b> 572</dd>
<dd>text mode, 584</dd>
<dd>turning on and off, 565</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
8-bit bus cycle-eater
<dl>
<dd>286 and 386 processors, 210</dd>
<dd>
8088 processor
<dl>
<dd>effects on performance, 82</dd>
<dd>optimizing for, 83-85</dd>
<dd>overview, 79-82</dd>
<dd>and registers, 85</dd>
</dl>
</dd>
</dl>
</dd>
<dd>8086 processor vs. 8088 processor, 79-81</dd>
<dd>
8088 processor
<dl>
<dd><b>CMP</b> instruction, 161, 306</dd>
<dd>
cycle-eaters
<dl>
<dd>8-bit bus cycle-eater, 79-85</dd>
<dd>display adapter cycle-eater, 101-108</dd>
<dd>DRAM refresh cycle-eater, 95-99</dd>
<dd>overview, 78-79, 80</dd>
<dd>prefetch queue cycle-eater, 86-94</dd>
<dd>wait states, 99-101</dd>
</dl>
</dd>
<dd>display memory access, 220</dd>
<dd>vs. 8086 processor, 79-81</dd>
<dd>effective address calculation options, 129</dd>
<dd><b>LAHF</b> and <b>SAHF</b> instructions, 148</dd>
<dd><b>LEA</b> vs. <b>ADD,</b> 130</dd>
<dd><b>LODSB</b> instruction, 304</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>memory variables, size of, 83-85</dd>
<dd>stack-based variables, placement of, 184-184</dd>
</dl>
</dd>
<dd>
8253 timer chip
<dl>
<dd>and DRAM refresh, 95</dd>
<dd>reference material, 72</dd>
<dd>resetting, 43</dd>
<dd>
system clock inaccuracies
<dl>
<dd>long-period Zen timer, 53, 54</dd>
<dd>Zen timer, 43, 45-46, 48</dd>
</dl>
</dd>
<dd>
timer 0
<dl>
<dd>operation, 44</dd>
<dd>stopping, 54, 65</dd>
</dl>
</dd>
<dd>timer modes, 44, 45</dd>
<dd>timer operation, 43-45</dd>
<dd>undocumented features, 54, 65</dd>
</dl>
</dd>
<dd>Emissive color, vs. reflective color, 1035</dd>
<dd>
Enable Set/Reset register
<dl>
<dd>setting drawing color, 666</dd>
<dd>specifying plane, 474</dd>
</dl>
</dd>
<dd><b>EnableSplitScreen</b> function, 824</dd>
<dd>
<b>ENTER</b> instruction
<dl>
<dd>486 processor, 241-242</dd>
<dd>Pentium processor, 377</dd>
<dd>286 processor, 221</dd>
</dl>
</dd>
<dd><b>Enter_display_mode</b> function, <b>328, 362</b></dd>
<dd>
Entities, Quake 3-D engine
<dl>
<dd>BSP models, 1284</dd>
<dd>particles, 1287</dd>
<dd>polygon models, 1285-1286</dd>
<dd>sprites, 1287</dd>
<dd>subdivision rasterization, 1286</dd>
<dd>z-buffering, 1285-1286</dd>
</dl>
</dd>
<dd><b>EraseEntities</b> function, <b>850, 867</b></dd>
<dd>Error accumulation, Wu antialiasing algorithm, 778-779, 792</dd>
<dd>
EU (Execution Unit)
<dl>
<dd>
286 and 386 processors
<dl>
<dd>instruction execution times, 223-225</dd>
<dd>and prefetch queue, 210</dd>
</dl>
</dd>
<dd>
8088 processor
<dl>
<dd>8-bit bus cycle-eater, 80</dd>
<dd>prefetch queue cycle-eater, 86</dd>
<dd>wait states, 101</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
Euclid&rsquo;s algorithm
<dl>
<dd>algorithm, 197</dd>
<dd>optimized assembly implementation, <b>200-202</b></dd>
<dd>recursive implementations, <b>198, 200</b></dd>
</dl>
</dd>
<dd><b>EVEN</b> directive, 214</dd>
<dd><b>EVGADot</b> function, <b>661-662,</b> 669-670</dd>
<dd>
<b>EVGALine</b> function
<dl>
<dd>
Bresenham&rsquo;s algorithm
<dl>
<dd>assembly implementation, 671, <b>675-677</b></dd>
<dd>C-language implementation, <b>664-665,</b> 665-668, 670-671</dd>
</dl>
</dd>
<dd>360x480 256-color mode line drawing program, <b>616-617</b></dd>
</dl>
</dd>
<dd>Execution times. <i>See</i> Clock cycles; Instruction execution time.</dd>
<dd><b>Exit_display_mode</b> function, <b>328, 329, 362</b></dd>
<dd><big><b>F</b></big></dd>
<dd><b>FADD</b> instruction, Pentium processor, 1167-1170</dd>
<dd>Far jumps, to absolute addresses, 186-187</dd>
<dd><b>FDIV</b> instruction, Pentium processor, 1167-1170</dd>
<dd>
Fetch time
<dl>
<dd><i>See also</i> Instruction fetching.</dd>
<dd>286 and 386 processors, 210, 211</dd>
<dd>8088 processor, 86-93</dd>
</dl>
</dd>
<dd>
Files
<dl>
<dd>
reading from
<dl>
<dd><b>getc()</b> function, 12, 14</dd>
<dd><b>read()</b> function, 12</dd>
</dl>
</dd>
<dd>restartable blocks, 16</dd>
<dd>text, searching for. <i>See</i> Search engine.</dd>
</dl>
</dd>
<dd>Fill patterns, drawing using latches, 453</dd>
<dd><b>FillConvexPolygon</b> function, <b>714-716</b>, 720-721</dd>
<dd><b>FillMonotoneVerticalPolygon</b> function, <b>763-764</b></dd>
<dd><b>FillPatternX</b> subroutine, 899, <b>900-903</b>, 903-904</dd>
<dd>
<b>FillPolygon</b> function
<dl>
<dd>complex polygons, <b>746</b></dd>
<dd>monotone-vertical polygons, <b>767</b></dd>
</dl>
</dd>
<dd><b>FillRect</b> subroutine, <b>869-870</b></dd>
<dd>
<b>FillRectangleX</b> subroutine
<dl>
<dd>four-plane parallel processing, 888-891, <b>891-893</b></dd>
<dd>pixel-by-pixel plane selection, <b>885-887</b></dd>
<dd>plane-by-plane processing, <b>887-889</b></dd>
</dl>
</dd>
<dd>
<b>FindIDAverage</b> function
<dl>
<dd>
assembly implementations
<dl>
<dd>based on compiler optimization, <b>160</b></dd>
<dd>data structure reorganization, 163, <b>165-166</b></dd>
<dd>unrolled loop, 161, <b>162</b></dd>
</dl>
</dd>
<dd>C language implementation, <b>158</b></dd>
<dd>compiler optimization, <b>159</b></dd>
</dl>
</dd>
<dd><b>FindNodeBeforeValue</b> function, <b>289</b></dd>
<dd><b>FindNodeBeforeValueNotLess</b> function, <b>286, 287</b></dd>
<dd>
<b>FindString</b> function
<dl>
<dd>Boyer-Moore algorithm, <b>269, 271-274, 274-277</b></dd>
<dd>overview, 175</dd>
<dd>scan-on-first-character approach, <b>176</b></dd>
<dd>scan-on-specified-character approach, <b>178</b></dd>
</dl>
</dd>
<dd><b>FirstPass</b> function, <b>355-358</b></dd>
<dd><b>Fix</b> function, <b>358,</b> 365</dd>
<dd><b>FixedDiv</b> subroutine, <b>982, 993, 1010-1012</b></dd>
<dd>FIXED_MUL macro, <b>1016-1017</b></dd>
<dd><b>FixedMul</b> subroutine, <b>981, 993-994, 1009-1010</b></dd>
<dd>
Fixed-point arithmetic
<dl>
<dd>vs. floating point, 985, 1206</dd>
<dd>vs. integer arithmetic, 730, 1065</dd>
<dd>32-bit fixed-point arithmetic, 1086-1089, <b>1090-1091,</b> 1092-1093</dd>
</dl>
</dd>
<dd>
Flags
<dl>
<dd>and <b>BSWAP</b> instruction, 254</dd>
<dd>Carry flag, 147-148, 185, 317-319</dd>
<dd><b>INC</b> vs. <b>ADD,</b> 147-148</dd>
<dd>and <b>LOOP</b> instruction, 148</dd>
<dd>and <b>NOT</b> instruction, 146-147</dd>
</dl>
</dd>
<dd><b>FLD</b> instruction, Pentium processor, 1167-1170</dd>
<dd>
Floating point optimization
<dl>
<dd>clock cycles, core instructions, 1167-1168</dd>
<dd>cross product optimization, 1171, <b>1172</b></dd>
<dd>dot product optimization, 1170, <b>1171</b></dd>
<dd><b>FXCH</b> instruction, 1169-1170</dd>
<dd>interleaved instructions, 1169-1170</dd>
<dd>matrix transformation optimization, 1172-1173, <b>1173-1174</b></dd>
<dd>overview, 1167-1170</dd>
<dd>pipelining, 1168-1170</dd>
<dd>projection to screen space, 1174</dd>
<dd>rounding control, 1174-1175</dd>
</dl>
</dd>
<dd>
Floating-point calculations
<dl>
<dd>vs. fixed-point calculations, 985, 1206</dd>
<dd>vs. integer calculations, 730</dd>
</dl>
</dd>
<dd>
<b>FMUL</b> instruction
<dl>
<dd>486 processor, 236</dd>
<dd>Pentium processor, 1167-1170</dd>
</dl>
</dd>
<dd>
486 processor
<dl>
<dd>AX register, setting to absolute value, 172</dd>
<dd>byte registers and lost cycles, 242-245</dd>
<dd>
<b>CMP</b> instruction
<dl>
<dd>operands, order of, 306</dd>
<dd>vs. <b>SCASW,</b> 161</dd>
</dl>
</dd>
<dd>copying bytes between registers, 172</dd>
<dd>and display adapter cycle-eater, 107</dd>
<dd>indexed addressing, 237-238</dd>
<dd>
internal cache
<dl>
<dd>effect on code timing, 246</dd>
<dd>optimization, 236</dd>
</dl>
</dd>
<dd><b>LAHF</b> and <b>SAHF</b> instructions, 148</dd>
<dd><b>LEA</b> instruction, vs. <b>ADD,</b> 131</dd>
<dd><b>LODSB</b> instruction, 304</dd>
<dd><b>LODSD</b> instruction, vs. <b>MOV/LEA</b> sequence, 171</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction, vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd><b>MOV</b> instruction, vs. <b>XCHG,</b> 377</dd>
<dd>n-bit vs. 1-bit shift and rotate instructions, 255-256</dd>
<dd>Pentium code, running on, 411</dd>
<dd>
pipelining
<dl>
<dd>address calculation, 238-240, 250</dd>
<dd>stack addressing, 241-242</dd>
</dl>
</dd>
<dd>rotation instructions, clock cycles, 185-186</dd>
<dd>stack-based variables, 184-184</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>timing code, 245-246</dd>
<dd>using 32-bit register as two 16-bit registers, 253-254</dd>
<dd><b>XCHG</b> instruction, vs. <b>MOV,</b> 377, 832</dd>
</dl>
</dd>
<dd>
FPU, Pentium processor
<dl>
<dd>clock cycles, core instructions, 1167-1168</dd>
<dd>cross product optimization, 1171, <b>1172</b></dd>
<dd>dot product optimization, 1170, <b>1171</b></dd>
<dd><b>FXCH</b> instruction, 1169-1170</dd>
<dd>interleaved instructions, 1169-1170</dd>
<dd>matrix transformation optimization, 1172-1173, <b>1173-1174</b></dd>
<dd>overview, 1167-1170</dd>
<dd>pipelining, 1168-1170</dd>
<dd>projection to screen space, 1174</dd>
<dd>rounding control, 1174-1175</dd>
</dl>
</dd>
<dd>Frustum, clipping to, 1200, <b>1201-1206,</b> 1206-1207</dd>
<dd><b>FST</b> instruction, Pentium processor, 1167-1170</dd>
<dd><b>FSUB</b> instruction, Pentium processor, 1167-1170</dd>
<dd>Function 13H, VGA BIOS, 459</dd>
<dd>Function calls, performance, 153</dd>
<dd><i>Fundamentals of Interactive Computer Graphics</i> (book), 660</dd>
<dd><b>FXCH</b> instruction, Pentium processor, 1169-1170</dd>
<dd><big><b>G</b></big></dd>
<dd>
Game of Life
<dl>
<dd>abstraction and performance, 330-332, 345-346</dd>
<dd>byte-per-cell implementation, 339-340, <b>341-345</b></dd>
<dd>
C++ implementation
<dl>
<dd>basic, 324, <b>325-328</b></dd>
<dd>optimized, <b>336,</b> 337-338</dd>
</dl>
</dd>
<dd>cellmap-wrapped implementation, 331-332, <b>333-335,</b> 336, <b>337-338</b></dd>
<dd>
challenge to readers
<dl>
<dd>rules, 346, 350</dd>
<dd>3-cell-per-word implementation (David Stafford), 351-352, <b>353-363,</b> 363-365</dd>
</dl>
</dd>
<dd>change list, 363-366</dd>
<dd>performance analysis, 329-330, 332, 338, 340, 350</dd>
<dd>re-examining problem, 338-339, 363</dd>
<dd>rules, 324</dd>
<dd>
3-cell-per-word implementation
<dl>
<dd>discussion, 363-365</dd>
<dd>listing, 352-363</dd>
<dd>overview, 351-352</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
GC (Graphics Controller), VGA
<dl>
<dd>addressing, 427-428</dd>
<dd>
architecture
<dl>
<dd>ALUs, 451-452</dd>
<dd>barrel shifter, 463-464</dd>
<dd>bit mask, 464-471</dd>
<dd>latches, 452-453</dd>
<dd>set/reset circuitry, 471-479</dd>
</dl>
</dd>
<dd>
Bit Mask register
<dl>
<dd>bit mask, controlling, 465</dd>
<dd>drawing solid text, 1040</dd>
<dd>setting inside a loop, 429</dd>
<dd>vs. write mode 3, 832, 844</dd>
</dl>
</dd>
<dd>Color Compare register, 531</dd>
<dd>
Data Rotate register
<dl>
<dd>barrel shifter, controlling, 463</dd>
<dd>vs. CPU-based rotations, 489</dd>
<dd>effect on ALUs, 452</dd>
</dl>
</dd>
<dd>
Enable Set/Reset register
<dl>
<dd>setting drawing color, 666</dd>
<dd>specifying plane, 474</dd>
</dl>
</dd>
<dd>
Graphics Mode register
<dl>
<dd>read mode 0, selecting, 525</dd>
<dd>read mode 1, selecting, 531</dd>
</dl>
</dd>
<dd>
Read Map register
<dl>
<dd>plane, selecting, for CPU reads, 526</dd>
<dd>planes, specifying to be read, 542</dd>
</dl>
</dd>
<dd>Set/Reset register, 666</dd>
</dl>
</dd>
<dd>
<b>Gcd()</b> function
<dl>
<dd>brute-force approach, 195</dd>
<dd>
Euclid&rsquo;s algorithm
<dl>
<dd>code recursive approach, 198</dd>
<dd>data recursion approach, 200</dd>
</dl>
</dd>
<dd>subtraction approach, 196</dd>
</dl>
</dd>
<dd>
GCD (Greatest Common Denominator) problem
<dl>
<dd>brute-force approach, 193-196</dd>
<dd>Euclid&rsquo;s algorithm, 197-200</dd>
<dd>subtraction approach, 196-197</dd>
</dl>
</dd>
<dd><b>Gcd_recurs()</b> function, <b>199</b></dd>
<dd>Generality, vs. performance, 335</dd>
<dd>Gerrold, David, 298</dd>
<dd>GET (global edge table), 744</dd>
<dd>
<b>Getc()</b> function
<dl>
<dd>overhead, 14</dd>
<dd>vs. <b>read()</b> function, 12</dd>
</dl>
</dd>
<dd><b>GetNextKey</b> subroutine, <b>598, 605</b></dd>
<dd><b>GetUpAndDown</b> function, <b>355</b></dd>
<dd>Global edge table (GET), 744</dd>
<dd>GLQuake, 1288-1290</dd>
<dd>
Gouraud shading
<dl>
<dd>overview, 1246-1247</dd>
<dd>perspective correction, 1248-1250</dd>
<dd>problems with, 1247-1250</dd>
</dl>
</dd>
<dd>Graphics cards, and surface caching, 1261-1262</dd>
<dd>Graphics Controller, VGA. <i>See</i> GC (Graphics Controller), VGA.</dd>
<dd>
Graphics Mode register
<dl>
<dd>read mode 0, selecting, 525</dd>
<dd>read mode 1, selecting, 531</dd>
</dl>
</dd>
<dd>Graphics screen capture demo program, <b>543-545</b></dd>
<dd>Graphics screen restore demo program, <b>545-547</b></dd>
<dd>Graphics-to-text demo program, <b>518-521</b></dd>
<dd>Great Buffalo Sauna Fiasco, 137-138</dd>
<dd>GUIs, and future of programming profession, 725-726</dd>
<dd><big><b>H</b></big></dd>
<dd>Hardware dependence, DDA (digital differential analyzer) texture mapping, 1053</dd>
<dd>
Hecker, Chris
<dl>
<dd>texture mapping insight, 1083</dd>
<dd>underlying functionality of different approaches, 1189</dd>
</dl>
</dd>
<dd>Heinlein, Robert A., 1079-1080</dd>
<dd>Herbert, Frank, 1193</dd>
<dd>HGC (Hercules Graphics Card), 104</dd>
<dd>
Hidden surface removal (HSR)
<dl>
<dd>backface removal, 954-957</dd>
<dd>depth sorting, 1000, 1001-1002</dd>
<dd>
sorted spans approach
<dl>
<dd>abutting span sorting, 1229-1230</dd>
<dd><b>AddPolygonEdges</b> function, <b>1232-1233,</b> 1238</dd>
<dd>BSP order vs. 1/z order, 1220, 1226</dd>
<dd><b>ClearEdgeLists</b> function, <b>1236-1237</b></dd>
<dd><b>DrawSpans</b> function, <b>1236</b></dd>
<dd>edge sorting, 1220-1222</dd>
<dd>edges vs. spans, 1215-1220</dd>
<dd>independent span sorting, 1230, <b>1231-1238,</b> 1239-1241</dd>
<dd>intersecting span sorting, 1228-1229</dd>
<dd>1/z sorting, 1220-1222, 1227-1231, <b>1231-1238,</b> 1239-1241</dd>
<dd>overview, 1214-1215</dd>
<dd><b>PolyFacesViewer</b> function, <b>1232</b></dd>
<dd>rotation instructions, clock cycles, 185-186</dd>
<dd><b>ScanEdges</b> function, <b>1234-1236,</b> 1238-1239</dd>
<dd><b>UpdateWorld</b> function, <b>1237-1238</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd>High school graduates in Hawaii, 991-992</dd>
<dd>Horizontal Pel Panning register, 442</dd>
<dd>Horizontal resolution, 360x480 256-color mode, 620</dd>
<dd>Horizontal smooth panning. <i>See</i> Panning.</dd>
<dd><big><b>I</b></big></dd>
<dd>id Software, 1118, 1190</dd>
<dd>Ideas, selling, 1193-1194</dd>
<dd>Illowsky, Dan, 187, 315</dd>
<dd>Image precedence. <i>See</i> Bit-plane animation.</dd>
<dd>
<b>IMUL</b> instruction
<dl>
<dd>486 processor, 236</dd>
<dd>on 386 processor, 173-174</dd>
</dl>
</dd>
<dd>
<b>INC</b> instruction
<dl>
<dd>vs. <b>ADD,</b> 147-148, 219</dd>
<dd>and Carry flag, 147-148</dd>
</dl>
</dd>
<dd>Incremental transformations of 3-D objects, 964</dd>
<dd>
Independent span sorting
<dl>
<dd><b>AddPolygonEdges</b> function, <b>1232-1233,</b> 1238</dd>
<dd><b>ClearEdgeLists</b> function, <b>1236-1237</b></dd>
<dd><b>DrawSpans</b> function, <b>1236</b></dd>
<dd>overview, 1230</dd>
<dd><b>PolyFacesViewer</b> function, <b>1232</b></dd>
<dd><b>ScanEdges</b> function, <b>1234-1236,</b> 1238-1239</dd>
<dd>texture mapping, 1238</dd>
<dd><b>UpdateWorld</b> function, <b>1237-1238</b></dd>
</dl>
</dd>
<dd>
Index registers, VGA
<dl>
<dd>AC Index register, 443</dd>
<dd>overview, 427-428</dd>
</dl>
</dd>
<dd>Indexed addressing, 237-238</dd>
<dd>Indirect far jumps, 186</dd>
<dd>Information, sharing, 1190, 1194</dd>
<dd><b>InitCellmap</b> function, <b>361</b></dd>
<dd><b>InitializeCubes</b> function, <b>980-981</b></dd>
<dd><b>InitializeFixedPoint</b> function, <b>977</b></dd>
<dd><b>InitializeObjectList</b> function, <b>1001</b></dd>
<dd><b>InitializePalette</b> function, <b>1037</b></dd>
<dd><b>InitLinkedList</b> function, <b>289</b></dd>
<dd>
Inorder tree traversal
<dl>
<dd>code recursion vs. data recursion, 1107-1108</dd>
<dd>data recursive implementation, 1108, <b>1109-1110,</b> 1110</dd>
<dd>performance, 1111-1113</dd>
</dl>
</dd>
<dd><b>INS</b> instruction, 221</dd>
<dd><b>InsertNodeSorted</b> assembly routine, <b>290</b></dd>
<dd><b>InsertNodeSorted</b> function, <b>289</b></dd>
<dd>
Instruction execution times
<dl>
<dd><i>See also</i> Clock cycles; Zen timer.</dd>
<dd>DRAM refresh cycle-eater, 97, 99</dd>
<dd>8-bit bus cycle-eater, 82-85</dd>
<dd>estimating, 93</dd>
<dd>and instruction fetching, 225</dd>
<dd>vs. instruction size, 90-92, 93, 211</dd>
<dd>memory-addressing vs. register-only instructions, 223-225</dd>
<dd>prefetch queue cycle-eater, 86-93</dd>
</dl>
</dd>
<dd>
Instruction fetching
<dl>
<dd><i>See also</i> Prefetch queue cycle-eater.</dd>
<dd>code alignment, 215-218</dd>
<dd>8088 processor, 86-93</dd>
<dd>and instruction execution times, 225</dd>
<dd>Pentium processor, 374</dd>
<dd>and system wait states, 211</dd>
<dd>286 processor, 215-218</dd>
<dd>and wait states, 101</dd>
</dl>
</dd>
<dd>Instruction size, 32-bit addressing modes, 257</dd>
<dd>
Instructions, assembly language
<dl>
<dd>optimizing, 23-24</dd>
<dd>
Pentium processor
<dl>
<dd>pairable instructions, 388, 390-394</dd>
<dd>V-pipe-capable instructions, 386-387</dd>
</dl>
</dd>
<dd>size vs. execution time, 90-92, 93</dd>
</dl>
</dd>
<dd>Integer calculations, vs. fixed-point, 730, 1065</dd>
<dd>Integers, sorting, 180-181</dd>
<dd>Interleaved color cycling, 649-650</dd>
<dd>
Interleaved operations, Pentium processor
<dl>
<dd><b>FXCH</b> instruction and floating point operations, 1169-1170</dd>
<dd>matrix transformation, 1172-1173, <b>1173-1174</b></dd>
<dd>overview, 394-395</dd>
<dd>TCP/IP checksum program, <b>408</b></dd>
</dl>
</dd>
<dd>Internal animation, 872</dd>
<dd>
Internal buffering
<dl>
<dd><i>See also</i> Restartable blocks.</dd>
<dd>in 16-bit checksum program, 15-16</dd>
<dd>in search engine, 114-115</dd>
</dl>
</dd>
<dd>
Internal cache
<dl>
<dd>
486 processor
<dl>
<dd>effect on optimization, 236</dd>
<dd>timing code, 246</dd>
</dl>
</dd>
<dd>
Pentium processor
<dl>
<dd>instruction fetching, 374</dd>
<dd>organization, 374-375</dd>
<dd>paired instructions, 391, 396</dd>
</dl>
</dd>
</dl>
</dd>
<dd>Internal indexing, VGA, 427-429</dd>
<dd>
Internet support
<dl>
<dd>Quake 2, 1293</dd>
<dd>QuakeWorld, 1291</dd>
</dl>
</dd>
<dd>
Interrupts
<dl>
<dd>DAC, loading, 643, 648</dd>
<dd>Divide By Zero interrupt, 181</dd>
<dd>and <b>IRET</b> instruction, 227</dd>
<dd>and long-period Zen timer, 53, 66</dd>
<dd>and page flipping, 446</dd>
<dd>and <b>POPF</b> instruction, 226</dd>
<dd>and Zen timer, 43, 45-46</dd>
</dl>
</dd>
<dd>Intersecting lines, 1121-1123</dd>
<dd>Intersecting span sorting, 1228-1229</dd>
<dd>Intuitive leaps, 1098</dd>
<dd><b>IRET</b> instruction, vs. <b>POPF</b> instruction, 226-231</dd>
<dd>IRQ0 interrupts, and Zen timer, 45</dd>
<dd><b>IS_VGA</b> equate, 572, 575</dd>
<dd><big><b>J</b></big></dd>
<dd>Jet Propulsion Lab, color perception research, 1035</dd>
<dd><b>JMP $+2</b> instructions, 558, 632</dd>
<dd><b>JMP DWORD PTR</b> instruction, 186-187</dd>
<dd>Jumps, to absolute addresses, 186-187</dd>
<dd><big><b>K</b></big></dd>
<dd>Kennedy, John, 171-172</dd>
<dd>
Kent, Jim
<dl>
<dd>dynamic palette adjustment, 1039</dd>
<dd>monotone-vertical polygons, filling, 760-761</dd>
</dl>
</dd>
<dd>
Kissing, learning to,
<dl>
<dd>281-282</dd>
</dl>
</dd>
<dd>Kitchen floor story, 261-262</dd>
<dd>Klerings, Peter, 350</dd>
<dd>Knuth, Donald, 323</dd>
<dd><big><b>L</b></big></dd>
<dd><b>LAHF</b> instruction, 148</dd>
<dd>
Large code model
<dl>
<dd>linking Zen timer, 71</dd>
<dd>optimizing assemblers, 71-72</dd>
</dl>
</dd>
<dd>
Latches
<dl>
<dd>and bit mask, 470</dd>
<dd>and Color Don&rsquo;t Care register, <b>535-537,</b> 535</dd>
<dd>and CPU reads, 530</dd>
<dd>drawing solid text, 1039-1041, <b>1042-1044</b></dd>
<dd>
Mode X
<dl>
<dd>copying pixels, <b>905-907,</b> 908, <b>909-911</b></dd>
<dd>loading, with double copying process, 903</dd>
<dd>masked copying, 918-919, 919-921, <b>922-923</b></dd>
<dd>pattern fills, 899, <b>900-903,</b> 903-904</dd>
</dl>
</dd>
<dd>overview, 452-453, 897-898</dd>
</dl>
</dd>
<dd>Latency, in QuakeWorld, 1291-1292</dd>
<dd>
<b>LEA</b> instruction
<dl>
<dd>vs. <b>ADD,</b> 130, 170-171</dd>
<dd>multiplication operations, 132-133, 172, 375-376</dd>
<dd>
32-bit registers
<dl>
<dd>addition, 131</dd>
<dd>multiplication, 132-133</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
<b>LEAVE</b> instruction
<dl>
<dd>486 processor, 241-242</dd>
<dd>Pentium processor, 377</dd>
<dd>286 processor, 221</dd>
</dl>
</dd>
<dd>Level performance, 1213-1214</dd>
<dd>Life, Game of. <i>See</i> Game of Life.</dd>
<dd>
Lighting
<dl>
<dd><i>See also</i> Shading.</dd>
<dd>
Gouraud shading
<dl>
<dd>overview, 1246-1247</dd>
<dd>perspective correction, 1248-1250</dd>
<dd>problems with, 1247-1250</dd>
</dl>
</dd>
<dd>intensity, calculating, 1137</dd>
<dd>overlapping lights, 1247</dd>
<dd>perspective correctness, 1248-1250</dd>
<dd>in Quake 3-D engine, 1282-1283</dd>
<dd>rotational variance, 1249</dd>
<dd>
surface-based lighting
<dl>
<dd>description, 1250-1251</dd>
<dd>mipmapping, 1254-1255</dd>
<dd>performance, 1251-1253</dd>
<dd>surface caching, 1253-1256, 1260-1262</dd>
</dl>
</dd>
<dd>two-pass approach, 1262</dd>
<dd>viewing variance, 1249</dd>
</dl>
</dd>
<dd>Limits, transcending, in creative design, 1179-1180</dd>
<dd>Lindley, Bill, 854-855</dd>
<dd>LINE1 macro, <b>672-674</b></dd>
<dd>LINE2 macro, <b>674-675</b></dd>
<dd>Line Compare register, 565</dd>
<dd>
Line segments
<dl>
<dd>clipping to planes, 1195-1197</dd>
<dd>representation, 1195, <b>1196</b></dd>
</dl>
</dd>
<dd>Linear addressing, VGA, 430</dd>
<dd>Linear-time sorting, 1099</dd>
<dd>
<b>LineDraw</b> function
<dl>
<dd>assembly implementation, <b>699-704,</b> 704-706</dd>
<dd>C-language implementation, <b>688-691</b></dd>
</dl>
</dd>
<dd>
Line-drawing algorithms
<dl>
<dd>accumulated pixels approach (Jim Mackraz), 678</dd>
<dd>
Bresenham&rsquo;s algorithms
<dl>
<dd>basic line-drawing algorithm, 655-661, <b>661-665,</b> 665-671, <b>671-677</b></dd>
<dd>run-length slice algorithm, 683-693, <b>698-704,</b> 705</dd>
</dl>
</dd>
<dd>characteristics of, 656-657</dd>
<dd>run-length slice algorithm, 683-693, <b>698-704,</b> 705</dd>
<dd>Wu antialiasing algorithm, 776-779, <b>780-791,</b> 791-792</dd>
</dl>
</dd>
<dd>Line-drawing demo program, <b>615-618,</b> 618-619</dd>
<dd><b>LineIntersectPlane</b> function, <b>1142-1143</b></dd>
<dd>
Lines
<dl>
<dd>
drawing
<dl>
<dd><i>See also</i> Line-drawing algorithms.</dd>
<dd>color-patterned lines demo program, <b>509-515</b></dd>
<dd>320<i>See also</i> Restartable blocks.400 256-color mode, 600</dd>
<dd>write mode 2, 509</dd>
</dl>
</dd>
<dd>intersecting, 1121-1123</dd>
<dd>
parametric lines
<dl>
<dd>clipping, 1121-1123</dd>
<dd>overview, 1119-1120</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
Linked lists
<dl>
<dd>basic implementation, 283-285</dd>
<dd>circular lists, 288-292</dd>
<dd>dummy nodes, 285-287</dd>
<dd>head pointers, 284, 285</dd>
<dd><b>InsertNodeSorted</b> assembly routine, <b>290</b></dd>
<dd>overview, 282</dd>
<dd>sentinels, 285-287</dd>
<dd>sorting techniques, 755</dd>
<dd>tail nodes, 286</dd>
<dd>test-bed program, <b>291</b></dd>
</dl>
</dd>
<dd>Little endian format, 252</dd>
<dd>
Local optimization
<dl>
<dd><i>See also</i> Assembly language optimization; Optimization.</dd>
<dd>bit flipping and flags, 146-147</dd>
<dd>defined, 140</dd>
<dd>incrementing and decrementing, 147-148</dd>
<dd>lookup tables, 145-146</dd>
<dd>unrolling loops, 143-145, 305, 312, 377-378, 410</dd>
</dl>
</dd>
<dd><b>LOCK</b> instruction, 377</dd>
<dd>Lockstep execution, Pentium processor, 390-394, 400-403</dd>
<dd><b>LODSB</b> instruction, 304, 312</dd>
<dd><b>LODSD</b> instruction, 171</dd>
<dd><b>LODSW</b> instruction, 312</dd>
<dd>Logical functions, ALU, 458</dd>
<dd>Logical height, virtual screen, 442</dd>
<dd>Logical width, virtual screen, 442</dd>
<dd>
Long-period Zen timer
<dl>
<dd><i>See also</i> Zen timer.</dd>
<dd>calling from C code, 69-72</dd>
<dd>and interrupts, 53</dd>
<dd>LZTEST.ASM listing, <b>66-67</b></dd>
<dd>LZTIME.BAT listing, <b>67-68</b></dd>
<dd>LZTIMER.ASM listing, <b>55-65</b></dd>
<dd>overview, 53</dd>
<dd><b>PS2</b> equate, 65-66</dd>
<dd>system clock inaccuracies, 43, 45-46, 48</dd>
<dd>test-bed program, 66-69</dd>
<dd>TESTCODE listing, <b>69</b></dd>
<dd><b>ZTimerOff</b> subroutine, <b>59-63</b></dd>
<dd><b>ZTimerOn</b> subroutine, <b>58-59</b></dd>
<dd><b>ZTimerReport</b> subroutine, <b>63-65</b></dd>
</dl>
</dd>
<dd>
Lookup tables
<dl>
<dd>CosSin subroutine, 994-996, 999</dd>
<dd>vs. rotating or shifting, 145-146</dd>
<dd>3-cell-per-word implementation, Game of Life, 365</dd>
<dd>
word count program
<dl>
<dd>author&rsquo;s implementation, 303, 304</dd>
<dd>David Stafford&rsquo;s implementation, <b>309-311,</b> 317-319</dd>
<dd>WC50 (Terje Mathisen), 307</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
<b>LOOP</b> instruction
<dl>
<dd><i>See also</i> Loops.</dd>
<dd>vs. <b>DEC/JNZ</b> sequence, 139, 140-141</dd>
<dd>and flags, 148</dd>
</dl>
</dd>
<dd>
Loops
<dl>
<dd><i>See also</i> <b>LOOP</b> instruction.</dd>
<dd>avoiding, 140</dd>
<dd>and branch prediction, Pentium processor, 377-378</dd>
<dd>unrolling, 143-145, 305, 312, 377-378, 410</dd>
<dd><big><b>M</b></big></dd>
</dl>
</dd>
<dd>Mackraz, Jim, 678</dd>
<dd>
Map Mask register
<dl>
<dd>demo program, <b>472-473</b></dd>
<dd>drawing text, 833</dd>
<dd>optimizing Mode X, 1074</dd>
<dd>vs. Read Map register, 526</dd>
<dd>selecting planes for CPU writes, 443-444, 471-472</dd>
<dd>with set/reset circuitry, 474</dd>
<dd>write mode 1, 443</dd>
</dl>
</dd>
<dd>Map Mask register demo program, <b>472-473</b></dd>
<dd>Mask register, blanking screen, 651</dd>
<dd>
Masked copying, Mode X
<dl>
<dd>clipping, 923</dd>
<dd>between display memory locations, 918-919, <b>919-921</b></dd>
<dd>image and mask alignments, generating, <b>922-923</b></dd>
<dd>performance, 924</dd>
<dd>system memory to display memory, <b>916-918,</b> 916</dd>
</dl>
</dd>
<dd>Masked images, 871-872</dd>
<dd>MASM (Microsoft Assembler), 187</dd>
<dd>
Math, 3-D
<dl>
<dd>cross products, 1139-1140</dd>
<dd>
dot products
<dl>
<dd>calculating, 1135-1137</dd>
<dd>calculating light intensity, 1137</dd>
<dd>projection, 1141-1142</dd>
<dd>rotation, 1143-1144</dd>
<dd>sign of, 1140-1141</dd>
<dd>of unit vectors, 1136</dd>
<dd>of vectors, 1135-1136</dd>
</dl>
</dd>
<dd>
matrix math
<dl>
<dd>assembly routines, 992, <b>996-999</b></dd>
<dd>C-language implementations, <b>974-976</b></dd>
<dd>normal vectors, calculating, 955-956</dd>
<dd>rotation of 3-D objects, 938-939, <b>943-944,</b> 948</dd>
<dd>transformation, optimized, 1172-1173, <b>1173-1174</b></dd>
</dl>
</dd>
<dd>vector length, 1135</dd>
</dl>
</dd>
<dd>Mathiew, Serge, 855-857</dd>
<dd>Mathisen, Terje, 250-252, 306, 319</dd>
<dd>
Matrices
<dl>
<dd>incremental transformations, 964</dd>
<dd>optimization of, 986, 1172-1173, <b>1173-1174</b></dd>
<dd>3-D rotation, representation of, 938-939</dd>
</dl>
</dd>
<dd>
Matrix math
<dl>
<dd>assembly routines, 992, <b>996-999</b></dd>
<dd>C-language implementations, <b>974-976</b></dd>
<dd>normal vectors, calculating, 955-956</dd>
<dd>rotation of 3-D objects, 938-939, <b>943-944,</b> 948</dd>
<dd>transformation, optimized, 1172-1173, <b>1173-1174</b></dd>
</dl>
</dd>
<dd>MDA (Monochrome Display Adapter), 104</dd>
<dd><b>Memchr()</b> function, 116</dd>
<dd><b>Memcmp()</b> function, 116</dd>
<dd><b>Memcpy()</b> function, 1147-1148</dd>
<dd>
Memory access
<dl>
<dd><i>See also</i> Display memory access.</dd>
<dd>clock cycles, bytes vs. words, 82, 83-85</dd>
<dd><b>DEC</b> instruction, 83</dd>
<dd>and DRAM refresh, 98</dd>
<dd>8-bit bus cycle-eater, 82</dd>
<dd>performance, 286 and 386 processors, 223-225</dd>
<dd>prefetch queue cycle-eater, 86</dd>
<dd>system wait states, 210-213</dd>
<dd>and wait states, 100</dd>
</dl>
</dd>
<dd>Memory addressing, 221</dd>
<dd>Memory addressing modes, and arithmetic operations, 130-133</dd>
<dd>
Memory allocation
<dl>
<dd>display memory, 903-904</dd>
<dd>page flipping, 834</dd>
</dl>
</dd>
<dd>Memory locations, pushing and popping, 254-255</dd>
<dd>
Memory variables
<dl>
<dd>data alignment, 213-215</dd>
<dd>8088 processor, optimization, 83-85</dd>
</dl>
</dd>
<dd>Memory-addressing instructions, 223-225</dd>
<dd><b>Memset()</b> C library function, 727</dd>
<dd>Miles, John, 1081, 1093</dd>
<dd>Mipmapping, 1254-1255</dd>
<dd>Mode 12H (hi-res mode), 851-855</dd>
<dd>Mode 13H, 515, 590</dd>
<dd>Mode Control register, 575</dd>
<dd>
Mode register
<dl>
<dd>color paging, 628-629</dd>
<dd>256-color modes, 629</dd>
</dl>
</dd>
<dd>
Mode X
<dl>
<dd><i>See also</i> X-Sharp 3-D animation package.</dd>
<dd>
animation demo programs
<dl>
<dd>page-flipped animation, 924-925, <b>925-930</b></dd>
<dd>3-D polygon rotation, 939, <b>940-945,</b> 948</dd>
</dl>
</dd>
<dd>bitmap organization, 882-883</dd>
<dd>features, 878-879</dd>
<dd>
<b>FillRectangleX</b> subroutine
<dl>
<dd>four-plane parallel processing, 888-891, <b>891-893</b></dd>
<dd>pixel-by-pixel plane selection, <b>885-887</b></dd>
<dd>plane-by-plane processing, <b>887-889</b></dd>
</dl>
</dd>
<dd>four-plane parallel processing, 888-891, <b>891-893</b></dd>
<dd>
latches
<dl>
<dd>copying pixels, <b>905-907,</b> 908, <b>909-911</b></dd>
<dd>loading, with double copying process, 903</dd>
<dd>overview, 897-898</dd>
<dd>pattern fills, 899, 900-903, 903-904</dd>
</dl>
</dd>
<dd>
masked copying
<dl>
<dd>animation demo program, 924-925, <b>925-930</b></dd>
<dd>clipping, 923</dd>
<dd>between display memory locations, 918-919, <b>919-921</b></dd>
<dd>image and mask alignments, generating, <b>922-923</b></dd>
<dd>performance, 924</dd>
<dd>system memory to display memory, <b>916-918,</b> 916</dd>
</dl>
</dd>
<dd>memory allocation, 903-904</dd>
<dd>mode set routine, <b>880-881,</b> 882</dd>
<dd>optimization, 1074</dd>
<dd>pattern fills, 899, <b>900-903,</b> 903-904</dd>
<dd>pixel access and hardware planes, 1082</dd>
<dd><b>ReadPixelX</b> subroutine, <b>884-885</b></dd>
<dd>vertical scanlines vs. horizontal, 1084-1086</dd>
<dd><b>WritePixelX</b> subroutine, <b>883-884</b></dd>
</dl>
</dd>
<dd><b>ModelColor</b> structure, <b>1035</b></dd>
<dd><b>ModelColorToColorIndex</b> function, 1036, <b>1038</b></dd>
<dd>Mod-R/M byte, 257</dd>
<dd>
Modular code
<dl>
<dd>and future of programming profession, 725-726</dd>
<dd>optimizing, 153</dd>
</dl>
</dd>
<dd>Monotone-vertical polygons, filling, 760-761, <b>761-771,</b> 771</dd>
<dd><b>MOV</b> instruction, 236, 377, 832</dd>
<dd><b>MoveBouncer</b> function, <b>824-825</b></dd>
<dd><b>MoveObject</b> function, <b>929</b></dd>
<dd>
<b>MoveXSortedToAET</b> function
<dl>
<dd>complex polygons, <b>749</b></dd>
<dd>monotone-vertical polygons, <b>770</b></dd>
</dl>
</dd>
<dd><b>MOVSD</b> instruction, 222, 386</dd>
<dd><b>MUL</b> instruction, 97, 173-174</dd>
<dd>
Multiplication
<dl>
<dd>increasing speed of, 173-174</dd>
<dd>using <b>LEA,</b> 132-133, 172</dd>
</dl>
</dd>
<dd>Multi-word arithmetic, 147-148</dd>
<dd><big><b>N</b></big></dd>
<dd><b>NEG</b> EAX instruction, 222</dd>
<dd>Negation, two&rsquo;s complement, 171</dd>
<dd><b>Next1</b> function, <b>353</b></dd>
<dd><b>Next2</b> function, <b>353</b></dd>
<dd><b>Next_generation</b> method, <b>327-328,</b> <b>335,</b> 336, 337-338, <b>344</b></dd>
<dd>Nonconvex objects, depth sorting, 1000, <b>1001-1002</b></dd>
<dd>
Normal vectors
<dl>
<dd>building BSP trees, 1106</dd>
<dd>calculating, 955-956</dd>
<dd>direction of, 1140</dd>
</dl>
</dd>
<dd>Normals. <i>See</i> Normal vectors.</dd>
<dd><b>NOSMART</b> assembler directive, 72</dd>
<dd><b>NOT</b> instruction, 146-147, 147</dd>
<dd><big><b>O</b></big></dd>
<dd>Object collisions, detecting, <b>531-534</b></dd>
<dd>Object space, 935, 1135</dd>
<dd>Object-oriented programming, 725-726</dd>
<dd>
<b>Octant0</b> function
<dl>
<dd>360x480 256-color mode line drawing demo program, <b>615</b></dd>
<dd>Bresenham&rsquo;s line-drawing algorithm, <b>662,</b> 668-669</dd>
</dl>
</dd>
<dd>
<b>Octant1</b> function
<dl>
<dd>360x480 256-color mode line drawing demo program, <b>616</b></dd>
<dd>Bresenham&rsquo;s line-drawing algorithm, <b>663,</b> 668-669</dd>
</dl>
</dd>
<dd>Octants, and line orientations, 666-667</dd>
<dd>
1/z sorting
<dl>
<dd>abutting span sorting, 1229-1230</dd>
<dd><b>AddPolygonEdges</b> function, <b>1232-1233,</b> 1238</dd>
<dd>vs. BSP-order sorting, 1226-1227</dd>
<dd>calculating 1/z value, 1220-1222</dd>
<dd><b>ClearEdgeLists</b> function, <b>1236-1237</b></dd>
<dd>DrawSpans function, 1236</dd>
<dd>independent span sorting, 1230, <b>1231-1238,</b> 1239-1241</dd>
<dd>intersecting span sorting, 1228-1229</dd>
<dd><b>PolyFacesViewer</b> function, <b>1232</b></dd>
<dd>reliability, 1227</dd>
<dd><b>ScanEdges</b> function, <b>1234-1236,</b> 1238-1239</dd>
<dd><b>UpdateWorld</b> function, <b>1237-1238</b></dd>
</dl>
</dd>
<dd>On-screen object collisions, detecting, <b>531-534</b></dd>
<dd>OpenGL API, GLQuake, 1288-1290</dd>
<dd>Operands, order of, 173-174</dd>
<dd><b>OPT2.ASM</b> listing, <b>313-315</b></dd>
<dd>
Optimization
<dl>
<dd><i>See also</i> Assembly language optimization; Local optimization.</dd>
<dd>32-bit registers, 187</dd>
<dd>and abstraction, 330-332, 345-346</dd>
<dd>and application parameters, 122</dd>
<dd>assemblers, optimizing, 71-72</dd>
<dd>avoiding thinking like a compiler, 152, 154-155</dd>
<dd>and biased perceptions, 1080, 1085</dd>
<dd>breakthrough level, 316</dd>
<dd>BSP trees, 1128-1129</dd>
<dd>buffer-filling routine, 416-420</dd>
<dd>C library functions, 15</dd>
<dd>
compiler-based
<dl>
<dd>data recursion vs. code recursion, 1112-1113</dd>
<dd>on vs. off, 9</dd>
</dl>
</dd>
<dd>data recursion, 1108-1113</dd>
<dd>data structures, 155-166</dd>
<dd>disk caches, 19</dd>
<dd>display adapter cycle-eater, 107</dd>
<dd>DRAM refresh, 98-99</dd>
<dd>8-bit bus cycle-eater, 83-85</dd>
<dd>fine-tuning existing code, 312-313</dd>
<dd>
floating point operations
<dl>
<dd>clock cycles, core instructions, 1167-1168</dd>
<dd>cross product optimization, 1171, <b>1172</b></dd>
<dd>dot product optimization, 1170, 1171</dd>
<dd><b>FXCH</b> instruction, 1169-1170</dd>
<dd>interleaved instructions, 1169-1170</dd>
<dd>matrix transformation optimization, 1172-1173, <b>1173-1174</b></dd>
<dd>overview, 1167-1170</dd>
<dd>pipelining, 1168-1170</dd>
<dd>projection to screen space, 1174</dd>
<dd>rounding control, 1174-1175</dd>
</dl>
</dd>
<dd>
486 processor
<dl>
<dd>addressing pipeline penalty, 238-240, 243, 250-252</dd>
<dd>internal cache, 236</dd>
<dd>vs. Pentium processor, 378-379</dd>
<dd>pushing and popping, 254-255</dd>
<dd>reference materials, 236</dd>
<dd>shift and rotate instructions, 255-256</dd>
<dd>single cycle, importance of, 238</dd>
<dd>stack addressing, 241-242</dd>
</dl>
</dd>
<dd>general rules, 223</dd>
<dd>generality, decreasing, 335</dd>
<dd>hardware efficiency, 1084-1086</dd>
<dd>knowing when to stop, 735</dd>
<dd>local optimization, 138-148</dd>
<dd>Mode X, 1074</dd>
<dd>modular code, 153</dd>
<dd>objectives and rules, 7-19, 156</dd>
<dd>pattern matching, 191-192, 202</dd>
<dd>
Pentium processor
<dl>
<dd>and branch prediction, 378</dd>
<dd>code size and performance, 390</dd>
<dd>floating point operations, 1167-1175</dd>
<dd>interleaving operations, 394-395</dd>
<dd>pairing instructions, 390-394</dd>
<dd>pixel-drawing code, 1086</dd>
<dd>prefix bytes, 376, 395, 407</dd>
<dd>reference material, 374</dd>
<dd>superscalar execution, 384-396</dd>
<dd>vs. 386 and 486 processors, 378-379, 384</dd>
</dl>
</dd>
<dd>perspective on problem, changing, 315-316, 1084</dd>
<dd>pixel drawing, 1074</dd>
<dd>pointer advancement optimization, 1086-1089, <b>1090-1091,</b> 1092-1093</dd>
<dd>prefetch queue cycle-eater, 93</dd>
<dd>problem definition, changing, 332</dd>
<dd>rearranging instructions, 418-419</dd>
<dd>reducing size of code, 416-418</dd>
<dd>redundant calculations, 682-683</dd>
<dd>re-examining problem, 338-339</dd>
<dd>register variables, 338</dd>
<dd>restartable blocks, 118</dd>
<dd>sorting techniques, 755</dd>
<dd>stack addressing, 420</dd>
<dd>sufficient, 312</dd>
<dd>
superscalar execution
<dl>
<dd>initial pipe, effect of, 405</dd>
<dd>overview, 384-386</dd>
<dd>pairable instructions, 388</dd>
<dd>V-pipe-capable instructions, 386-387</dd>
</dl>
</dd>
<dd>
texture-mapping optimization
<dl>
<dd>inner-loop optimizations, <b>1069-1073,</b> 1074, 1081-1084</dd>
<dd>instruction-by-instruction optimizations, 1086-1092</dd>
<dd>pointer advancement optimization, 1086-1089, <b>1090-1091</b></dd>
<dd>vertical scanlines, 1084-1086</dd>
</dl>
</dd>
<dd>32-bit fixed-point arithmetic, 1086-1089, 1090-1091, 1092-1093</dd>
<dd>32-bit instructions, 1091</dd>
<dd>386 processor, 378-379</dd>
<dd>time vs. space tradeoff, 187</dd>
<dd>transformation inefficiencies, 25-26</dd>
<dd>transformation matrices, 986</dd>
<dd>understanding data, importance of, 122, 175, 180, 305</dd>
<dd>understanding how things work, 726</dd>
<dd>unifying model, developing, 1110-1111</dd>
<dd>unrolling loops, 143-145, 410</dd>
<dd>using restartable blocks, 118</dd>
<dd>and VGA memory speed, 704-705</dd>
</dl>
</dd>
<dd>Optimized searching, 174-180</dd>
<dd>Optimizing assemblers, 71-72</dd>
<dd><b>OR</b> instruction, 377</dd>
<dd>Orientation-independent texture mapping, 1065-1066, <b>1067</b></dd>
<dd>
<b>OUT</b> instruction
<dl>
<dd>clock cycles, 1082-1083</dd>
<dd>loading DAC, 640, 642-643</dd>
<dd>loading palette RAM or DAC registers, 632</dd>
<dd>performance, 444, 843</dd>
<dd>word-<b>OUT</b> vs. byte-<b>OUT,</b> 429, 479</dd>
<dd>vs. write mode 3, 483-484</dd>
</dl>
</dd>
<dd><b>OUTS</b> instruction, 221</dd>
<dd>OUT_WORD macro, <b>566,</b> 594</dd>
<dd>
Overdraw problem, VSD
<dl>
<dd>and beam trees, 1185-1186</dd>
<dd>painter&rsquo;s algorithm, 1184-1185</dd>
<dd>sorted spans, 1215</dd>
</dl>
</dd>
<dd>Overflow register, split screen operation, 565</dd>
<dd>
Overhead
<dl>
<dd>
DOS function calls
<dl>
<dd>in 16-bit checksum program, 12</dd>
<dd>in search engine, 121</dd>
</dl>
</dd>
<dd><b>memcmp()</b> function, 116</dd>
<dd><b>strstr()</b> function, 115</dd>
<dd>of Zen timer, timing, 46, 72</dd>
</dl>
</dd>
<dd>Overlapping rectangles, in dirty-rectangle animation, 872-873</dd>
<dd>Overscan, 555-556, 641</dd>
<dd><big><b>P</b></big></dd>
<dd>
Page flipping
<dl>
<dd>and bit-plane animation, 814</dd>
<dd>color cycling, 650</dd>
<dd>vs. dirty-rectangle animation, 846, 862</dd>
<dd>display memory start address, changing, 857</dd>
<dd>mechanics of, 833-836</dd>
<dd>memory allocation, 834, 903-904</dd>
<dd>overview, 444-446</dd>
<dd>single-page technique, 855-857</dd>
<dd>640x480 mode, 836-837</dd>
<dd>with split screen, 836-837</dd>
<dd>320x400 256-color mode, <b>600-605</b></dd>
<dd>timing updates, 835-836</dd>
<dd>VGA mode 12H (hi-res mode), 851-855</dd>
</dl>
</dd>
<dd>
Page flipping animation demo programs
<dl>
<dd>Mode X, 924-925, <b>925-930</b></dd>
<dd>split screen and page flipping, <b>820-825,</b> <b>825-830,</b> 836-837</dd>
<dd>320x400 256-color mode, <b>600-605</b></dd>
</dl>
</dd>
<dd>
Painter&rsquo;s algorithm
<dl>
<dd><i>See also</i> 3-D animation; 3-D drawing.</dd>
<dd>and BSP trees, 1099, 1104-1105</dd>
<dd>overdraw problem, 1184-1185</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
<dd>Pairable instructions, Pentium processor, 388</dd>
<dd>Palette adjustment, dynamic, 1039</dd>
<dd>
Palette RAM
<dl>
<dd><i>See also</i> Palette registers.</dd>
<dd>color paging, 628-629</dd>
<dd>setting registers, 629-630, 631-632</dd>
<dd>VGA color path, 626</dd>
</dl>
</dd>
<dd>
Palette registers
<dl>
<dd><i>See also</i> Palette RAM.</dd>
<dd>EGA, 549-550</dd>
<dd>setting for bit-plane animation, 799-801, 811-813</dd>
</dl>
</dd>
<dd>
Panning
<dl>
<dd>byte-by-byte vs. pixel-by-pixel, 574</dd>
<dd>overview, 441-442</dd>
<dd>in split screens, 574-575, <b>575-582,</b> 582-583</dd>
<dd>in text mode, 442</dd>
</dl>
</dd>
<dd><b>PanRight</b> subroutine, <b>582</b></dd>
<dd>
Parametric lines
<dl>
<dd>clipping, 1121-1123</dd>
<dd>overview, 1119-1120</dd>
</dl>
</dd>
<dd>Particles, Quake 3-D engine, 1287</dd>
<dd>Pattern fills, 899, 900-903, 903-904</dd>
<dd>Pattern matching, 191-192, 202</dd>
<dd>PC compatibility, Zen timer, 48-49</dd>
<dd>Pel panning. <i>See</i> Panning.</dd>
<dd>Pel Panning register, 574, 583</dd>
<dd>
Pentium processor
<dl>
<dd>AGIs (Address Generation Interlocks), 400-403</dd>
<dd>alignment, 376</dd>
<dd>branch instructions, pairing, 404-405</dd>
<dd>branch prediction, 377-378</dd>
<dd>bus, locking, 377</dd>
<dd>cache lines, 374</dd>
<dd>code size and performance, 390</dd>
<dd>data cache and paired instructions, 391</dd>
<dd>display adapter cycle-eater, 107</dd>
<dd>EA (effective address) calculations, 375-376</dd>
<dd>
floating point optimization
<dl>
<dd>clock cycles, core instructions, 1167-1168</dd>
<dd>cross product optimization, 1171, <b>1172</b></dd>
<dd>dot product optimization, 1170, <b>1171</b></dd>
<dd><b>FXCH</b> instruction, 1169-1170</dd>
<dd>interleaved instructions, 1169-1170</dd>
<dd>matrix transformation optimization, 1172-1173, <b>1173-1174</b></dd>
<dd>overview, 1167-1170</dd>
<dd>pipelining, 1168-1170</dd>
<dd>projection to screen space, 1174</dd>
<dd>rounding control, 1174-1175</dd>
</dl>
</dd>
<dd>FPU pipelining, 1168-1170</dd>
<dd>instruction fetching, 374</dd>
<dd>internal cache, 374-375, 396</dd>
<dd><b>LAHF</b> and <b>SAHF</b> instructions, 148</dd>
<dd><b>LEA</b> vs. <b>ADD</b> instructions, 131</dd>
<dd><b>LODSB</b> instruction, 304</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd><b>MOV</b> vs. <b>XCHG</b> instructions, 377</dd>
<dd>
optimization
<dl>
<dd>pairing instructions, 390-394</dd>
<dd>pixel-drawing code, 1086</dd>
<dd>reference material, 374</dd>
</dl>
</dd>
<dd>overview, 373-375</dd>
<dd>
pipeline stalls
<dl>
<dd>FPU, 1168-1170</dd>
<dd>overview, 375</dd>
<dd>texture-mapping code, 1092</dd>
</dl>
</dd>
<dd>prefix bytes, 376, 395, 407</dd>
<dd>running Pentium code on 386 or 486, 411</dd>
<dd>
superscalar execution
<dl>
<dd>initial pipe, effect of, 405</dd>
<dd>interleaving operations, 394-395</dd>
<dd>internal cache, 396</dd>
<dd>lockstep execution, 390-394, 400-403</dd>
<dd>overview, 384-386</dd>
<dd>pairable instructions, 388</dd>
<dd>prefix bytes, 395</dd>
<dd>register contention, 403-405</dd>
<dd>registers, small set, 395</dd>
</dl>
</dd>
<dd>U-pipe, 385-386</dd>
<dd>V-pipe, 385-386, 386-387</dd>
<dd><b>XCHG</b> vs. <b>MOV</b> instructions, 377, 832</dd>
</dl>
</dd>
<dd><i>Pentium Processor Optimization Tools</i> (book), 1148</dd>
<dd>
Performance
<dl>
<dd><i>See also</i> Assembly language optimization; Clock cycles; Cycle-eaters; Local optimization; Optimization; Zen timer.</dd>
<dd>and abstraction, 330-332, 345-346</dd>
<dd>beam trees, 1186</dd>
<dd>Boyer-Moore algorithm, 266-268</dd>
<dd>branching, 140</dd>
<dd>BSP (Binary Space Partitioning) trees, 1100, 1111-1113</dd>
<dd>bubble sort, 755</dd>
<dd>complex polygons, filling, 753</dd>
<dd>dirty-rectangle animation, 873</dd>
<dd>display adapter cycle-eater, 221</dd>
<dd>DRAM refresh, 97</dd>
<dd>function calls, 153</dd>
<dd>
Game of Life
<dl>
<dd>byte-per-cell implementation, 340</dd>
<dd>cellmap-wrapped implementation, 332, 338</dd>
<dd>challenge results, 351</dd>
<dd>general analysis, 329-330</dd>
</dl>
</dd>
<dd>and generality, 335</dd>
<dd>level performance, 1213-1214</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd>masked copying, Mode X, 924</dd>
<dd>measuring, importance of, 34, 396</dd>
<dd>memory access, 223-225</dd>
<dd><b>OUT</b> instruction, 444</dd>
<dd><b>OUT</b> instructions, 843</dd>
<dd>PC-compatible computers, 48-49</dd>
<dd>polygon-filling implementations, 728</dd>
<dd>precalculated potentially visible set (PVS), 1213-1214</dd>
<dd>profiling and 80x87 emulator, Borland C++, 999</dd>
<dd>stack frames, 153</dd>
<dd>SuperVGA, with 486 processor, 842-844</dd>
<dd>texture mapping, 1074-1074</dd>
<dd>3-D polygon rotation demo programs, 949</dd>
<dd>360x480 256-color mode, 618</dd>
<dd>320x400 256-color mode, 599-600</dd>
<dd>time-critical code, 13</dd>
<dd>vertical scanlines in texture mapping, 1084</dd>
<dd>video performance, 104</dd>
<dd>Wu antialiasing algorithm, 777-778</dd>
<dd>z-buffers, 1213</dd>
</dl>
</dd>
<dd>Perspective correction in texture mapping, 1093</dd>
<dd>Perspective correctness problem, Gouraud shading, 1248-1250</dd>
<dd>
Perspective projection, 937, 1135
<dl>
<dd><i>See also</i> Projection.</dd>
</dl>
</dd>
<dd>
Pipeline stalls, Pentium processor, 375
<dl>
<dd><i>See also</i> Addressing pipeline penalty; AGIs (Address Generation Interlocks).</dd>
</dl>
</dd>
<dd>
Pipelining
<dl>
<dd>
486 processor
<dl>
<dd>addressing pipeline penalty, 238-240, 250</dd>
<dd>stack addressing, 241-242</dd>
</dl>
</dd>
<dd>FPU, Pentium processor, 1168-1170</dd>
</dl>
</dd>
<dd>Pitch angle, in polygon clipping, 1206</dd>
<dd>Pixel bits, rotating, 252</dd>
<dd>
Pixel drawing
<dl>
<dd><i>See also</i> Pixels.</dd>
<dd><b>EVGADot</b> function, <b>661-662,</b> 669-670</dd>
<dd>optimization, 1074, 1086</dd>
<dd>painter&rsquo;s algorithm and overdraw problem, 1184</dd>
</dl>
</dd>
<dd>Pixel intensity calculations, Wu&rsquo;s antialiasing algorithm, 778-779</dd>
<dd>Pixel values, mapping to colors, 548-551, <b>551-555</b></dd>
<dd>
Pixels
<dl>
<dd><i>See also</i> Boundary pixels, polygons; Pixel drawing.</dd>
<dd>copying, using latches (Mode X), <b>905-907,</b> 908, <b>909-911</b></dd>
<dd>reading (320x400 256-color mode), 599</dd>
<dd>redrawing, display adapter cycle-eater, 102</dd>
<dd>rotating bits, 252</dd>
<dd>writing (320x400 256-color mode), 599, 600</dd>
</dl>
</dd>
<dd>Plane mask, 1074</dd>
<dd>Plane-manipulation demo program, <b>476-478</b></dd>
<dd>
Planes
<dl>
<dd>clipping line segments to, 1195-1197</dd>
<dd>1/z value, calculating, 1221</dd>
<dd>representation, <b>1196</b></dd>
</dl>
</dd>
<dd>
Planes, VGA
<dl>
<dd><i>See also</i> Bit-plane animation.</dd>
<dd>ALUs and latches, 451-453</dd>
<dd>and bit mask, 465</dd>
<dd>capturing and restoring screens, 541-542, <b>543-547,</b> 547-548</dd>
<dd>and Color Don&rsquo;t Care register, 534-535, <b>535-537</b></dd>
<dd>fonts, in text modes, 516</dd>
<dd>manipulating, 443-444, 476-478</dd>
<dd>and Map Mask register, 471-472</dd>
<dd>
Mode X
<dl>
<dd>bitmap organization, 882-883</dd>
<dd>four-plane parallel processing, 888-891, <b>891-893</b></dd>
<dd>pixel-by-pixel plane selection, <b>885-887</b></dd>
<dd>plane-by-plane processing, <b>887-889</b></dd>
</dl>
</dd>
<dd>Mode X pixel access, 1082</dd>
<dd>overview, 430</dd>
<dd>and Read Map register, 542</dd>
<dd>read mode 0, 525-526</dd>
<dd>and set/reset circuitry, 471-478</dd>
<dd>setting all to single color, 473-474</dd>
<dd>single-color drawing with write mode 3, 831-832</dd>
<dd>write mode 2, 502-504, 509</dd>
</dl>
</dd>
<dd>Pohl, Frederick, 1275</dd>
<dd>Pointer advancement optimization, 1086-1089, <b>1090-1091,</b> 1092-1093</dd>
<dd>Pointer arithmetic, 171</dd>
<dd>Points, representation of, <b>1196</b></dd>
<dd><b>PolyFacesViewer</b> function, <b>1203,</b> 1232</dd>
<dd>
Polygon clipping
<dl>
<dd><b>BackRotateVector</b> function, <b>1203</b></dd>
<dd>clipping to frustum, 1200, <b>1201-1206,</b> 1206-1207</dd>
<dd><b>ClipToFrustum</b> function, <b>1204</b></dd>
<dd><b>ClipToPlane</b> function, <b>1199</b></dd>
<dd>optimization, 1207</dd>
<dd>overview, 1197-1200</dd>
<dd><b>PolyFacesViewer</b> function, <b>1203</b></dd>
<dd><b>ProjectPolygon</b> function, <b>1201</b></dd>
<dd><b>SetUpFrustum</b> function, <b>1204</b></dd>
<dd><b>SetWorldspace</b> function, <b>1204</b></dd>
<dd><b>TransformPoint</b> function, <b>1203</b></dd>
<dd><b>TransformPolygon</b> function, <b>1203</b></dd>
<dd><b>UpdateViewPos</b> function, <b>1202</b></dd>
<dd><b>UpdateWorld</b> function, <b>1205</b></dd>
<dd>viewspace clipping, 1207</dd>
<dd><b>ZSortObjects</b> function, <b>1201</b></dd>
</dl>
</dd>
<dd>
POLYGON.H header file
<dl>
<dd>complex polygons, <b>751</b></dd>
<dd>monotone-vertical polygons, filling, <b>771</b></dd>
<dd>non-overlapping convex polygons, <b>719-720</b></dd>
<dd>texture mapped polygons, <b>1054</b></dd>
<dd>3-D polygon rotation, <b>945-946</b></dd>
<dd>3-D solid cube rotation program, <b>965</b></dd>
<dd>X-Sharp 3-D animation package, <b>982-984</b></dd>
</dl>
</dd>
<dd>Polygon models, Quake 3-D engine, 1285-1286</dd>
<dd>
Polygon-filling programs
<dl>
<dd><i>See also</i> Polygons, filling.</dd>
<dd>complex polygons, 742-744, <b>745-752,</b> 753, <b>754,</b> 755-756</dd>
<dd>monotone-vertical polygons, 760, <b>761-771</b></dd>
<dd>
non-overlapping convex polygons
<dl>
<dd>assembly implementations, 732-733, <b>733-734,</b> <b>735-739</b></dd>
<dd>C-language implementations, <b>713-720,</b> 720-721, <b>729-732</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd>PolygonIsMonotoneVertical function, 761</dd>
<dd>
Polygons
<dl>
<dd><i>See also</i> Texture mapping.</dd>
<dd>adjacent, and 1/z span sorting, 1230</dd>
<dd>backface removal, 954-957, 1160-1161</dd>
<dd>categories of, 710, 742, 759-760</dd>
<dd>clipping, 1158-1159</dd>
<dd>Gouraud shading, 1247</dd>
<dd>hidden surface removal, 1214-1222</dd>
<dd>normal vector, calculating, 955-956</dd>
<dd>projection in 3-D space, 937, <b>944-945,</b> 948</dd>
<dd>representation, <b>1196</b></dd>
<dd>
3-D polygon rotation demo program
<dl>
<dd>matrix multiplication functions, <b>943-944,</b> 948</dd>
<dd>overview, 939</dd>
<dd>performance, 949</dd>
<dd>polygon filling with clipping support, <b>940-943</b></dd>
<dd>transformation and projection, <b>944-945,</b> 948</dd>
</dl>
</dd>
<dd>transformation to 3-D space, 935</dd>
<dd>unit normal, calculating, 1027-1028, 1137-1140</dd>
<dd>visibility, calculating, 955-956</dd>
<dd>
visible surface determination (VSD)
<dl>
<dd>beam trees, 1185-1189</dd>
<dd>overdraw problem, 1184-1185</dd>
<dd>polygon culling, 1181-1184</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
<dd>visible surface determination (VSD)culling to frustum, 1181-1184</dd>
<dd>wall orientation testing, BSP tree rendering, 1160-1161</dd>
</dl>
</dd>
<dd>
Polygons, filling
<dl>
<dd><i>See also</i> Polygon-filling programs; Polygons; Texture mapping.</dd>
<dd>active edges, 742-744, 753, 755, 756</dd>
<dd>boundary pixels, selecting, 712</dd>
<dd>with clipping support, 940-943</dd>
<dd>complex polygons, 742</dd>
<dd>drawing, speeding up, 727-729</dd>
<dd>
edge tracing
<dl>
<dd>overview, 711-713</dd>
<dd><b>ScanEdge</b> function, <b>716-717,</b> 720-721, <b>730-732,</b> <b>735-738</b></dd>
</dl>
</dd>
<dd>fitting adjacent polygons, 712-713</dd>
<dd>flat vs. pointed top, 720</dd>
<dd>integer vs. fixed-point arithmetic, 1065</dd>
<dd>in Mode X, <b>940-943</b></dd>
<dd>monotone-vertical polygons, 760-761, 771</dd>
<dd>nonconvex polygons, 755</dd>
<dd>non-overlapping convex polygons, 720-721</dd>
<dd>performance, comparison of implementations, 728</dd>
<dd>rasterization, 710-712</dd>
<dd>
scan conversion, 710, 720-721
<dl>
<dd>active edges, 721, 742-744, 753, 755, 756</dd>
<dd>C-language implementation, <b>713-717,</b> 720-721</dd>
<dd>defined, 710</dd>
<dd>zero-length segments, 721</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
Polyhedrons
<dl>
<dd>hidden surfaces, 955, 1000, <b>1001-1002</b></dd>
<dd>representation of, 962</dd>
<dd>
3-D solid cube rotation demo program
<dl>
<dd>basic implementation, <b>957-961,</b> 962-963</dd>
<dd>incremental transformations, <b>964-966</b></dd>
<dd>object representation, 967</dd>
</dl>
</dd>
</dl>
</dd>
<dd><b>POP</b> instruction, 241-242, 404</dd>
<dd><b>POPA</b> instruction, 221</dd>
<dd><b>POPF</b> instruction, 226, 226-231</dd>
<dd>Popping, memory locations vs. registers, 254-255</dd>
<dd>Portable code, and future of programming profession, 725-726</dd>
<dd>
Portals
<dl>
<dd>and beam trees, 1188</dd>
<dd>in Quake 3-D engine, 1279-1280</dd>
</dl>
</dd>
<dd>
Potentially visible set (PVS)
<dl>
<dd>vs. portals, 1279-1280</dd>
<dd>precalculating, 1188-1189, 1213-1214</dd>
<dd>Quake 3-D engine, 1278-1279</dd>
</dl>
</dd>
<dd>
Precalculated results
<dl>
<dd>BSP trees and potentially visible set (PVS), 1188-1189</dd>
<dd>lookup tables, 146</dd>
</dl>
</dd>
<dd>
Precision
<dl>
<dd>long-period Zen timer, 53</dd>
<dd>rounding vs. truncation, 1002-1003</dd>
<dd>Zen timer, 48, 52</dd>
</dl>
</dd>
<dd>
Prefetch queue
<dl>
<dd>286 and 386 processors, 225</dd>
</dl>
</dd>
<dd>
Prefetch queue cycle-eater
<dl>
<dd>286 and 386 processors, 210</dd>
<dd>instruction execution times, 87-93</dd>
<dd>optimizing for, 93</dd>
<dd>overview, 86</dd>
<dd>system wait states, 210</dd>
<dd>and Zen timer, 88, 92</dd>
</dl>
</dd>
<dd>
Prefix bytes
<dl>
<dd>Pentium processor, 376, 395, 407</dd>
<dd>and stack-based variables, 184</dd>
</dl>
</dd>
<dd>Prefixes. <i>See</i> Prefix bytes.</dd>
<dd><i>Principles of Interactive Computer Graphics</i> (book), 934</dd>
<dd>Problems, quick responses to, 1166</dd>
<dd>Profiling, and 80x87 emulator, Borland C++, 999</dd>
<dd>Program size vs. clock cycles, 28</dd>
<dd><i>Programmer&rsquo;s Guide to PC Video Systems</i> (book), 651</dd>
<dd>
Projection
<dl>
<dd>defined, 1135</dd>
<dd>floating point optimization, 1174</dd>
<dd><b>LineIntersectPlane</b> function, <b>1142-1143</b></dd>
<dd>
overview, 937, 948
<dl>
<dd><b>XformAndProjectPoly</b> function, <b>944-945</b></dd>
</dl>
</dd>
<dd>rotation without matrices, 1143-1144</dd>
<dd>using dot product, 1141-1142</dd>
</dl>
</dd>
<dd><b>ProjectPolygon</b> function, <b>1201</b></dd>
<dd>Proportional text, 489</dd>
<dd>
Protected mode
<dl>
<dd>addressable memory, 221</dd>
<dd>
486 processor
<dl>
<dd>addressing calculation pipeline, 239</dd>
<dd>indexed addressing, 237-238</dd>
</dl>
</dd>
<dd>general tips, 140</dd>
<dd>overview, 208-209</dd>
<dd>32-bit addressing modes, 256-258</dd>
</dl>
</dd>
<dd><b>PS2</b> equate, long-period Zen timer, 65-66</dd>
<dd>PS/2 computers, 54, 66</dd>
<dd><b>PUSH</b> instruction, 222, 241-242, 404</dd>
<dd><b>PUSHA</b> instruction, 221</dd>
<dd>Pushing, memory locations vs. registers, 254-255</dd>
<dd>PZTEST.ASM listing, Zen timer, <b>49</b></dd>
<dd>PZTIME.BAT listing, Zen timer, <b>51</b></dd>
<dd>PZTIMER.ASM listing, Zen timer, <b>35-42</b></dd>
<dd><big><b>Q</b></big></dd>
<dd>QLife program, <b>352-363</b></dd>
<dd><b>QSCAN3.ASM</b> listing, <b>309-311</b></dd>
<dd>Quake 2, 1293</dd>
<dd>
Quake
<dl>
<dd>surface caching, 1253-1256, 1260-1262</dd>
<dd>
surface-based lighting
<dl>
<dd>description, 1250-1251</dd>
<dd>mipmapping, 1254-1255</dd>
<dd>performance, 1251-1253</dd>
<dd>surface caching, 1253-1256, 1260-1262</dd>
<dd>texture mapping, 1261-1262</dd>
</dl>
</dd>
<dd>
3-D engine
<dl>
<dd>BSP trees, 1276-1277</dd>
<dd>lighting, 1282-1283</dd>
<dd>model overview, 1276-1277</dd>
<dd>portals, 1279-1280</dd>
<dd>potentially visible set (PVS), 1278-1279</dd>
<dd>rasterization, 1282</dd>
<dd>world, drawing, 1280-1281</dd>
</dl>
</dd>
<dd>and visible surface determination (VSD), 1181</dd>
</dl>
</dd>
<dd>QuakeWorld, 1291-1292</dd>
<dd><big><b>R</b></big></dd>
<dd>Radiosity lighting, Quake 2, 1293</dd>
<dd>
Rasterization of polygons
<dl>
<dd><i>See also</i> Polygons, filling.</dd>
<dd>boundary pixels, selecting, 712</dd>
<dd>efficient implementation, 711</dd>
<dd>in Quake 3-D engine, 1282</dd>
</dl>
</dd>
<dd>Rate of divergence, in 3-D drawing, 937</dd>
<dd>Raycast, subdividing, and beam trees, 1187</dd>
<dd><b>RCL</b> instruction, 185-186</dd>
<dd><b>RCR</b> instruction, 185-186</dd>
<dd><b>Read360x480Dot</b> subroutine, <b>614-615</b></dd>
<dd>
<b>Read()</b> C library function
<dl>
<dd>vs. <b>getc()</b> function, 12</dd>
<dd>overhead, 121</dd>
</dl>
</dd>
<dd>Read Index register, 651-652</dd>
<dd>
Read Map register
<dl>
<dd>demo program, <b>526-530</b></dd>
<dd>planes, specifying to be read, 542</dd>
<dd>read mode, 0, 526</dd>
</dl>
</dd>
<dd>Read Map register demo program, <b>526-530</b></dd>
<dd>Read mode, 0, 521</dd>
<dd>
Read mode 1
<dl>
<dd>Color Don&rsquo;t Care register, 534</dd>
<dd>overview, 525-526</dd>
<dd>vs. read mode 0, 521</dd>
<dd>selecting, 525</dd>
</dl>
</dd>
<dd>Read/write/modify operations, 107</dd>
<dd>Read-after-write register contention, 404</dd>
<dd><b>ReadPixel</b> subroutine, <b>598</b>, 599</dd>
<dd><b>ReadPixelX</b> subroutine, <b>884-885</b></dd>
<dd>Real mode. <i>See</i> 386 processor.</dd>
<dd>
Real mode
<dl>
<dd>addressing calculation pipeline, 239</dd>
<dd>32-bit addressing modes, 256-258</dd>
</dl>
</dd>
<dd>
Rectangle fill, Mode X
<dl>
<dd>four-plane parallel processing, 888-891, <b>891-893</b></dd>
<dd>pixel-by-pixel plane selection, <b>885-887</b></dd>
<dd>plane-by-plane processing, <b>887-889</b></dd>
</dl>
</dd>
<dd>
Recursion
<dl>
<dd>
BSP trees
<dl>
<dd>building BSP trees, 1101-1104</dd>
<dd>data recursive inorder traversal, 1107-1113</dd>
<dd>visibility ordering, 1104-1106</dd>
</dl>
</dd>
<dd>
code recursion
<dl>
<dd>vs. data recursion, 1108-1110</dd>
<dd>Euclid&rsquo;s algorithm, 198-199</dd>
</dl>
</dd>
<dd>compiler-based optimization, 1112-1113</dd>
<dd>
data recursion
<dl>
<dd>vs. code recursion, 1108-1110</dd>
<dd>compiler-based optimization, 1112-1113</dd>
<dd>Euclid&rsquo;s algorithm, 200</dd>
<dd>inorder tree traversal, 1108-1110</dd>
<dd>performance, 1111-1113</dd>
</dl>
</dd>
<dd>performance, 1111-1113</dd>
</dl>
</dd>
<dd>
Reference materials
<dl>
<dd>3-D drawing, 934-935</dd>
<dd>3-D math, 1135</dd>
<dd>bitmapped text, drawing, 471</dd>
<dd>Bresenham&rsquo;s line-drawing algorithm, 660</dd>
<dd>BSP trees, 1114, 1157</dd>
<dd>circle drawing, 626</dd>
<dd>color perception, 625</dd>
<dd>8253 timer chip, 72</dd>
<dd>486 processor, 236</dd>
<dd>parametric line clipping, 1121</dd>
<dd>Pentium processor, 374, 1148</dd>
<dd>SVGA programming, 626</dd>
<dd>VGA registers, 583</dd>
</dl>
</dd>
<dd><b>ReferenceZTimerOff</b> subroutine, 41</dd>
<dd><b>ReferenceZTimerOn</b> subroutine, 40</dd>
<dd>Reflections, in GLQuake, 1290</dd>
<dd>Reflective color, vs. emissive color, 1035</dd>
<dd>Register contention, Pentium processor, 403-405</dd>
<dd>Register-only instructions, 223-225</dd>
<dd>
Registers
<dl>
<dd><i>See also</i> 32-bit registers; VGA registers.</dd>
<dd>AX register, 171</dd>
<dd>copying bytes between, 172</dd>
<dd>EGA palette registers, 549-550</dd>
<dd>8-bit bus cycle-eater, 85</dd>
<dd>
486 processor
<dl>
<dd>addressing pipeline penalty, 238-240, 250</dd>
<dd>byte registers and lost cycles, 242-245</dd>
<dd>indexed addressing, 237-238</dd>
<dd>pushing or popping, vs. memory locations, 254-255</dd>
<dd>scaled, 256-258</dd>
<dd>stack addressing, 241-242</dd>
<dd>32-bit addressing modes, 256-258</dd>
</dl>
</dd>
<dd>prefetch queue cycle-eater, 94</dd>
<dd>and split screen operations, 573</dd>
<dd>and stack frames, 153</dd>
<dd>VGA architecture, 427-429</dd>
</dl>
</dd>
<dd>Relocating bitmaps, 516-517</dd>
<dd>
Rendering BSP trees
<dl>
<dd>backface removal, 1160-1161</dd>
<dd>clipping, 1158-1159</dd>
<dd><b>ClipWalls</b> function, <b>1152-1155</b>, 1158-1159</dd>
<dd><b>DrawWallsBackToFront</b> function, <b>1155-1156</b>, 1160-1161</dd>
<dd>overview, 1149</dd>
<dd>reference materials, 1157</dd>
<dd><b>TransformVertices</b> function, <b>1151-1152</b>, 1158</dd>
<dd><b>UpdateViewPos</b> function, <b>1151</b>, 1157</dd>
<dd><b>UpdateWorld</b> function, <b>1156-1157</b>, 1157</dd>
<dd>viewspace, transformation of objects to, 1158</dd>
<dd>wall orientation testing, 1160-1161</dd>
<dd><b>WallFacingViewer</b> function, <b>1150-1151</b>, 1161</dd>
</dl>
</dd>
<dd><i>RenderMan Companion</i> (book), 742</dd>
<dd><b>REP MOVS</b> instruction, 148</dd>
<dd><b>REP MOVSW</b> instruction, 82, 105, 220</dd>
<dd><b>REP SCASW</b> instruction, 166</dd>
<dd><b>REP STOS</b> instruction, 727, 735</dd>
<dd>
<b>REPNZ SCASB</b> instruction
<dl>
<dd>vs. Boyer-Moore algorithm, 267-268, 271, 274</dd>
<dd>in string searching problem, 121-122, 174-175, 262-263</dd>
</dl>
</dd>
<dd>
<b>REPZ CMPS</b> instruction
<dl>
<dd>vs. Boyer-Moore algorithm, 267-268, 271, 274</dd>
<dd>in string searching problem, 121-122, 174-175, 262-263</dd>
</dl>
</dd>
<dd>
Restartable blocks
<dl>
<dd>in 16-bit checksum program, 16</dd>
<dd>optimizing file processing, 118</dd>
<dd>performance, 122</dd>
<dd>in search engine, 117-118</dd>
<dd>size of, 114, 121</dd>
</dl>
</dd>
<dd>
Results, precalculating
<dl>
<dd><i>See also</i> lookup tables.</dd>
<dd>BSP trees and potentially visible set (PVS), 1188-1189</dd>
</dl>
</dd>
<dd><b>RET</b> instruction, 241-242</dd>
<dd>Reusable code, and future of programming profession, 725-726</dd>
<dd>
RGB (red, green, blue) color model
<dl>
<dd>mapping to 256-color mode, 1036, <b>1037-1038</b>, 1039</dd>
<dd>overview, 1034-1035</dd>
</dl>
</dd>
<dd>Richardson, John, 316</dd>
<dd>Right-handed coordinate system, 935-937</dd>
<dd><b>ROL</b> instruction, 185-186</dd>
<dd>Roll angle, in polygon clipping, 1206</dd>
<dd><b>ROR</b> instruction, 185-186</dd>
<dd>
Rotate instructions
<dl>
<dd>hand assembling, 255-256</dd>
<dd>n-bit vs. 1-bit, 255-256</dd>
<dd>286 processor, 222</dd>
</dl>
</dd>
<dd><b>RotateAndMovePObject</b> function, 977-978</dd>
<dd>
Rotation, 3-D animation
<dl>
<dd><b>ConcatXforms</b> function, 944</dd>
<dd>matrix representation, 938-939</dd>
<dd>multiple axes of rotation, 948</dd>
<dd>using dot product, 1143-1144</dd>
<dd><b>XformVec</b> function, 943</dd>
</dl>
</dd>
<dd>Rotational variance, 1249</dd>
<dd>
Rotations, bitwise
<dl>
<dd>vs. lookup tables, 145-146</dd>
<dd>multi-bit vs. single-bit, 185-186</dd>
</dl>
</dd>
<dd>
Rounding vs. truncation
<dl>
<dd>in 3-D animation, 1002-1003</dd>
<dd>floating point optimization, 1174-1175</dd>
<dd>texture mapping, 1066-1067</dd>
</dl>
</dd>
<dd>
Run-length slice algorithm
<dl>
<dd>assembly implementation, <b>698-704</b></dd>
<dd>C-language implementations, <b>688-692</b>, <b>692-693</b></dd>
<dd>description, 683-684</dd>
<dd>implementation details, 685-687</dd>
<dd>integer-based implementation, 685-687</dd>
<dd>potential optimizations, 705</dd>
</dl>
</dd>
<dd>Ruts, mental, staying out of, 1147-1148</dd>
<dd><big><b>S</b></big></dd>
<dd><b>SAHF</b> instruction, 148</dd>
<dd>Sam the Golden Retriever, 841-842</dd>
<dd>
SC (Sequence Controller), VGA
<dl>
<dd>addressing, 427-428</dd>
<dd>
Map Mask register
<dl>
<dd>CPU writes, selecting planes, 443-444, 471-472</dd>
<dd>drawing text, 833</dd>
<dd>optimizing Mode X, 1074</dd>
<dd>vs. Read Map register, 526</dd>
<dd>with set/reset circuitry, 474</dd>
<dd>write mode 1, 444</dd>
</dl>
</dd>
</dl>
</dd>
<dd>Scaled registers, 256-258</dd>
<dd>
Scan conversion, polygons
<dl>
<dd>active edges, 721, 742-744, 753, 755, 756</dd>
<dd>C-language implementation, <b>713-717</b>, 720-721</dd>
<dd>defined, 710</dd>
<dd>zero-length segments, 721</dd>
</dl>
</dd>
<dd>
Scan lines
<dl>
<dd>redefining length of, 442</dd>
<dd>in split screens, 564-565, 573</dd>
<dd>360x480 256-color mode, 619</dd>
<dd>vertical, in texture mapping, 1084-1086</dd>
</dl>
</dd>
<dd>
<b>ScanBuffer</b> assembly routine
<dl>
<dd>author&rsquo;s implementation, <b>301-302</b>, <b>303-304</b></dd>
<dd>hand-optimized implementation(Willem Clements), <b>313-315</b></dd>
<dd>lookup table implementation (David Stafford), <b>309-311</b>, 317-319</dd>
</dl>
</dd>
<dd>
<b>ScanEdge</b> function
<dl>
<dd>assembly implementation, <b>735-738</b>, 735</dd>
<dd>floating-point C implementation, <b>716-717</b>, 720-721</dd>
<dd>integer-based C implementation, <b>730-732</b></dd>
</dl>
</dd>
<dd><b>ScanEdges</b> function, <b>1234-1236</b>, 1238-1239</dd>
<dd>
<b>ScanOutAET</b> function
<dl>
<dd>complex polygons, <b>749-750</b></dd>
<dd>monotone-vertical polygons, <b>770</b></dd>
</dl>
</dd>
<dd>
<b>ScanOutLine</b> function
<dl>
<dd>assembly implementation, <b>1069-1073</b>, 1074</dd>
<dd>C-language implementation, <b>1058-1059</b>, <b>1067-1069</b></dd>
</dl>
</dd>
<dd><b>SCASW</b> instruction, 161</dd>
<dd>
Screen blanking
<dl>
<dd>demo program, <b>556-557</b></dd>
<dd>using DAC Mask register, 651</dd>
</dl>
</dd>
<dd>Screen blanking demo program, <b>556-557</b></dd>
<dd>Screen capture programs, 541-548</dd>
<dd>Screen redraws, and display adapter cycle-eater, 101, 102</dd>
<dd>Screen refresh rate, 619</dd>
<dd>
Screenspace
<dl>
<dd>defined, 1135</dd>
<dd>and normals of polygons, 1137-1138</dd>
<dd>projecting to, BSP tree rendering, 1159</dd>
<dd>uses for, 967</dd>
</dl>
</dd>
<dd>SEARCH.C listing, <b>118-121</b></dd>
<dd>
Search engine
<dl>
<dd><i>See also</i> Searching.</dd>
<dd>Boyer-Moore algorithm, 263-277</dd>
<dd>design considerations, 114</dd>
<dd>execution profile, 121</dd>
<dd><b>FindString</b> function, 175, <b>176</b>, <b>178</b>, <b>269</b></dd>
<dd>optimization, 174-180</dd>
<dd>restartable blocks, 117-118</dd>
<dd>search space and optimization, 122, 175</dd>
<dd>search techniques, 115-116, 175</dd>
</dl>
</dd>
<dd><b>SearchForString</b> function, <b>118</b></dd>
<dd>
Searching
<dl>
<dd><i>See also</i> Search engine.</dd>
<dd>Boyer-Moore algorithm, 263-277</dd>
<dd>in linked list of arrays, 156-166</dd>
<dd>for specified byte in buffer, 141-145</dd>
<dd>using <b>REP SCASW</b>, 166</dd>
</dl>
</dd>
<dd><b>SecondPass</b> function, <b>358-360</b></dd>
<dd>Sedgewick, Robert (<i>Algorithms</i>), 192, 196</dd>
<dd>
Segments
<dl>
<dd>compiler handling of, 154</dd>
<dd>and far jumps, 186</dd>
<dd>protected mode, 208-209</dd>
<dd>386 processor, 222</dd>
</dl>
</dd>
<dd><b>SelectBSPTree</b> function, <b>1124-1125</b></dd>
<dd>Selling ideas, 1193-1194</dd>
<dd>Sentinels, in linked lists, 286</dd>
<dd>Sequence Controller, VGA. <i>See</i> SC (Sequence Controller), VGA.</dd>
<dd><b>Set320x400Mode</b> subroutine, 593, <b>596-597</b>, 599, <b>602-604</b></dd>
<dd><b>Set320x240Mode</b> subroutine, <b>881-882</b></dd>
<dd><b>Set360x480Mode</b> subroutine, <b>612</b>, 620-621</dd>
<dd><b>Set640x400</b> function, <b>855</b></dd>
<dd>
Set/reset circuitry, VGA
<dl>
<dd>color-forcing demo program, 474-476</dd>
<dd>and CPU data, 474</dd>
<dd>emulating write mode 3, 490</dd>
<dd>overview, 471-472, 478-479</dd>
<dd>plane-manipulation demo program, <b>476-478</b></dd>
<dd>planes, setting all to single color, 473-474</dd>
<dd>and write mode 2, 501-502, 509, 515</dd>
</dl>
</dd>
<dd>Set/Reset register, 666</dd>
<dd><b>SetBIOS8x8Font</b> subroutine, <b>830</b></dd>
<dd><b>Set_cell</b> method, <b>327</b>, <b>334</b>, <b>342</b></dd>
<dd>SETGC macro, 454, 475</dd>
<dd><b>SetPalette</b> function, <b>783-784</b></dd>
<dd><b>SetPelPan</b> subroutine, <b>580</b></dd>
<dd>SETSC macro, 474</dd>
<dd><b>SetSplitScreenScanLine</b> subroutine, <b>570-571</b>, <b>581</b></dd>
<dd><b>SetStartAddress</b> subroutine, <b>570</b>, <b>580</b></dd>
<dd><b>SetUpEdge</b> function, <b>1057-1058</b></dd>
<dd><b>SetWorldspace</b> function, <b>1204</b></dd>
<dd>
Shading
<dl>
<dd><i>See also</i> Lighting; 3-D drawing.</dd>
<dd>ambient shading, 1023</dd>
<dd>diffuse shading, 1023-1024</dd>
<dd>directed light sources, 1028</dd>
<dd>effects, 360x480 256-color mode, 618</dd>
<dd>overall shading, calculating, 1025</dd>
<dd>of polygons, <b>1025-1026</b>, 1027-1029</dd>
</dl>
</dd>
<dd>
Shearing
<dl>
<dd>cause of, 813</dd>
<dd>in dirty-rectangle animation, 846</dd>
<dd>page flipping, 814</dd>
<dd>sheep, 1063</dd>
</dl>
</dd>
<dd>Shift instructions, 222, 255-256</dd>
<dd>Shifting bits, vs. lookup tables, 145-146</dd>
<dd><b>SHL</b> instruction, 376</dd>
<dd><b>ShowBounceCount</b> function, <b>823-824</b></dd>
<dd>
<b>ShowPage</b> subroutine
<dl>
<dd>masked copying animation, Mode X, <b>929-930</b></dd>
<dd>page flipping animation, <b>827</b></dd>
</dl>
</dd>
<dd><b>Show_text</b> function, <b>329</b>, <b>363</b></dd>
<dd><b>SHR</b> instruction, 88-91, 97</dd>
<dd>SIB byte, 257</dd>
<dd>640x400 mode, mode set routine, <b>852-853</b></dd>
<dd>640x480 mode, page flipping, 836-837</dd>
<dd>
16-bit checksum program
<dl>
<dd><i>See also</i> TCP/IP checksum program.</dd>
<dd>assembly implementation, <b>10-12</b>, <b>17-18</b></dd>
<dd>C language implementation, <b>8-9</b>, <b>15-16</b></dd>
<dd>overview, 8</dd>
<dd>redesigning, 9</dd>
</dl>
</dd>
<dd>
16-color VGA modes
<dl>
<dd>color paging, 628-629</dd>
<dd>DAC (Digital/Analog Converter), 626-628</dd>
<dd>palette RAM, 626</dd>
</dl>
</dd>
<dd>Small code model, linking Zen timer, 70</dd>
<dd>Software patents, 1194</dd>
<dd>
Sorted span hidden surface removal
<dl>
<dd>abutting span sorting, 1229-1230</dd>
<dd><b>AddPolygonEdges</b> function, <b>1232-1233</b>, 1238</dd>
<dd>BSP order vs. 1/z order, 1220, 1226</dd>
<dd><b>ClearEdgeLists</b> function, <b>1236-1237</b></dd>
<dd><b>DrawSpans</b> function, <b>1236</b></dd>
<dd>edge sorting, 1220-1222</dd>
<dd>edges vs. spans, 1215-1220</dd>
<dd>independent span sorting, 1230, <b>1231-1238</b>, 1239-1241</dd>
<dd>intersecting span sorting, 1228-1229</dd>
<dd>1/z sorting, 1220-1222, 1227-1231, <b>1231-1238</b>, 1239-1241</dd>
<dd>overview, 1214-1215</dd>
<dd><b>PolyFacesViewer</b> function, <b>1232</b></dd>
<dd><b>ScanEdges</b> function, <b>1234-1236</b>, 1238-1239</dd>
<dd><b>UpdateWorld</b> function, <b>1237-1238</b></dd>
</dl>
</dd>
<dd>
Sorting techniques
<dl>
<dd>25-byte sorting routine, 180-181</dd>
<dd>BSP trees, 1099</dd>
<dd>moving models in 3-D drawings, 1212-1222</dd>
<dd>1/z sorting for hidden surface removal, 1220-1222</dd>
<dd>and optimization, 755</dd>
<dd>z-buffers, 1212-1213</dd>
</dl>
</dd>
<dd><b>SortObjects</b> function, <b>1002</b></dd>
<dd>Span-based drawing, and beam trees, 1187</dd>
<dd>Specular reflection, 1023</dd>
<dd>
Split screens
<dl>
<dd>EGA bug, 573-574</dd>
<dd>horizontal panning, 574-575, <b>575-582</b>, 583</dd>
<dd>overview, 563-565</dd>
<dd>page flipping, 640x480 mode, 836-837</dd>
<dd>registers, setting, 573</dd>
<dd>safety of, 585</dd>
<dd>split screen demo program, 565, <b>566-572</b>, 572</dd>
<dd>text mode, 584</dd>
<dd>turning on and off, 565</dd>
</dl>
</dd>
<dd><b>SplitScreenDown</b> subroutine, <b>572</b></dd>
<dd><b>SplitScreenUp</b> subroutine, <b>572</b></dd>
<dd>
Spotlights
<dl>
<dd>Gouraud shading, 1247</dd>
<dd>shading implementation, 1028</dd>
</dl>
</dd>
<dd>
Sprites
<dl>
<dd>masked images, 871-872</dd>
<dd>Quake 3-D engine, 1287</dd>
</dl>
</dd>
<dd>Square wave timer mode, 44</dd>
<dd>
Stack addressing
<dl>
<dd>address pipeline effects, 241-242</dd>
<dd>assembly language optimization, 420</dd>
</dl>
</dd>
<dd>Stack frames, performance, 153</dd>
<dd>Stack pointer alignment, 218-219</dd>
<dd>Stack-based variables, placement of, 184-185</dd>
<dd>Stacks, <b>POPF</b> vs. <b>IRET</b>, 226-231</dd>
<dd>
Stafford, David
<dl>
<dd>25-byte sorting routine, 180-181</dd>
<dd>Game of Life implementation, 351-352, <b>353-363</b>, 363-365</dd>
<dd><b>ScanBuffer</b> assembly routine, word count program, <b>309-311</b>, 317-319</dd>
<dd>24-byte hi/lo function, 292-293</dd>
</dl>
</dd>
<dd>Start Address High and Low registers, 834-836</dd>
<dd>
State machines
<dl>
<dd>3-cell-per-word implementation, Game of Life, 363-366</dd>
<dd>word count program, 315</dd>
</dl>
</dd>
<dd><b>StepEdge</b> function, <b>1056-1057</b></dd>
<dd><b>STOSB</b> instruction, 236</dd>
<dd>String instructions, 107</dd>
<dd>String searching. <i>See</i> Search engine; Searching.</dd>
<dd><b>Strstr()</b> function, 115</dd>
<dd><b>SUB</b> instruction, 219</dd>
<dd>Subdivision rasterization, 1266-1267, <b>1267-1270</b>, 1286</dd>
<dd>
Superscalar execution
<dl>
<dd>initial pipe, effect of, 405</dd>
<dd>interleaving operations, 394-395</dd>
<dd>lockstep execution, 390-394, 400-403</dd>
<dd>overview, 384-386</dd>
<dd>register contention, 403-405</dd>
<dd>V-pipe-capable instructions, 386-387</dd>
</dl>
</dd>
<dd>SuperVGA, 104, 107, 842-844</dd>
<dd>
Surface caching
<dl>
<dd>hardware interactions, 1260-1262</dd>
<dd>surface-based lighting, 1253-1256</dd>
<dd>in VQuake, 1288</dd>
</dl>
</dd>
<dd>
Surface-based lighting
<dl>
<dd>description, 1250-1251</dd>
<dd>mipmapping, 1254-1255</dd>
<dd>performance, 1251-1253</dd>
<dd>surface caching, 1253-1256, 1260-1262</dd>
<dd>texture mapping, 1261-1262</dd>
</dl>
</dd>
<dd>
System clock
<dl>
<dd>
inaccuracies
<dl>
<dd>long-period Zen timer, 53, 54</dd>
<dd>Zen timer, 43, 45-46, 48</dd>
</dl>
</dd>
<dd>timer 0, 8253 chip, 44, 54</dd>
</dl>
</dd>
<dd>
System memory, Mode X
<dl>
<dd>copying to display memory, 908, <b>909-911</b></dd>
<dd>masked copy to display memory, <b>916-918</b>, 916</dd>
</dl>
</dd>
<dd>System wait states, 210-213</dd>
<dd><big><b>T</b></big></dd>
<dd>Table-driven state machines, 316-319</dd>
<dd>Tail nodes, in linked lists, 286</dd>
<dd>TASM (Turbo Assembler), 71-72</dd>
<dd>
TCP/IP checksum program
<dl>
<dd>basic implementation, <b>406</b></dd>
<dd>dword implementation, <b>409</b></dd>
<dd>interleaved implementation, <b>408</b></dd>
<dd>unrolled loop implementation, <b>410</b></dd>
</dl>
</dd>
<dd><b>Test</b> function, <b>358</b>, 365</dd>
<dd><b>TEST</b> instruction, 377, 401-402</dd>
<dd>
Texels
<dl>
<dd>Gouraud shading, 1247</dd>
<dd>mipmapping, 1254-1255</dd>
</dl>
</dd>
<dd>
Text, drawing
<dl>
<dd>
bitmapped text demo program
<dl>
<dd>using bit mask, <b>466-469</b>, 470-471</dd>
<dd>using write mode 3, <b>484-489</b>, 489-490, <b>490-496</b></dd>
</dl>
</dd>
<dd>high-speed text demo program, using write mode 3, <b>490-496</b></dd>
<dd>solid text demo program, using latches, 1039-1041, <b>1042-1044</b></dd>
<dd>using write mode 0, 832-833</dd>
</dl>
</dd>
<dd>
Text mode
<dl>
<dd>display adapter cycle-eater, 104</dd>
<dd>horizontal resolution, 620</dd>
<dd>panning, 443</dd>
<dd>split screen operations, 584-585</dd>
</dl>
</dd>
<dd>Text pages, flipping from graphics to text, 517</dd>
<dd>TEXT_UP macro, <b>454</b>, 459</dd>
<dd><b>TextUp</b> subroutine, <b>829</b></dd>
<dd>
Texture mapping
<dl>
<dd><i>See also</i> DDA (digital differential analyzer) texture mapping.</dd>
<dd>boundary pixels, polygons, 1049-1052, 1066, <b>1067</b></dd>
<dd>C implementation, <b>1053-1058</b></dd>
<dd>independent span sorting, 1238</dd>
<dd>onto 2-D transformed polygons, 1050</dd>
<dd>onto 3-D transformed polygons, 1051</dd>
<dd>onto untransformed polygon, 1049</dd>
<dd>
optimization
<dl>
<dd>inner-loop optimizations, <b>1069-1073</b>, 1074, 1081-1084</dd>
<dd>instruction-by-instruction optimizations, 1086-1092</dd>
<dd>pointer advancement optimization, 1086-1089, <b>1090-1091</b></dd>
<dd>vertical scanlines, 1084-1086</dd>
</dl>
</dd>
<dd>orientation independence, 1065-1066, <b>1067</b></dd>
<dd>overview, 1048</dd>
<dd>Pentium pipeline stalls, 1092</dd>
<dd>perspective correction, 1093</dd>
<dd>surface-based lighting, 1261-1262</dd>
<dd>vertical scanlines, 1084-1086</dd>
</dl>
</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>32-bit division, 181-184, 1008</dd>
<dd>32-bit fixed-point arithmetic, optimizing, 1086-1089, <b>1090-1091</b>, 1092-1093</dd>
<dd>32-bit instructions, optimizing, 1091</dd>
<dd>
32-bit registers
<dl>
<dd><i>See also</i> Registers; VGA registers.</dd>
<dd>adding with <b>LEA</b>, 131</dd>
<dd><b>BSWAP</b> instruction, 252</dd>
<dd>multiplying with <b>LEA</b>, 132-133</dd>
<dd>386 processor, 222</dd>
<dd>time vs. space tradeoff, 187</dd>
<dd>using as two 16-bit registers, 253-254</dd>
</dl>
</dd>
<dd>
3-D animation
<dl>
<dd><i>See also</i> Hidden surface removal; 3-D drawing; 3-D polygon rotation demo program; X-Sharp 3-D animation package.</dd>
<dd>
demo programs
<dl>
<dd>solid cube rotation program, <b>957-961</b>, 962-963, <b>964-966</b>, 967</dd>
<dd>3-D polygon rotation program, 939, <b>940-945</b>, 948-949</dd>
<dd>12-cube rotation program, 972, <b>973-984</b>, 985-987</dd>
</dl>
</dd>
<dd>depth sorting, 1000, <b>1001-1002</b></dd>
<dd>
rotation
<dl>
<dd><b>ConcatXforms</b> function, <b>944</b></dd>
<dd>matrix representation, 938-939</dd>
<dd>multiple axes of rotation, 948</dd>
<dd><b>XformVec</b> function, <b>943</b></dd>
</dl>
</dd>
<dd>rounding vs. truncation, 1002-1003</dd>
<dd>translation of objects, 937-938</dd>
</dl>
</dd>
<dd>
3-D clipping
<dl>
<dd>arithmetic imprecision, handling, 1240</dd>
<dd>line segments, clipping to planes, 1195-1197</dd>
<dd>overview, 1195</dd>
<dd>
polygon clipping
<dl>
<dd><b>BackRotateVector</b> function, <b>1203</b></dd>
<dd>clipping to frustum, 1200, <b>1201-1206</b>, 1206-1207</dd>
<dd><b>ClipToFrustum</b> function, <b>1204</b></dd>
<dd><b>ClipToPlane</b> function, <b>1199</b></dd>
<dd>optimization, 1207</dd>
<dd>overview, 1197-1200</dd>
<dd><b>PolyFacesViewer</b> function, <b>1203</b></dd>
<dd><b>ProjectPolygon</b> function, <b>1201</b></dd>
<dd><b>SetUpFrustum</b> function, <b>1204</b></dd>
<dd><b>SetWorldspace</b> function, <b>1204</b></dd>
<dd><b>TransformPoint</b> function, <b>1203</b></dd>
<dd><b>TransformPolygon</b> function, <b>1203</b></dd>
<dd><b>UpdateViewPos</b> function, <b>1202</b></dd>
<dd><b>UpdateWorld</b> function, <b>1205</b></dd>
<dd>viewspace clipping, 1207</dd>
<dd><b>ZSortObjects</b> function, <b>1201</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd>
3-D drawing
<dl>
<dd><i>See also</i> BSP (Binary Space Partitioning) trees; Hidden surface removal; Polygons, filling; Shading; 3-D animation.</dd>
<dd>
backface removal
<dl>
<dd>BSP tree rendering, 1160-1161</dd>
<dd>calculations, 955-957</dd>
<dd>motivation for, 954-955</dd>
<dd>and sign of dot product, 1140</dd>
<dd>solid cube rotation demo program, <b>957-961</b>, 962-963, <b>964-966</b>, 967</dd>
</dl>
</dd>
<dd>background surfaces, 1240</dd>
<dd>draw-buffers, and beam trees, 1187</dd>
<dd>and dynamic objects, 1100-1101</dd>
<dd>Gouraud shading, 1246-1250</dd>
<dd>
lighting
<dl>
<dd>Gouraud shading, 1246-1250</dd>
<dd>overlapping lights, 1247</dd>
<dd>perspective correctness, 1248-1250</dd>
<dd>rotational variance, 1249</dd>
<dd>surface-based lighting, 1250-1256, 1260-1262</dd>
<dd>viewing variance, 1249</dd>
</dl>
</dd>
<dd>moving models in 3-D drawings, 1212-1222</dd>
<dd>painter&rsquo;s algorithm, 1099, 1104-1105</dd>
<dd>perspective correctness problem, 1248-1250</dd>
<dd>portals, and beam trees, 1188</dd>
<dd>
projection
<dl>
<dd>dot products, 1141-1142</dd>
<dd>overview, 937, 948</dd>
</dl>
</dd>
<dd>raycast, subdividing, and beam trees, 1187</dd>
<dd>reference materials, 934-935</dd>
<dd>
rendering BSP trees
<dl>
<dd>backface removal, 1160-1161</dd>
<dd>clipping, 1158-1159</dd>
<dd><b>ClipWalls</b> function, <b>1152-1155</b>, 1158-1159</dd>
<dd><b>DrawWallsBackToFront</b> function, <b>1155-1156</b>, 1160-1161</dd>
<dd>overview, 1149</dd>
<dd>reference materials, 1157</dd>
<dd><b>TransformVertices</b> function, <b>1151-1152</b>, 1158</dd>
<dd><b>UpdateViewPos</b> function, <b>1151</b>, 1157</dd>
<dd><b>UpdateWorld</b> function, <b>1156-1157</b>, 1157</dd>
<dd>viewspace, transformation of objects to, 1158</dd>
<dd>wall orientation testing, 1160-1161</dd>
<dd><b>WallFacingViewer</b> function, <b>1150-1151</b>, 1161</dd>
</dl>
</dd>
<dd>span-based drawing, and beam trees, 1187</dd>
<dd>transformation of objects, 935-936</dd>
<dd>
triangle model drawing
<dl>
<dd>fast triangle drawing, 1263-1265</dd>
<dd>overview, 1262-1263</dd>
<dd>precision, 1265</dd>
<dd>subdivision rasterization, 1266-1267, <b>1267-1270</b></dd>
</dl>
</dd>
<dd>vertex-free surfaces, and beam trees, 1187</dd>
<dd>visibility determination, 1099-1106</dd>
<dd>
visible surface determination (VSD)
<dl>
<dd>beam trees, 1185-1189</dd>
<dd>culling to frustum, 1181-1184</dd>
<dd>overdraw problem, 1184-1185</dd>
<dd>polygon culling, 1181-1184</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
3-D engine, Quake
<dl>
<dd>BSP trees, 1276-1277</dd>
<dd>lighting, 1282-1283</dd>
<dd>model overview, 1276-1277</dd>
<dd>portals, 1279-1280</dd>
<dd>potentially visible set (PVS), 1278-1279</dd>
<dd>rasterization, 1282</dd>
<dd>world, drawing, 1280-1281</dd>
</dl>
</dd>
<dd>
3-D math
<dl>
<dd>cross products, 1139-1140</dd>
<dd>
dot products
<dl>
<dd>calculating, 1135-1137</dd>
<dd>calculating light intensity, 1137</dd>
<dd>projection, 1141-1142</dd>
<dd>rotation, 1143-1144</dd>
<dd>sign of, 1140-1141</dd>
<dd>of unit vectors, 1136</dd>
<dd>of vectors, 1135-1136</dd>
</dl>
</dd>
<dd>
matrix math
<dl>
<dd>assembly routines, 992, <b>996-999</b></dd>
<dd>C-language implementations, <b>974-976</b></dd>
<dd>normal vectors, calculating, 955-956</dd>
<dd>rotation of 3-D objects, 938-939, <b>943-944</b>, 948</dd>
<dd>transformation, optimized, 1172-1173, <b>1173-1174</b></dd>
</dl>
</dd>
<dd>vector length, 1135</dd>
</dl>
</dd>
<dd>
3-D polygon rotation demo program
<dl>
<dd>matrix multiplication functions, <b>943-944</b>, 948</dd>
<dd>overview, 939</dd>
<dd>performance, 949</dd>
<dd>polygon filling with clipping support, <b>940-943</b></dd>
<dd>transformation and projection, <b>944-945</b>, 948</dd>
</dl>
</dd>
<dd>
3-D solid cube rotation demo program
<dl>
<dd>basic implementation, <b>957-961</b>, 962-963</dd>
<dd>incremental transformations, <b>964-966</b></dd>
<dd>object representation, 967</dd>
</dl>
</dd>
<dd>386 native mode, 32-bit displacements, 187</dd>
<dd>
386 processor
<dl>
<dd>alignment, stack pointer, 218-219</dd>
<dd><b>CMP</b> instruction, 161, 306</dd>
<dd>cycle-eaters, 209-210</dd>
<dd>data alignment, 213, 218</dd>
<dd>and display adapter cycle-eater, 107</dd>
<dd>display adapter cycle-eater, 219-221</dd>
<dd>doubleword alignment, 218</dd>
<dd>DRAM refresh cycle-eater, 219</dd>
<dd>effective address calculations, 129, 223-225</dd>
<dd><b>LEA</b> instruction, 130-133, 172</dd>
<dd><b>LODSD</b> vs. <b>MOV/LEA</b> sequence, 171</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>memory access, performance, 223-225</dd>
<dd><b>MUL</b> and <b>IMUL</b> instructions, 173-174</dd>
<dd>multiplication operations, increasing speed of, 173-174</dd>
<dd>new instructions and features, 222</dd>
<dd>Pentium code, running on, 411</dd>
<dd>protected mode, 208-209</dd>
<dd>rotation instructions, clock cycles, 185-186</dd>
<dd>system wait states, 210-212</dd>
<dd>32-bit addressing modes, 256-258</dd>
<dd>32-bit multiply and divide operations, 985</dd>
<dd>using 32-bit register as two 16-bit registers, 253-254</dd>
<dd><b>XCHG</b> vs. <b>MOV</b> instructions, 377, 832</dd>
</dl>
</dd>
<dd>386SX processor, 16-bit bus cycle-eater, 81</dd>
<dd>
360x480 256-color mode
<dl>
<dd>display memory, accessing, 621-622</dd>
<dd><b>Draw360x480Dot</b> subroutine, 613-614</dd>
<dd>drawing speed, 618</dd>
<dd>horizontal resolution, 620</dd>
<dd>line drawing demo program, <b>615-618</b>, 618-619</dd>
<dd>mode set routine (John Bridges), 609, <b>612</b>, 620-621</dd>
<dd>on VGA clones, 610-611</dd>
<dd><b>Read360x480Dot</b> subroutine, <b>614-615</b></dd>
<dd>256-color resolution, 619-620</dd>
<dd>vertical resolution, 619</dd>
</dl>
</dd>
<dd>
320x400 256-color mode
<dl>
<dd>advantages of, 590-591</dd>
<dd>display memory organization, 591-593</dd>
<dd>line drawing, 600</dd>
<dd>page flipping demo program, <b>600-605</b></dd>
<dd>performance, 599-600</dd>
<dd>pixel drawing demo program, <b>593-598</b>, 599-600</dd>
</dl>
</dd>
<dd>320x240 256-color mode. <i>See</i> Mode X.</dd>
<dd>Time perception, subjectivity of, 972</dd>
<dd>Time-critical code, 13</dd>
<dd>
Timer 0, 8253 timer chip
<dl>
<dd>operation, 44</dd>
<dd>stopping, 54, 65</dd>
</dl>
</dd>
<dd>Timer modes, 44, 45</dd>
<dd><b>TIMER_INT</b> BIOS routine, 44</dd>
<dd>
Timers
<dl>
<dd><i>See also</i> 8253 timer chip; Long-period Zen timer; Zen timer.</dd>
<dd>divide-by-N mode, 45</dd>
<dd>square wave mode, 44</dd>
</dl>
</dd>
<dd>Timeslicing delays, 446</dd>
<dd>
Timing intervals
<dl>
<dd>long-period Zen timer, 53</dd>
<dd>Zen timer, 45</dd>
</dl>
</dd>
<dd>Transformation inefficiencies, 25-26</dd>
<dd>Transformation matrices. <i>See</i> Matrices; Matrix math.</dd>
<dd>
Transformation of 3-D objects
<dl>
<dd>defined, 1135</dd>
<dd>floating point optimization, 1172-1173, <b>1173-1174</b></dd>
<dd>incremental transformations, 964</dd>
<dd>steps in, 935-936</dd>
</dl>
</dd>
<dd><b>TransformPolygon</b> function, <b>1203</b></dd>
<dd>Translation in 3-D space, 937-938</dd>
<dd>Treuenfels, Anton, 756</dd>
<dd>
Triangle model drawing
<dl>
<dd>fast triangle drawing, 1263-1265</dd>
<dd>overview, 1262-1263</dd>
<dd>precision, 1265</dd>
<dd>subdivision rasterization, 1266-1267, <b>1267-1270</b></dd>
</dl>
</dd>
<dd>Triangles, and rotational variance, 1249-1250</dd>
<dd>Trinity, 1294</dd>
<dd>Truncation errors, in 3-D animation, 1002-1003</dd>
<dd>
Truncation vs. rounding
<dl>
<dd>floating point optimization, 1174-1175</dd>
<dd>texture mapping, 1066-1067</dd>
</dl>
</dd>
<dd>TSRs, and DAC, loading, 643, 648</dd>
<dd>Turbo Profiler, and 80x87 emulator, Borland C++, 999</dd>
<dd>
12-cube rotation demo program
<dl>
<dd>limitations of, 986</dd>
<dd>optimizations in, 985-986</dd>
<dd>performance, 986</dd>
<dd>X-Sharp animation package, 972, <b>973-984</b>, 984-985</dd>
</dl>
</dd>
<dd>24-byte hi/lo function, 292-293</dd>
<dd>
286 processor
<dl>
<dd><b>CMP</b> instruction, 161, 306</dd>
<dd>code alignment, 215-218</dd>
<dd>cycle-eaters, 209-210</dd>
<dd>data alignment, 213-215</dd>
<dd>data transfer rates, 212</dd>
<dd>display adapter cycle-eater, 219-221</dd>
<dd>display memory wait states, 220</dd>
<dd>DRAM refresh cycle-eater, 219</dd>
<dd>effective address calculations, 129, 223-225</dd>
<dd>instruction fetching, 215-218</dd>
<dd><b>LEA</b> vs. <b>ADD</b> instructions, 130</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>memory access, performance, 223-225</dd>
<dd>new features, 221</dd>
<dd><b>POPF</b> instruction, and interrupts, 226</dd>
<dd>protected mode, 208-209</dd>
<dd>stack pointer alignment, 218-219</dd>
<dd>system wait states, 210-212</dd>
</dl>
</dd>
<dd>
256-color modes
<dl>
<dd><i>See also</i> 320x400 256-color mode.</dd>
<dd>DAC settings, 629</dd>
<dd>mapping RGB model to, 1036, <b>1037-1038</b>, 1039</dd>
<dd>resolution, 360x480 256-color mode, 619-620</dd>
</dl>
</dd>
<dd>Two-pass lighting, 1262</dd>
<dd>Two&rsquo;s complement negation, 171</dd>
<dd><big><b>U</b></big></dd>
<dd>Unifying models, and optimization, 1110-1111</dd>
<dd>Unit normal of polygons, calculating, 1027-1028, 1137-1140</dd>
<dd>Unit vectors, dot product, 1136-1137</dd>
<dd>Unrolling loops, 143-145, 305, 312, 377-378, 410</dd>
<dd><b>UpdateViewPos</b> function, <b>1202</b></dd>
<dd><b>UpdateWorld</b> function, <b>1205</b>, <b>1237-1238</b></dd>
<dd>
U-pipe, Pentium processor
<dl>
<dd>branch instructions, 404-405</dd>
<dd>overview, 385-386</dd>
<dd>pairable instructions, 388</dd>
<dd><big><b>V</b></big></dd>
</dl>
</dd>
<dd>Variables, word-sized vs. byte-sized, 82, 83-85</dd>
<dd>
Vectors
<dl>
<dd>cross product, 1139-1140</dd>
<dd>cross-products, calculating, 955-956</dd>
<dd>dot product, 1135-1137</dd>
<dd>length equation, 1135</dd>
<dd>optimization of, 986</dd>
<dd>unit vectors, dot product, 1136-1137</dd>
</dl>
</dd>
<dd>
<b>VectorsUp</b> function
<dl>
<dd>Bresenham&rsquo;s line-drawing algorithm, <b>664-665</b></dd>
<dd>360x480 256-color mode line drawing program, <b>617-618</b></dd>
</dl>
</dd>
<dd>Verite Quake, 1287-1280</dd>
<dd>Vertex-free surfaces, and beam trees, 1187</dd>
<dd>Vertical blanking, loading DAC, 641</dd>
<dd>Vertical resolution, 360x480 256-color mode, 619</dd>
<dd>Vertical scanlines, in texture mapping, 1084-1086</dd>
<dd>
Vertical sync pulse
<dl>
<dd>loading DAC, 641, 648</dd>
<dd>and page flipping, 444-446, 835-836</dd>
<dd>split screens, 573</dd>
</dl>
</dd>
<dd>
VGA BIOS
<dl>
<dd>
DAC (Digital/Analog Converter)
<dl>
<dd>loading, 641-642, 648</dd>
<dd>setting registers, 630, 631-632</dd>
</dl>
</dd>
<dd>vs. direct hardware programming, 458-459</dd>
<dd>function 13H, 459</dd>
<dd>and nonstandard modes, 854-855</dd>
<dd>palette RAM, setting registers, 629-630, 631-632</dd>
<dd>reading from DAC, 652</dd>
<dd>text routines, in 320x400 256-color mode, 592</dd>
<dd>and VGA registers, 458</dd>
</dl>
</dd>
<dd>
VGA clones
<dl>
<dd>potential incompatibilities, 446-447</dd>
<dd>360x480 256-color mode, 610-611</dd>
</dl>
</dd>
<dd>
VGA color path
<dl>
<dd>color paging, 628-629</dd>
<dd>DAC (Digital/Analog Converter), 626-628, 630, 631-632</dd>
<dd>palette RAM, 626, 629-630, 631-632</dd>
</dl>
</dd>
<dd>VGA compatibility, 446-447, 610-611</dd>
<dd>
VGA memory
<dl>
<dd>Color Don&rsquo;t Care register, <b>535-537</b>, 535</dd>
<dd>CPU reads, 520, 526</dd>
</dl>
</dd>
<dd>
VGA modes
<dl>
<dd>bit-plane animation, 811</dd>
<dd>color compare mode, <b>531-534</b>, 531</dd>
<dd>mode 0, set/reset circuitry, 471-472, 474-479</dd>
<dd>mode 12H (hi-res mode), page flipping, 851-855</dd>
<dd>
mode 13H
<dl>
<dd>converting to 320x400 256-color mode, 593</dd>
<dd>overview, 515</dd>
<dd>resolution, 590</dd>
</dl>
</dd>
<dd>
Mode X
<dl>
<dd>bitmap organization, 882-883</dd>
<dd>copying pixels using latches, <b>905-907</b>, 908, <b>909-911</b></dd>
<dd>features, 878-879</dd>
<dd>four-plane parallel processing, 888-891, <b>891-893</b></dd>
<dd>masked copying, <b>916-918</b>, 916, 918-919, <b>919-921</b></dd>
<dd>memory allocation, 903-904</dd>
<dd>mode set routine, <b>880-881</b>, 882</dd>
<dd>pattern fills, 899, <b>900-903</b>, 903-904</dd>
<dd>pixel-by-pixel plane selection, <b>885-887</b></dd>
<dd>plane-by-plane processing, <b>887-889</b></dd>
<dd><b>ReadPixelX</b> subroutine, <b>884-885</b></dd>
<dd><b>WritePixelX</b> subroutine, <b>883-884</b></dd>
</dl>
</dd>
<dd>and page flipping, 444-445</dd>
<dd>
read mode 1
<dl>
<dd>Color Don&rsquo;t Care register, 534</dd>
<dd>overview, 525-526, 531</dd>
<dd>selecting, 525</dd>
</dl>
</dd>
<dd>and set/reset circuitry, 478</dd>
<dd>640x400 mode set routine, <b>852-853</b></dd>
<dd>split screen operations, 584-585</dd>
<dd>text mode, panning, 443</dd>
<dd>
320x400 256-color mode
<dl>
<dd>advantages, 590-591</dd>
<dd>converting mode 13H to, 593</dd>
<dd>display memory organization, 591-593</dd>
<dd>page flipping demo program, <b>600-605</b></dd>
</dl>
</dd>
<dd>and virtual screens, 441</dd>
<dd>write mode 0, drawing text, 832-833</dd>
<dd>write mode 1, overview, 444</dd>
<dd>
write mode 2
<dl>
<dd>chunky bitmaps, converting to planar, 504-505, <b>505-508</b></dd>
<dd>mechanics, 502</dd>
<dd>overview, 501-502</dd>
<dd>selecting, 504</dd>
</dl>
</dd>
<dd>
write mode 3
<dl>
<dd>vs. Bit Mask register, 844</dd>
<dd>drawing bitmapped text, <b>484-489</b>, 489-490, <b>490-496</b></dd>
<dd>overview, 483-484, 496</dd>
<dd>single-color drawing, 831-832</dd>
<dd>vs. write mode 0, 490</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
VGA registers
<dl>
<dd>AC Index register, bit 5 settings, 443</dd>
<dd>
Bit Mask register
<dl>
<dd>bit mask, controlling, 465</dd>
<dd>drawing solid text, 1040</dd>
<dd>setting inside a loop, 429</dd>
<dd>vs. write mode 3, 832, 844</dd>
</dl>
</dd>
<dd>Color Compare register, in read mode 1, 531</dd>
<dd>Color Don&rsquo;t Care register, in read mode 1, 534</dd>
<dd>Color Select register, color paging, 628-629</dd>
<dd>Data register, loading DAC, 642-643</dd>
<dd>
Data Rotate register
<dl>
<dd>barrel shifter, controlling, 463</dd>
<dd>vs. CPU-based rotations, 489</dd>
<dd>effect on ALUs, 452</dd>
</dl>
</dd>
<dd>
Enable Set/Reset register
<dl>
<dd>setting drawing color, 666</dd>
<dd>specifying plane, 474</dd>
</dl>
</dd>
<dd>
Graphics Mode register
<dl>
<dd>read mode 0, selecting, 525</dd>
<dd>read mode 1, selecting, 531</dd>
</dl>
</dd>
<dd>and high-level languages, 548</dd>
<dd>Horizontal Pel Panning register, 442</dd>
<dd>internal indexing, 427-429</dd>
<dd>Line Compare register, split screen operation, 565</dd>
<dd>
Map Mask register
<dl>
<dd>drawing text, 833</dd>
<dd>optimizing Mode X, 1074</dd>
<dd>vs. Read Map register, 526</dd>
<dd>selecting planes for CPU writes, 443-444, 471-472</dd>
<dd>with set/reset circuitry, 474</dd>
<dd>write mode 1, 444</dd>
</dl>
</dd>
<dd>Mask register, blanking screen, 651</dd>
<dd>Mode Control register, pel panning in split screen, 575</dd>
<dd>
Mode register
<dl>
<dd>color paging, 628-629</dd>
<dd>256-color modes, 629</dd>
</dl>
</dd>
<dd>Overflow register, split screen operation, 565</dd>
<dd>palette RAM registers, setting, 631-632</dd>
<dd>Pel Panning register, 574, 583</dd>
<dd>Read Index register, 651-652</dd>
<dd>
Read Map register
<dl>
<dd>plane, selecting, for CPU reads, 526</dd>
<dd>planes, specifying to be read, 542</dd>
</dl>
</dd>
<dd>Set/Reset register, setting drawing color, 666</dd>
<dd>setting, 504, 558</dd>
<dd>setting and reading, 582</dd>
<dd>Start Address High and Low registers, 834-836</dd>
<dd>and VGA BIOS, 458</dd>
<dd>
Write Index register
<dl>
<dd>DAC index wrapping, 651</dd>
<dd>loading DAC, 642-643</dd>
</dl>
</dd>
</dl>
</dd>
<dd>
VGA (Video Graphics Adapter)
<dl>
<dd>ALU and latch demo program, <b>453-457</b>, 458-460</dd>
<dd>
architecture, 426-429
<dl>
<dd>ALUs, 451-452</dd>
<dd>barrel shifter, 463-464</dd>
<dd>bit mask, 464-471</dd>
<dd>latches, 452-453</dd>
<dd>set/reset circuitry, 471-479</dd>
</dl>
</dd>
<dd>ball animation demo program, <b>431-441</b></dd>
<dd>CGA compatibility, 430</dd>
<dd>delay sequences, 558</dd>
<dd>and display adapter cycle-eater, 104-108</dd>
<dd>display memory, 446</dd>
<dd>fill patterns, drawing, 453</dd>
<dd>GC (Graphics Controller), architecture, 451-453, 463-479</dd>
<dd>I/O access times, 842-844</dd>
<dd>linear addressing, 430</dd>
<dd>memory access times, 842-844</dd>
<dd>overview, 426</dd>
<dd>page flipping, 444-446</dd>
<dd>panning, 441-443</dd>
<dd>performance, with 486 processor, 842-844</dd>
<dd>potential incompatibilities, 446-447</dd>
<dd>registers, internal indexing, 426-429</dd>
<dd>screens, capturing and restoring, 541-542, <b>543-547</b>, 547-548</dd>
<dd>
split screens
<dl>
<dd>horizontal panning, 574-575, <b>575-582</b>, 583</dd>
<dd>overview, 563-565</dd>
<dd>registers, setting, 573</dd>
<dd>safety of, 585</dd>
<dd>split screen demo program, 565, <b>566-572</b>, 572</dd>
<dd>text mode, 584</dd>
<dd>turning on and off, 565</dd>
</dl>
</dd>
<dd>25 MHz clock and 28 MHz clock, switching between, 620-621</dd>
<dd>
virtual screens
<dl>
<dd>overview, 430</dd>
<dd>panning, 441-443</dd>
</dl>
</dd>
</dl>
</dd>
<dd>Video function 10H, EGA BIOS, 550-551, 555</dd>
<dd>Viewing angle, and BSP tree rendering, 1157-1158</dd>
<dd>Viewing variance, 1249</dd>
<dd>
Viewspace
<dl>
<dd>defined, 1135</dd>
<dd>and normals of polygons, 1137-1138</dd>
<dd>in 3-D transformation, 935</dd>
<dd>transformation to, BSP rendering, 1158</dd>
<dd>uses for, 967</dd>
</dl>
</dd>
<dd>Viewspace clipping, 1207</dd>
<dd>
Virtual screens
<dl>
<dd>overview, 430</dd>
<dd>panning, 441-443</dd>
</dl>
</dd>
<dd>
Visibility determination
<dl>
<dd><i>See also</i> Visible surface determination.</dd>
<dd>and BSP trees, 1099-1106</dd>
</dl>
</dd>
<dd>Visibility of polygons, calculating, 955-956</dd>
<dd>
Visible surface determination (VSD)
<dl>
<dd>beam trees, 1185-1189</dd>
<dd>culling to frustum, 1181-1184</dd>
<dd>overdraw problem, 1184-1185</dd>
<dd>polygon culling, 1181-1184</dd>
<dd>and portals, 1279-1280</dd>
<dd>potentially visible set (PVS), precalculating, 1188-1189</dd>
</dl>
</dd>
<dd>
V-pipe, Pentium processor
<dl>
<dd>branch instructions, 404-405</dd>
<dd>overview, 385-386</dd>
<dd>V-pipe-capable instructions, 386-387</dd>
</dl>
</dd>
<dd>VQuake, 1287-1280</dd>
<dd>VSD. <i>See</i> Visible surface determination (VSD).</dd>
<dd><big><b>W</b></big></dd>
<dd><b>Wait30Frames</b> function, <b>854</b></dd>
<dd>
Wait states
<dl>
<dd>
display memory wait states
<dl>
<dd>8088 processor, 101-103</dd>
<dd>286 processor, 220</dd>
</dl>
</dd>
<dd>vs. DRAM refresh, 100</dd>
<dd>overview, 99</dd>
<dd>system memory wait states, 210-213</dd>
</dl>
</dd>
<dd><b>WaitForVerticalSyncEnd</b> subroutine, <b>569</b>, <b>579-580</b></dd>
<dd><b>WaitForVerticalSyncStart</b> subroutine, <b>569</b>, <b>579</b></dd>
<dd><b>WalkBSPTree</b> function, <b>1106</b></dd>
<dd>
<b>WalkTree</b> function
<dl>
<dd>code recursive version, <b>1108</b></dd>
<dd>data recursive version, <b>1109-1110</b></dd>
</dl>
</dd>
<dd>Wall orientation testing, BSP tree rendering, 1160-1161</dd>
<dd>WC word counting program (TerjeMathisen), optimization, 250-252, 306, 319</dd>
<dd>Williams, Rob, 174</dd>
<dd>Winnie the Pooh orbiting Saturn, 1047</dd>
<dd>WinQuake, 1290</dd>
<dd>
Word alignment, 286 processor
<dl>
<dd>code alignment, 215-218</dd>
<dd>data alignment, 213-215</dd>
<dd>stack pointer alignment, 218-219</dd>
</dl>
</dd>
<dd>
Word count program
<dl>
<dd>edge triggered device, 316</dd>
<dd>fine-tuning optimization, 312-313</dd>
<dd>initial C implementation, <b>299</b></dd>
<dd>lookup table, <b>303</b>, 304, 317-319</dd>
<dd>
<b>ScanBuffer</b> assembly routine
<dl>
<dd>author&rsquo;s implementation, <b>301-302</b></dd>
<dd>Stafford, David&rsquo;s, <b>309-311</b>, 317-319</dd>
<dd>Willem Clements&rsquo; implementation, <b>313-315</b></dd>
</dl>
</dd>
<dd>as state machine, 315</dd>
<dd>theoretical maximum performance, 319</dd>
</dl>
</dd>
<dd>Word-<b>OUT</b> instruction, 429</dd>
<dd>
Word-sized variables, 8088 processor
<dl>
<dd>memory access, 82</dd>
<dd>optimization, 83-85</dd>
</dl>
</dd>
<dd>World, drawing, in Quake 3-D engine, 1280-1281</dd>
<dd>
Worldspace
<dl>
<dd>defined, 1135</dd>
<dd>in 3-D transformation, 935</dd>
<dd>uses for, 967</dd>
</dl>
</dd>
<dd>
Write Index register
<dl>
<dd>DAC index wrapping, 651</dd>
<dd>loading DAC, 642-643</dd>
</dl>
</dd>
<dd>
Write mode 0
<dl>
<dd>drawing text, 832-833</dd>
<dd>vs. write mode 2, 503</dd>
</dl>
</dd>
<dd>
Write mode 1
<dl>
<dd>overview, 444</dd>
<dd>vs. write mode 3, 490</dd>
</dl>
</dd>
<dd>
Write mode 2
<dl>
<dd>chunky bitmaps, converting to planar, 504-505, <b>505-508</b></dd>
<dd>color-patterned lines demo program, <b>509-515</b></dd>
<dd>mechanics, 502</dd>
<dd>overview, 501-502</dd>
<dd>selecting, 504</dd>
<dd>vs. set/reset circuitry, 509, 515</dd>
<dd>vs. write mode 0, 503</dd>
</dl>
</dd>
<dd>
Write mode 3
<dl>
<dd>vs. Bit Mask register, 844</dd>
<dd>character/attribute map, 517</dd>
<dd>drawing bitmapped text, <b>484-489</b>, 489-490, <b>490-496</b></dd>
<dd>drawing solid text, 1039-1041, <b>1042-1044</b></dd>
<dd>graphics, preserving on switch to, 515-517, <b>518-521</b></dd>
<dd>overview, 483-484, 496</dd>
<dd>single-color drawing, 831-832</dd>
<dd>vs. write mode 1, 490</dd>
</dl>
</dd>
<dd>Write mode 3 demo program, <b>484-489</b>, 489-490, <b>490-496</b></dd>
<dd>
Write modes, VGA
<dl>
<dd>and set/reset circuitry, 478</dd>
<dd>text, drawing, 484, 490, 496</dd>
</dl>
</dd>
<dd>Write-after-write register contention, 404</dd>
<dd><b>WritePixel</b> subroutine, <b>597</b>, 599</dd>
<dd><b>WritePixelX</b> subroutine, <b>883-884</b></dd>
<dd>
Writing pixels
<dl>
<dd>320x400 256-color mode, 599, 600</dd>
</dl>
</dd>
<dd>
Wu antialiasing algorithm
<dl>
<dd>assembly implementation, <b>787-791</b></dd>
<dd>C-language implementation, <b>780-786</b></dd>
<dd>description, 776-778, 791-792</dd>
<dd>error accumulation, 778-779, 792</dd>
<dd>performance, 777-778</dd>
<dd>pixel intensity calculations, 778-779</dd>
</dl>
</dd>
<dd>Wu, Xiaolin. <i>See</i> Wu antialiasing algorithm.</dd>
<dd><big><b>X</b></big></dd>
<dd>
X86 family CPUs
<dl>
<dd><i>See also</i> 8088 processor.</dd>
<dd>32-bit division, 181-184, 1008</dd>
<dd>branching, performance, 140</dd>
<dd>copying bytes between registers, 172</dd>
<dd>interrupts, 9</dd>
<dd>limitations for assembly programmers, 27</dd>
<dd>lookup tables, vs. rotating or shifting, 145-146</dd>
<dd><b>LOOP</b> instruction vs. <b>DEC/JNZ</b> sequence, 139</dd>
<dd>machine instructions, versatility, 128</dd>
<dd>memory addressing modes, 129-133</dd>
<dd>overview, 208</dd>
<dd>transformation inefficiencies, 26</dd>
</dl>
</dd>
<dd><b>XCHG</b> instruction, 377, 832</dd>
<dd>X-clipping, in BSP tree rendering, 1159</dd>
<dd><b>XformAndProjectPObject</b> function, <b>974</b></dd>
<dd><b>XformAndProjectPoints</b> function, <b>960</b></dd>
<dd><b>XformAndProjectPoly</b> function, <b>944-945</b></dd>
<dd>
<b>XformVec</b> function
<dl>
<dd>assembly implementation, <b>996-997</b>, <b>1017-1019</b></dd>
<dd>C implementation, <b>943</b>, <b>976</b></dd>
</dl>
</dd>
<dd>
<b>XLAT</b> instruction
<dl>
<dd>in Boyer-Moore algorithm, 274-277</dd>
<dd>byte registers, 243</dd>
<dd>with lookup table, 304</dd>
</dl>
</dd>
<dd><b>XOR</b> instruction, vs. <b>NOT</b>, 147</dd>
<dd>
X-Sharp 3-D animation package
<dl>
<dd><b>AppendRotationX</b> function, <b>975</b></dd>
<dd><b>AppendRotationY</b> function, <b>964-965</b>, <b>975</b></dd>
<dd><b>AppendRotationZ</b> function, <b>965</b>, <b>976</b></dd>
<dd>code archives on diskette, 985</dd>
<dd>
<b>ConcatXforms</b> function
<dl>
<dd>assembly implementation, <b>997-999</b>, <b>1019-1022</b></dd>
<dd>C implementations, <b>944</b>, <b>976</b></dd>
</dl>
</dd>
<dd><b>CosSin</b> subroutine, <b>994-996</b>, 999, <b>1013-1015</b></dd>
<dd>
DDA (digital differential analyzer) texture mapping
<dl>
<dd>assembly implementation, <b>1069-1073</b>, 1074</dd>
<dd>C implementation, <b>1053-1058</b></dd>
<dd>disadvantages, 1052-1053, 1059</dd>
<dd><b>DrawTexturedPolygon</b>, <b>1055-1056</b></dd>
<dd>hardware dependence, 1053</dd>
<dd>multiple adjacent polygons, 1068</dd>
<dd>optimized implementation, <b>1069-1073</b>, 1074</dd>
<dd>orientation independence, 1065-1067, <b>1067</b></dd>
<dd>performance, 1074</dd>
<dd><b>ScanOutLine</b> function, <b>1058-1059</b>, <b>1067</b></dd>
<dd><b>SetUpEdge</b> function, <b>1057-1058</b></dd>
<dd><b>StepEdge</b> function, <b>1056-1057</b></dd>
<dd>techniques, 1048-1051</dd>
</dl>
</dd>
<dd>
<b>DrawPObject</b> function, <b>978-979</b>
<dl>
<dd>ambient and diffuse shading support, <b>1025-1027</b></dd>
</dl>
</dd>
<dd><b>FixedDiv</b> subroutine, <b>982</b>, <b>993</b>, <b>1010-1012</b></dd>
<dd>FIXED_MUL macro, 1016-1017</dd>
<dd><b>FixedMul</b> subroutine, <b>981</b>, <b>993-994</b>, <b>1009-1010</b></dd>
<dd><b>InitializeCubes</b> function, <b>980-981</b></dd>
<dd><b>InitializeFixedPoint</b> function, <b>977</b></dd>
<dd>matrix math, assembly routines, 992, <b>996-999</b></dd>
<dd><b>ModelColorToColorIndex</b> function, 1036, <b>1038</b></dd>
<dd>older processors, support for, 1007-1008, <b>1008-1023</b></dd>
<dd>overview, 984-985</dd>
<dd>POLYGON.H header file, <b>982-984</b></dd>
<dd>
RGB color model
<dl>
<dd>mapping to 256-color mode, 1036, <b>1037-1038</b>, 1039</dd>
<dd>overview, 1034-1035</dd>
</dl>
</dd>
<dd><b>RotateAndMovePObject</b> function, <b>977-978</b></dd>
<dd><b>XformAndProjectPObject</b> function, <b>974</b></dd>
<dd>
<b>XformVec</b> function
<dl>
<dd>assembly implementation, <b>996-997</b>, <b>1017-1019</b></dd>
<dd>C implementation, <b>976</b></dd>
</dl>
</dd>
</dl>
</dd>
<dd>
<b>XSortAET</b> function
<dl>
<dd>complex polygons, <b>748</b></dd>
<dd>monotone-vertical polygons, <b>769</b></dd>
<dd><big><b>Y</b></big></dd>
</dl>
</dd>
<dd>Yaw angle, in polygon clipping, 1206</dd>
<dd>Y-clipping, in BSP tree rendering, 1159</dd>
<dd><big><b>Z</b></big></dd>
<dd>
Z-buffers
<dl>
<dd>performance, 1213</dd>
<dd>Quake 3-D engine, 1285-1286</dd>
<dd>vs. sorted spans, 1215</dd>
<dd>sorting moving models, 1212-1213</dd>
</dl>
</dd>
<dd>Z-clipping, in BSP tree rendering, 1158</dd>
<dd>
Zen timer
<dl>
<dd><i>See also</i> Long-period Zen timer.</dd>
<dd>calling, 48</dd>
<dd>calling from C code, 69-72</dd>
<dd>and DRAM refresh, 99</dd>
<dd>and interrupts, 43</dd>
<dd>interval length, 45</dd>
<dd>overhead of, timing, 46, 72</dd>
<dd>PC compatibility, 48-49</dd>
<dd>precision, 48, 52</dd>
<dd>prefetch queue cycle-eater, 88, 92</dd>
<dd>PS/2 compatibility, 66</dd>
<dd>PZTEST.ASM listing, <b>49</b></dd>
<dd>PZTIME.BAT listing, <b>51</b></dd>
<dd>PZTIMER.ASM listing, <b>35-42</b></dd>
<dd><b>ReferenceZTimerOff</b> subroutine, <b>41</b></dd>
<dd><b>ReferenceZTimerOn</b> subroutine, <b>40</b></dd>
<dd>reporting results, 47</dd>
<dd>starting, 43</dd>
<dd>stopping, 46</dd>
<dd>system clock inaccuracies, 43, 45-46, 48</dd>
<dd>test-bed program, 48-52</dd>
<dd>TESTCODE listing, <b>50</b></dd>
<dd>timing 486 code, 245-246</dd>
<dd><b>ZTimerOff</b> subroutine, <b>38-41</b>, 46-47</dd>
<dd><b>ZTimerOn</b> subroutine, <b>37-38</b>, 43</dd>
<dd><b>ZTimerReport</b> subroutine, <b>41-42</b>, 47-48</dd>
</dl>
</dd>
<dd>Zero-wait-state memory, 211</dd>
<dd>Z-order display, masked images, 872</dd>
<dd>Z-sorting, for hidden surface removal, 1220-1222</dd>
<dd><b>ZSortObjects</b> function, <b>1201</b></dd>
<dd>
<b>ZTimerOff</b> subroutine
<dl>
<dd>long-period Zen timer, <b>59-63</b></dd>
<dd>Zen timer, <b>38-41</b>, 46-47</dd>
</dl>
</dd>
<dd>
<b>ZTimerOn</b> subroutine
<dl>
<dd>long-period Zen timer, <b>58-59</b></dd>
<dd>Zen timer, <b>37-38</b>, 43</dd>
</dl>
</dd>
<dd>
<b>ZTimerReport</b> subroutine
<dl>
<dd>long-period Zen timer, <b>63-65</b></dd>
<dd>Zen timer, <b>41-42</b>, 47-48</dd>
</dl>
</dd>
</dl>
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