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<HTML>
<HEAD>
<META name=vsisbn content="1576101746">
<META name=vstitle content="Michael Abrash's Graphics Programming Black Book, Special Edition">
<META name=vsauthor content="Michael Abrash">
<META name=vspublisher content="The Coriolis Group">
<META name=vspubdate content="07/01/97">
<META name=vscategory content="Web and Software Development: Game Development,Web and Software Development: Graphics and Multimedia Development">
<TITLE>Michael Abrash's Graphics Programming Black Book Special Edition: Index</TITLE>
<!-- HEADER -->
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<!--ISBN=1576101746//-->
<!--TITLE=Michael Abrash's Graphics Programming Black Book Special Edition//-->
<!--AUTHOR=Michael Abrash//-->
<!--PUBLISHER=The Coriolis Group, Inc.//-->
<!--CHAPTER=Index//-->
<!--PAGES=1299-1342//-->
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<TABLE BORDER>
<TR>
<TD><A HREF="appendix-a.html">Previous</A></TD>
<TD><A HREF="index.html">Table of Contents</A></TD>
<TD><A HREF="index.html">Next</A></TD>
</TR>
</TABLE>
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<P><BR></P>
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Index</FONT></H2>
<DL>
<DD><BIG><B>Numbers</B></BIG>
<DD>1/z sorting
<DL>
<DD>abutting span sorting, 1229-1230
<DD><B>AddPolygonEdges</B> function, <B>1232-1233,</B> 1238
<DD>vs. BSP-order sorting, 1226-1227
<DD>calculating 1/z value, 1220-1222
<DD><B>ClearEdgeLists</B> function, <B>1236-1237</B>
<DD><B>DrawSpans</B> function, <B>1236</B>
<DD>independent span sorting, 1230, <B>1231-1238,</B> 1239-1241
<DD>intersecting span sorting, 1228-1229
<DD><B>PolyFacesViewer</B> function, <B>1232</B>
<DD>reliability, 1227
<DD><B>ScanEdges</B> function, <B>1234-1236,</B> 1238-1239
<DD><B>UpdateWorld</B> function, 1237-1238
</DL>
<DD>3-D animation
<DL>
<DD><I>See also</I> Hidden surface removal; 3-D drawing; 3-D polygon rotation demo program; X-Sharp 3-D animation package.
<DD>demo programs
<DL>
<DD>solid cube rotation program, <B>957-961,</B> 962-963, <B>964-966,</B> 967
<DD>3-D polygon rotation program, 939, <B>940-945,</B> 948-949
<DD>12-cube rotation program, 972, <B>973-984,</B> 985-987
</DL>
<DD>depth sorting, 1000, <B>1001-1002</B>
<DD>rotation
<DL>
<DD><B>ConcatXforms</B> function, <B>944</B>
<DD>matrix representation, 938-939
<DD>multiple axes of rotation, 948
<DD><B>XformVec</B> function, <B>943</B>
</DL>
<DD>rounding vs. truncation, 1002-1003
<DD>translation of objects, 937-938
</DL>
<DD>3-D clipping
<DL>
<DD>arithmetic imprecision, handling, 1240
<DD>line segments, clipping to planes, 1195-1197
<DD>overview, 1195
<DD>polygon clipping
<DL>
<DD><B>BackRotateVector</B> function, <B>1203</B>
<DD>clipping to frustum, 1200, <B>1201-1206,</B> 1206-1207
<DD><B>ClipToFrustum</B> function, <B>1204</B>
<DD><B>ClipToPlane</B> function, <B>1199</B>
<DD>optimization, 1207
<DD>overview, 1197-1200
<DD><B>PolyFacesViewer</B> function, <B>1203</B>
<DD><B>ProjectPolygon</B> function, <B>1201</B>
<DD><B>SetUpFrustum</B> function, <B>1204</B>
<DD><B>SetWorldspace</B> function, <B>1204</B>
<DD><B>TransformPoint</B> function, <B>1203</B>
<DD><B>TransformPolygon</B> function, <B>1203</B>
<DD><B>UpdateWorld</B> function, <B>1205</B>
<DD>viewspace clipping, 1207
<DD><B>ZSortObjects</B> function, <B>1201</B>
</DL>
</DL>
<DD>3-D drawing
<DL>
<DD><I>See also</I> BSP (Binary Space Partitioning) trees; Hidden surface removal; Polygons, filling; Shading; 3-D animation.
<DD>backface removal
<DL>
<DD>BSP tree rendering, 1160-1161
<DD>calculations, 955-957
<DD>motivation for, 954-955
<DD>and sign of dot product, 1140
<DD>solid cube rotation demo program, <B>957-961,</B> 962-963, <B>964-966,</B> 967
</DL>
<DD>background surfaces, 1240
<DD>draw-buffers, and beam trees, 1187
<DD>and dynamic objects, 1100-1101
<DD>Gouraud shading, 1246-1250
<DD>lighting
<DL>
<DD>Gouraud shading, 1246-1250
<DD>overlapping lights, 1247
<DD>perspective correctness, 1248-1250
<DD>rotational variance, 1249
<DD>surface-based lighting, 1250-1256, 1260-1262
<DD>viewing variance, 1249
</DL>
<DD>moving models in 3-D drawings, 1212-1222
<DD>painter&#146;s algorithm, 1099, 1104-1105
<DD>perspective correctness problem, 1248-1250
<DD>portals, and beam trees, 1188
<DD>projection
<DL>
<DD>dot products, 1141-1142
<DD>overview, 937, 948
</DL>
<DD>raycast, subdividing, and beam trees, 1187
<DD>reference materials, 934-935
<DD>rendering BSP trees
<DL>
<DD>clipping, 1158-1159
<DD><B>ClipWalls</B> function, <B>1152-1155,</B> 1158-1159
<DD><B>DrawWallsBackToFront</B> function, <B>1155-1156,</B> 1160-1161
<DD>overview, 1149
<DD>reference materials, 1157
<DD><B>TransformVertices</B> function, <B>1151-1152,</B> 1158
<DD><B>UpdateViewPos</B> function, <B>1151,</B> 1157
<DD><B>UpdateWorld</B> function, <B>1156-1157,</B> 1157
<DD>viewspace, transformation of objects to, 1158
<DD>wall orientation testing, 1160-1161
<DD><B>WallFacingViewer</B> function, <B>1150-1151,</B> 1161
</DL>
<DD>span-based drawing, and beam trees, 1187
<DD>transformation of objects, 935-936
<DD>triangle model drawing
<DL>
<DD>fast triangle drawing, 1263-1265
<DD>overview, 1262-1263
<DD>precision, 1265
<DD>subdivision rasterization, 1266-1267, <B>1267-1270</B>
</DL>
<DD>vertex-free surfaces, and beam trees, 1187
<DD>visibility determination, 1099-1106
<DD>visible surface determination (VSD)
<DL>
<DD>beam trees, 1185-1189
<DD>culling to frustum, 1181-1184
<DD>overdraw problem, 1184-1185
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
</DL>
<DD>3-D engine, Quake
<DL>
<DD>BSP trees, 1276-1277
<DD>lighting, 1282-1283
<DD>model overview, 1276-1277
<DD>portals, 1279-1280
<DD>potentially visible set (PVS), 1278-1279
<DD>rasterization, 1282
<DD>world, drawing, 1280-1281
</DL>
<DD>3-D math
<DL>
<DD>cross products, 1139-1140
<DD>dot products
<DL>
<DD>calculating, 1135-1137
<DD>calculating light intensity, 1137
<DD>projection, 1141-1142
<DD>rotation, 1143-1144
<DD>sign of, 1140-1141
<DD>of unit vectors, 1136
<DD>of vectors, 1135-1136
</DL>
<DD>matrix math
<DL>
<DD>assembly routines, 992, <B>996-999</B>
<DD>C-language implementations, <B>974-976</B>
<DD>normal vectors, calculating, 955-956
<DD>rotation of 3-D objects, 938-939, <B>943-944,</B> 948
<DD>transformation, optimized, 1172-1173, <B>1173-1174</B>
</DL>
<DD>vector length, 1135
</DL>
<DD>3-D polygon rotation demo program
<DL>
<DD>matrix multiplication functions, <B>943-944,</B> 948
<DD>overview, 939
<DD>performance, 949
<DD>polygon filling with clipping support, <B>940-943</B>
<DD>transformation and projection, <B>944-945,</B> 948
</DL>
<DD>3-D solid cube rotation demo program
<DL>
<DD>basic implementation, <B>957-961,</B> 962-963
<DD>incremental transformations, <B>964-966</B>
<DD>object representation, 967
</DL>
<DD>8-bit bus cycle-eater
<DL>
<DD>286 and 386 processors, 210
<DD>8088 processor
<DL>
<DD>effects on performance, 82
<DD>optimizing for, 83-85
<DD>overview, 79-82
<DD>and registers, 85
</DL>
</DL>
<DD>12-cube rotation demo program
<DL>
<DD>limitations of, 986
<DD>optimizations in, 985-986
<DD>performance, 986
<DD>X-Sharp animation package, 972, <B>973-984,</B> 984-985
</DL>
<DD>16-bit checksum program
<DL>
<DD><I>See also</I> TCP/IP checksum program.
<DD>assembly implementation, <B>10-12, 17-18</B>
<DD>C language implementation, <B>8-9, 15-16</B>
<DD>overview, 8
<DD>redesigning, 9
</DL>
<DD>16-color VGA modes
<DL>
<DD>color paging, 628-629
<DD>DAC (Digital/Analog Converter), 626-628
<DD>palette RAM, 626
</DL>
<DD>24-byte hi/lo function, 292-293
<DD>32-bit addressing modes, 256-258
<DD>32-bit division, 181-184, 1008
<DD>32-bit fixed-point arithmetic, optimizing, 1086-1089, <B>1090-1091,</B> 1092-1093
<DD>32-bit instructions, optimizing, 1091
<DD>32-bit registers
<DL>
<DD><I>See also</I> Registers; VGA registers.
<DD>adding with <B>LEA,</B> 131
<DD><B>BSWAP</B> instruction, 252
<DD>multiplying with <B>LEA,</B> 132-133
<DD>386 processor, 222
<DD>time vs. space tradeoff, 187
<DD>using as two 16-bit registers, 253-254
</DL>
<DD>256-color modes
<DL>
<DD><I>See also</I> 320&#215;400 256-color mode.
<DD>DAC settings, 629
<DD>mapping RGB model to, 1036, <B>1037-1038,</B> 1039
<DD>resolution, 360&#215;480 256-color mode, 619-620
</DL>
<DD>286 processor
<DL>
<DD><B>CMP</B> instruction, 161, 306
<DD>code alignment, 215-218
<DD>cycle-eaters, 209-210
<DD>data alignment, 213-215
<DD>data transfer rates, 212
<DD>display adapter cycle-eater, 219-221
<DD>display memory wait states, 220
<DD>DRAM refresh cycle-eater, 219
<DD>effective address calculations, 129, 223-225
<DD>instruction fetching, 215-218
<DD><B>LEA</B> vs. <B>ADD</B> instructions, 130
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>memory access, performance, 223-225
<DD>new features, 221
<DD><B>POPF</B> instruction, and interrupts, 226
<DD>protected mode, 208-209
<DD>stack pointer alignment, 218-219
<DD>system wait states, 210-212
</DL>
<DD>320&#215;240 256-color mode. <I>See</I> Mode X.
<DD>320&#215;400 256-color mode
<DL>
<DD>advantages of, 590-591
<DD>display memory organization, 591-593
<DD>line drawing, 600
<DD>page flipping demo program, <B>600-605</B>
<DD>performance, 599-600
<DD>pixel drawing demo program, <B>593-598,</B> 599-600
</DL>
<DD>360&#215;480 256-color mode
<DL>
<DD>display memory, accessing, 621-622
<DD><B>Draw360&#215;480Dot</B> subroutine, <B>613-614</B>
<DD>drawing speed, 618
<DD>horizontal resolution, 620
<DD>line drawing demo program, <B>615-618,</B> 618-619
<DD>mode set routine (John Bridges), 609, <B>612,</B> 620-621
<DD>on VGA clones, 610-611
<DD><B>Read360&#215;480Dot</B> subroutine, <B>614-615</B>
<DD>256-color resolution, 619-620
<DD>vertical resolution, 619
</DL>
<DD>386 native mode, 32-bit displacements, 187
<DD>386 processor
<DL>
<DD>alignment, stack pointer, 218-219
<DD><B>CMP</B> instruction, 161, 306
<DD>cycle-eaters, 209-210
<DD>data alignment, 213, 218
<DD>and display adapter cycle-eater, 107
<DD>display adapter cycle-eater, 219-221
<DD>doubleword alignment, 218
<DD>DRAM refresh cycle-eater, 219
<DD>effective address calculations, 129, 223-225
<DD><B>LEA</B> instruction, 130-133, 172
<DD><B>LODSD</B> vs. <B>MOV/LEA</B> sequence, 171
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>memory access, performance, 223-225
<DD><B>MUL</B> and <B>IMUL</B> instructions, 173-174
<DD>multiplication operations, increasing speed of, 173-174
<DD>new instructions and features, 222
<DD>Pentium code, running on, 411
<DD>protected mode, 208-209
<DD>rotation instructions, clock cycles, 185-186
<DD>system wait states, 210-212
<DD>32-bit addressing modes, 256-258
<DD>32-bit multiply and divide operations, 985
<DD>using 32-bit register as two 16-bit registers, 253-254
<DD><B>XCHG</B> vs. <B>MOV</B> instructions, 377, 832
</DL>
<DD>386SX processor, 16-bit bus cycle-eater, 81
<DD>486 processor
<DL>
<DD>AX register, setting to absolute value, 172
<DD>byte registers and lost cycles, 242-245
<DD><B>CMP</B> instruction
<DL>
<DD>operands, order of, 306
<DD>vs. <B>SCASW,</B> 161
</DL>
<DD>copying bytes between registers, 172
<DD>and display adapter cycle-eater, 107
<DD>indexed addressing, 237-238
<DD>internal cache
<DL>
<DD>effect on code timing, 246
<DD>optimization, 236
</DL>
<DD><B>LAHF</B> and <B>SAHF</B> instructions, 148
<DD><B>LEA</B> instruction, vs. <B>ADD,</B> 131
<DD><B>LODSB</B> instruction, 304
<DD><B>LODSD</B> instruction, vs. <B>MOV/LEA</B> sequence, 171
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction, vs. <B>DEC/JNZ</B> sequence, 139
<DD><B>MOV</B> instruction, vs. <B>XCHG,</B> 377
<DD>n-bit vs. 1-bit shift and rotate instructions, 255-256
<DD>Pentium code, running on, 411
<DD>pipelining
<DL>
<DD>address calculation, 238-240, 250
<DD>stack addressing, 241-242
</DL>
<DD>rotation instructions, clock cycles, 185-186
<DD>stack-based variables, 184-184
<DD>32-bit addressing modes, 256-258
<DD>timing code, 245-246
<DD>using 32-bit register as two 16-bit registers, 253-254
<DD><B>XCHG</B> instruction, vs. <B>MOV,</B> 377, 832
</DL>
<DD>640&#215;400 mode, mode set routine, <B>852-853</B>
<DD>640&#215;480 mode, page flipping, 836-837
<DD>8086 processor vs. 8088 processor, 79-81
<DD>8088 processor
<DL>
<DD><B>CMP</B> instruction, 161, 306
<DD>cycle-eaters
<DL>
<DD>8-bit bus cycle-eater, 79-85
<DD>display adapter cycle-eater, 101-108
<DD>DRAM refresh cycle-eater, 95-99
<DD>overview, 78-79, 80
<DD>prefetch queue cycle-eater, 86-94
<DD>wait states, 99-101
</DL>
<DD>display memory access, 220
<DD>effective address calculation options, 129
<DD>vs. 8086 processor, 79-81
<DD><B>LAHF</B> and <B>SAHF</B> instructions, 148
<DD><B>LEA</B> vs. <B>ADD,</B> 130
<DD><B>LODSB</B> instruction, 304
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>memory variables, size of, 83-85
<DD>stack-based variables, placement of, 184-184
</DL>
<DD>8253 timer chip
<DL>
<DD>and DRAM refresh, 95
<DD>reference material, 72
<DD>resetting, 43
<DD>system clock inaccuracies
<DL>
<DD>long-period Zen timer, 53, 54
<DD>Zen timer, 43, 45-46, 48
</DL>
<DD>timer 0
<DL>
<DD>operation, 44
<DD>stopping, 54, 65
</DL>
<DD>timer modes, 44, 45
<DD>timer operation, 43-45
<DD>undocumented features, 54, 65
<DD><BIG><B>A</B></BIG>
</DL>
<DD>Absolute value, setting AX register, 171
<DD>Abstraction, and optimization, 330-332, 345-346
<DD>Abutting span sorting, 1229-1230
<DD>AC (Attribute Controller), VGA
<DL>
<DD>addressing, 427-428
<DD>Color Select register, 628-629
<DD>Index register, 443, 555
<DD>Mode Control register, 575
<DD>Mode register
<DL>
<DD>color paging, 628-629
<DD>256-color modes, 629
</DL>
<DD>palette RAM registers, setting, 631-632
<DD>Pel Panning register, 574
<DD>registers, setting and reading, 583
<DD>screen blanking demo program, <B>556-557</B>
</DL>
<DD>Active edge table (AET), 744
<DD>Adapters, display. <I>See</I> Display adapter cycle-eater.
<DD><B>ADD</B> instruction
<DL>
<DD>and Carry flag, 147-148
<DD>vs. <B>INC,</B> 147-148, 219
<DD>vs. <B>LEA,</B> 130, 170-171
</DL>
<DD><B>AddDirtyRect</B> function, <B>867-869</B>
<DD>Addition, using LEA, 130, 131
<DD><B>AddObject</B> function, <B>1001-1002</B>
<DD><B>AddPolygonEdges</B> function, <B>1232-1233,</B> 1238
<DD>Addressable memory, protected mode, 221
<DD>Addressing modes
<DL>
<DD>486 processor
<DL>
<DD>indexed addressing, 237-238
<DD>32-bit addressing modes, 256-258
</DL>
<DD>386 processor, 130-133, 222
<DD>VGA, internal indexing, 427-428
</DL>
<DD>Addressing pipeline penalty
<DL>
<DD><I>See also</I> Pipeline stalls.
<DD>486 processor, 238-240, 250
<DD>Pentium processor, 400-403
</DL>
<DD><B>AdvanceAET</B> function
<DL>
<DD>complex polygons, <B>748-749</B>
<DD>monotone-vertical polygons, <B>769</B>
</DL>
<DD>AET (active edge table), 744
<DD>AGIs (Address Generation Interlocks), 400-403
<DL>
<DD><I>See also</I> Addressing pipeline penalty; Pipeline stalls.
</DL>
<DD><I>Algorithms In C</I> (book), 192, 196
<DD>Alignment
<DL>
<DD>Pentium processor
<DL>
<DD>non-alignment penalties, 376
<DD>TCP/IP checksum program, 409
</DL>
<DD><B>REP STOS</B> instruction, 735
<DD>386 processor, 218
<DD>286 processor
<DL>
<DD>code alignment, 215-218
<DD>data alignment, 213-215
<DD>stack pointer alignment, 218-219
</DL>
</DL>
<DD>ALU and latch demo program, <B>453-457,</B> 458-460
<DD>ALUs (Arithmetic Logic Units), VGA
<DL>
<DD>ALU and latch demo program, <B>453-457,</B> 458-460
<DD>logical functions, 458
<DD>operational modes, 458
<DD>overview, 451-452
</DL>
<DD>Ambient shading, 1023, <B>1025-1027</B>
<DD><B>AND</B> instruction, Pentium processor
<DL>
<DD>AGIs (Address Generation Interlocks), 401-402
<DD>vs. <B>TEST,</B> 377
</DL>
<DD>Animation
<DL>
<DD><I>See also</I> Animation demo programs; Mode X; 3-D animation.
<DD>apparent motion, 1064
<DD>ball animation demo program, <B>431-441</B>
<DD>challenges in, 819-820
<DD>on PCs, 795-796
<DD>page flipping, flicker-free animation, 444-446
<DD>speed, importance of, 1064
</DL>
<DD>Animation demo programs
<DL>
<DD>Mode X animation, 924-925, <B>925-930</B>
<DD>page flipping animation
<DL>
<DD>assembly code, <B>825-830</B>
<DD>C code, <B>820-825</B>
<DD>split screen and page flipping, 830-837
</DL>
<DD>3-D polygon rotation
<DL>
<DD>matrix multiplication functions, <B>943-944,</B> 948
<DD>overview, 939
<DD>performance, 949
<DD>polygon filling with clipping support, <B>940-943</B>
<DD>transformation and projection, <B>944-945,</B> 948
</DL>
<DD>3-D solid cube rotation demo program
<DL>
<DD>basic implementation, <B>957-961,</B> 962-963
<DD>incremental transformations, <B>964-966</B>
<DD>object representation, 967
</DL>
</DL>
<DD>Animation techniques
<DL>
<DD>bit-plane animation
<DL>
<DD>assembly implementation, <B>801-809,</B> 810
<DD>limitations, 811-813
<DD>page flipping, 814
<DD>palette registers, 799-801
<DD>principles, 796-798
<DD>shearing, 813
</DL>
<DD>dirty-rectangle animation
<DL>
<DD>C implementation, <B>847-851, 863-869</B>
<DD>description, 844-845
<DD>ordering rectangles, 873
<DD>overlapping rectangles, 872-873
<DD>vs. page flipping, 846, 862
<DD>performance, 873
<DD>system memory buffer size, 851
<DD>writing to display memory, 856-857
</DL>
<DD>internal animation, 872
<DD>masked images, 871-872
</DL>
<DD>Antialiasing, Wu&#146;s algorithm, 776-779, <B>780-791,</B> 791-792
<DD>Apparent motion, in animation, 1064
<DD><B>AppendRotationX</B> function, <B>964, 975</B>
<DD><B>AppendRotationY</B> function, <B>964-965, 975</B>
<DD><B>AppendRotationZ</B> function, <B>965, 976</B>
<DD>Appropriate technology, 775-776
<DD>Arithmetic flags. <I>See</I> Flags.
<DD>Arrays, sorting, 180-181
<DD>Aspect ratio, Mode X, 878
<DD>Assemblers
<DL>
<DD>MASM (Microsoft Assembler), 187
<DD>optimizing assemblers, 71-72
<DD>TASM (Turbo Assembler), 71-72
</DL>
<DD>Assembly language optimization
<DL>
<DD><I>See also</I> Clock cycles; Local optimization; Optimization.
<DD>data, placing limitations on, 274
<DD>instruction size vs. execution time, 90-92, 93
<DD>multi-bit rotations, 23-24
<DD>objectives, 28
<DD>optimizing instructions, 23-24
<DD>programmer&#146;s responsibilities, 27-29
<DD>rearranging instructions, 418-419
<DD>reducing size of code, 416-418
<DD>stack addressing, 420
<DD>understanding data, importance of, 122
</DL>
<DD>Assembly language programmers, vs. compilers, 154-155
<DD>Assembly language, transformation issues, 25-26
<DD>AT computer
<DL>
<DD>display adapter cycle-eater, 107
<DD>286 processor, data transfer rates, 212
</DL>
<DD>Attribute Controller, VGA. <I>See</I> AC (Attribute Controller), VGA.
<DD>Automatic variables, 184-185
<DD>AX register, setting to absolute value, 171
<DD><BIG><B>B</B></BIG>
<DD>Backface culling. <I>See</I> Backface removal.
<DD>Backface removal
<DL>
<DD><I>See also</I> Hidden surface removal; Visible surface determination.
<DD>BSP tree rendering, 1160-1161
<DD>calculations, 955-957
<DD>motivation for, 954-955
<DD>and sign of dot product, 1140
<DD>solid cube rotation demo program, <B>957-961,</B> 962-963, <B>964-966,</B> 967
</DL>
<DD>Background surfaces, 1240
<DD><B>BackRotateVector</B> function, <B>1203</B>
<DD>Ball animation demo program, 431-441
<DD>Barrel shifter, VGA, 463-464
<DD>Beam trees
<DL>
<DD>improvement, attempts at, 1187-1188
<DD>overview, 1185
<DD>performance, 1186
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
<DD>Benchmarks, reliability of, 729
<DD>Biased perceptions, and optimization, 1080, 1085
<DD>Big endian format, 252
<DD>BIOS. <I>See</I> EGA BIOS; VGA BIOS.
<DD>Bit mask
<DL>
<DD>bitmapped text demo program, <B>466-469,</B> 470-471
<DD>and latches, 470
<DD>overview, 464-466
</DL>
<DD>Bit Mask register
<DL>
<DD>bit mask, controlling, 465
<DD>drawing solid text, 1040
<DD>setting inside a loop, 429
<DD>vs. write mode 3, 832, 844
</DL>
<DD>BitMan, 1039-1041, <B>1042-1044</B>
<DD>Bitmap organization, Mode X, 882-883
<DD>Bitmapped text
<DL>
<DD>demo program using bit mask, <B>466-469,</B> 470-471
<DD>reference material, 471
</DL>
<DD>Bitmapped text demo program, <B>466-469,</B> 470-471
<DD>Bitmaps
<DL>
<DD>chunky, converting to planar, 504-505, <B>505-508</B>
<DD>relocating, 516-517
<DD>transient color effects, 509
</DL>
<DD>Bit-plane animation
<DL>
<DD>assembly implementation, <B>801-809,</B> 810
<DD>limitations, 811-813
<DD>overview, 796
<DD>page flipping, 814
<DD>palette registers, 799-801
<DD>principles, 796-798
<DD>shearing, 813
</DL>
<DD>&#147;Black box&#148; approach, and future of programming, 725-726
<DD>Blocks. <I>See</I> Restartable blocks.
<DD>Borders (overscan), 555-556
<DD><B>BOUND</B> instruction, 221
<DD>Boundary pixels, polygons
<DL>
<DD>rules for selecting, 712
<DD>texture mapping, 1049-1052, 1065-1066, <B>1067</B>
</DL>
<DD>Bounding volumes, 1184
<DD>Boyer-Moore algorithm
<DL>
<DD>assembly implementations, <B>271-274, 274-277</B>
<DD>C language implementation, <B>269</B>
<DD>overview, 263-265
<DD>performance, 266-268
<DD>test-bed program, <B>270</B>
</DL>
<DD>Branch prediction, Pentium processor, 377-378
<DD>Branching instructions
<DL>
<DD><I>See also</I> Branch prediction.
<DD>286 and 386 processors
<DL>
<DD>non-word-alignment penalty, 216
<DD>and prefetch queue cycle-eater, 210
</DL>
<DD>eliminating, 312-313
<DD>Pentium processor
<DL>
<DD>branches within loops, 378
<DD>pairing in U-pipe, 405
</DL>
<DD>x86 family CPUs, performance, 140
</DL>
<DD>Bresenham&#146;s line-drawing algorithm
<DL>
<DD>basic algorithm
<DL>
<DD>assembly implementation, 655-656, <B>671-677</B>
<DD>C language implementation, <B>661-665,</B> 665-671
<DD>description, 657-660
<DD>strengths and weaknesses, 660-661
</DL>
<DD>run-length slice algorithm
<DL>
<DD>assembly implementation, <B>698-704</B>
<DD>C-language implementations, <B>688-692, 692-693</B>
<DD>description, 683-684
<DD>implementation details, 685-687
<DD>integer-based implementation, 685-687
<DD>potential optimizations, 705
</DL>
</DL>
<DD>Bresenham&#146;s run-length slice algorithm. <I>See</I> Run-length slice algorithm.
<DD>Bridges, John
<DL>
<DD>mode set routine, 360x480 256-color mode, 609, <B>612,</B> 620-621
<DD>256-color modes, undocumented, 879
</DL>
<DD>Brute-force solutions, 193
<DD>BSP (Binary Space Partitioning) trees
<DL>
<DD>2-D line representation, 1120
<DD>3-D rendering, 1162
<DD>beam trees
<DL>
<DD>improvement, attempts at, 1187-1188
<DD>overview, 1185
<DD>performance, 1186
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
<DD>BSP compiler
<DL>
<DD><B>BuildBSPTree</B> function, <B>1125-1127</B>
<DD><B>SelectBSPTree</B> function, <B>1124-1125</B>
</DL>
<DD><B>BuildBSPTree</B> function, <B>1125-1127</B>
<DD>building, 1101-1104
<DD><B>BuildTree</B> function, <B>1112</B>
<DD>data recursion vs. code recursion, 1108-1113
<DD>description, 1098-1099, 1119
<DD>and dynamic objects, 1100-1101
<DD>edge sorting for hidden surface removal, 1220, 1226
<DD>inorder traversal, 1107-1113
<DD>leaves, storing polygons in, 1181
<DD>multiple BSP trees, sorting, 1227
<DD>optimizations, 1128-1129
<DD>performance, 1100, 1111-1113
<DD>potentially visible set (PVS)
<DL>
<DD>precalculating, 1188-1189
<DD>world, drawing, 1280-1281
</DL>
<DD>reference materials, 1114
<DD>rendering recursively
<DL>
<DD>backface removal, 1160-1161
<DD>clipping, 1158-1159
<DD><B>ClipWalls</B> function, <B>1152-1155,</B> 1158-1159
<DD><B>DrawWallsBackToFront</B> function, <B>1155-1156,</B> 1160-1161
<DD>overview, 1149
<DD>reference materials, 1157
<DD><B>TransformVertices</B> function, <B>1151-1152,</B> 1158
<DD><B>UpdateViewPos</B> function, <B>1151,</B> 1157
<DD><B>UpdateWorld</B> function, <B>1156-1157,</B> 1157
<DD>viewspace, transformation of objects to, 1158
<DD>wall orientation testing, 1160-1161
<DD><B>WallFacingViewer</B> function, <B>1150-1151,</B> 1161
</DL>
<DD><B>SelectBSPTree</B> function, <B>1124-1125</B>
<DD>splitting heuristic, 1128-1129
<DD>3-D engine, Quake
<DL>
<DD>overview, 1276-1277
<DD>potentially visible set (PVS) management, 1278-1279
</DL>
<DD>visible surface determination (VSD)
<DL>
<DD>beam trees, 1185-1189
<DD>culling to frustum, 1181-1184
<DD>overdraw problem, 1184-1185
<DD>painter&#146;s algorithm, 1099-1106
<DD>polygon culling, 1181-1184
<DD>PVS, precalculating, 1188-1189
</DL>
<DD><B>WalkBSPTree</B> function, <B>1106</B>
<DD><B>WalkTree</B> function, 1109-1110
</DL>
<DD>BSP compiler
<DL>
<DD><B>BuildBSPTree</B> function, <B>1125-1127</B>
<DD>overview, 1123
<DD><B>SelectBSPTree</B> function, <B>1124-1125</B>
</DL>
<DD>BSP models, Quake 3-D engine, 1284
<DD><B>BSWAP</B> instruction, 486 processor
<DL>
<DD>32-bit registers, using as two 16-bit registers, 253-254
<DD>rotating pixel bits, 252
</DL>
<DD>Bubble sort, 755
<DD>Buffer-filling routine, optimizations
<DL>
<DD>rearranging instructions, 418-419
<DD>reducing size of code, 416-418
<DD>stack addressing, 420
</DL>
<DD>Buffers, internal
<DL>
<DD>in 16-bit checksum program, 15-16
<DD>in search engine, 114-115
</DL>
<DD><B>BuildBSPTree</B> function, <B>1125-1127</B>
<DD><B>BuildGET</B> function, <B>768-769</B>
<DD><B>BuildGETStructure</B> function, <B>747-748</B>
<DD><B>BuildMaps</B> function, <B>353-355</B>
<DD><B>BuildTree</B> function, <B>1112</B>
<DD>Bus access
<DL>
<DD>8088 processor, 81, 99-101
<DD>Pentium processor, 377
</DL>
<DD>Byte registers, 486 processor, 242-245
<DD>Byte-<B>OUT</B> instruction, 429
<DD>Byte-per-pixel mode. <I>See</I> Mode X.
<DD><BIG><B>C</B></BIG>
<DD>C library functions
<DL>
<DD><B>getc()</B> function, 12, 14
<DD><B>memchr()</B> function, 116
<DD><B>memcmp()</B> function, 116
<DD><B>memcpy()</B> function, 1147-1148
<DD><B>memset()</B> function, 727
<DD>optimization, 15
<DD><B>read()</B> function, 12, 121
<DD><B>strstr()</B> function, 115
</DL>
<DD>Cache, internal. <I>See</I> Internal cache.
<DD>Cache lines, Pentium processor, 374
<DD>Calculations, redundant, and optimization, 682-683
<DD><I>Calculus and Analytic Geometry</I> (book), 1135
<DD><B>CALL</B> instruction
<DL>
<DD>486 processor, 241-242
<DD>Pentium processor, 404
</DL>
<DD>Carmack, John
<DL>
<DD>and id Software, 1118
<DD>overdraw, 1184-1186
<DD>subdivision rasterization, 1266-1267, <B>1267-1270</B>
</DL>
<DD>Carry flag
<DL>
<DD><B>DEC</B> instruction, 148
<DD><B>INC</B> vs. <B>ADD</B> instructions, 147-148
<DD>LOOP instruction, 148
<DD>rotating bits through, 185
<DD>in word count program (David Stafford), 317-319
</DL>
<DD>Cats, shipping via air freight, 697-698
<DD><B>Cellmap</B> class, <B>325-329, 333-335, 341-345</B>
<DD>Cellmap wrapping, Game of Life, 331-332, <B>333-335, 336,</B> 337-338
<DD><B>Cell_state</B> method, <B>327, 334, 344</B>
<DD>CGA (Color/Graphics Adapter)
<DL>
<DD>display adapter cycle-eater, 104
<DD>VGA compatibility with, 430
</DL>
<DD>Challenges
<DL>
<DD>Game of Life
<DL>
<DD>rules, 346, 350
<DD>3-cell-per-word implementation (David Stafford), 351-352, <B>353-363,</B> 363-365
</DL>
<DD><B>ScanBuffer</B> routine, 305, 307-319
</DL>
<DD>Change list, in Game of Life, 363-366
<DD>Chaplin, Michael, 776
<DD>Character/attribute map, VGA mode 3, 517
<DD>Chartreuse moose story, 399
<DD>Checksum programs. <I>See</I> 16-bit checksum program; TCP/IP checksum program.
<DD>Chunky bitmap conversion demo program, <B>505-508</B>
<DD>Chunky bitmaps, converting to planar, 504-505, <B>505-508</B>
<DD>Circular linked lists, 288-292
<DD><B>Clear_cell</B> method, <B>327, 334, 343</B>
<DD><B>ClearEdgeLists</B> function, <B>1236-1237</B>
<DD>Clements, Willem, <B>313-315</B>
<DD>Client-server architecture, and QuakeWorld, 1291
<DD>Clipping
<DL>
<DD><I>See also</I> Hidden surface removal (HSR); Visible surface determination (VSD).
<DD>arithmetic imprecision, handling, 1240
<DD>in BSP tree rendering, 1158-1159
<DD>line segments, clipping to planes, 1195-1197
<DD>masked copying, Mode X, 923
<DD>overview, 1195
<DD>polygon clipping
<DL>
<DD><B>BackRotateVector</B> function, <B>1203</B>
<DD>clipping to frustum, 1200, <B>1201-1206,</B> 1206-1207
<DD><B>ClipToFrustum</B> function, 1204
<DD><B>ClipToPlane</B> function, 1199
<DD>optimization, 1207
<DD>overview, 1197-1200
<DD><B>PolyFacesViewer</B> function, <B>1203</B>
<DD><B>ProjectPolygon</B> function, <B>1201</B>
<DD><B>SetUpFrustum</B> function, <B>1204</B>
<DD><B>SetWorldspace</B> function, <B>1204</B>
<DD><B>TransformPoint</B> function, <B>1203</B>
<DD><B>TransformPolygon</B> function, <B>1203</B>
<DD><B>UpdateViewPos</B> function, <B>1202</B>
<DD><B>UpdateWorld</B> function, <B>1205</B>
<DD>viewspace clipping, 1207
<DD><B>ZSortObjects</B> function, <B>1201</B>
</DL>
</DL>
<DD><B>ClipToFrustum</B> function, <B>1204</B>
<DD><B>ClipToPlane</B> function, <B>1199</B>
<DD>Clock cycles
<DL>
<DD><I>See also</I> Cycle-eaters.
<DD>address calculation pipeline, 238-240
<DD>branch prediction, 377-378
<DD>byte registers and lost cycles, 242-245
<DD>cross product floating point optimization, 1171, 1172
<DD>and data alignment, 213-215
<DD>data transfer rates, 81, 82
<DD>dot product floating point optimization, 1170
<DD>dual-pipe execution, 405
<DD>effective address calculations
<DL>
<DD>286 and 386 processors, 223-225
<DD>Pentium processor, 375-376
</DL>
<DD>8088 processor
<DL>
<DD>data transfer rates, 81, 82
<DD>memory access, 82, 83-85
</DL>
<DD>floating point instructions, 1167-1170
<DD>486 processor
<DL>
<DD>address calculation pipeline, 238-240, 250
<DD>byte registers and lost cycles, 242-245
<DD>indexed addressing, 237-238
<DD>stack addressing, 241-242
<DD>32-bit addressing modes, 256-258
</DL>
<DD><B>FXCH</B> instruction, 1170
<DD>indexed addressing, 237-238
<DD>instruction execution times, 86-93
<DD>lockstep execution, 390-394, 400-403
<DD>matrix transformation optimization, 1173
<DD>memory access, 82, 83-85
<DD>non-alignment penalties, 376
<DD>non-word-alignment penalty, 217
<DD>1/z value of planes, calculating, 1221
<DD><B>OUT</B> instructions, 843, 1082-1083
<DD>Pentium processor
<DL>
<DD>branch prediction, 377-378
<DD>cross product floating point optimization, 1171, <B>1172</B>
<DD>dot product floating point optimization, 1170
<DD>effective address calculations, 375-376
<DD>floating point instructions, 1167-1168
<DD><B>FXCH</B> instruction, 1170
<DD>initial pipe, effect of, 405
<DD>lockstep execution, 390-394, 400-403
<DD>matrix transformation optimization, 1173
<DD>non-alignment penalties, 376
<DD>pipelining, 1168-1170
<DD>prefix bytes, 376, 395, 407
</DL>
<DD>prefix bytes, 376, 395, 407
<DD>vs. program size, 28
<DD>projection, floating point optimization, 1174
<DD>stack addressing, 241-242
<DD>string instructions, 82
<DD>system wait states, 211
<DD>32-bit addressing modes, 256-258
<DD>386 processor, effective address calculation, 223-225
<DD>286 processor
<DL>
<DD>effective address calculation, 223-225
<DD>system wait states, 211
</DL>
</DL>
<DD><B>CMP</B> instruction
<DL>
<DD>operands, order of, 306
<DD>vs. <B>SCASW,</B> 161
</DL>
<DD><B>CMPXCHG8B</B> instruction, Pentium processor, 378
<DD>Code alignment
<DL>
<DD>386 processor, 218
<DD>286 processor, 215-218
</DL>
<DD>Code generator, for Game of Life (David Stafford), 351-352, 353-363, 363-365
<DD>Code recursion
<DL>
<DD>vs. data recursion, 1108-1110
<DD>Euclid&#146;s algorithm, 198-199
</DL>
<DD>Collision detection demo program, <B>531-534</B>
<DD>Color
<DL>
<DD>adapter-dependent mapping, 1036
<DD>color perception research, 1035
<DD>reflective vs. emissive, 1035
</DL>
<DD>Color Compare register, 531
<DD>Color cycling
<DL>
<DD>bit-by-bit loading of DAC, 650-651
<DD>demo program, 643, <B>644-648,</B> 648-649
<DD>interleaved loading of DAC, 649-650
<DD>loading DAC, 640-643
<DD>overview, 639-640
<DD>using page flipping, 650
<DD>using subset of DAC, 649
</DL>
<DD>Color cycling demo program, 643, <B>644-648,</B> 648-649
<DD>Color Don&#146;t Care register, 534
<DD>Color Don&#146;t Care register demo program, <B>535-537,</B> 535
<DD>Color mapping demo program, EGA, <B>551-555</B>
<DD>Color models. <I>See</I> RGB (red, green, blue) color model.
<DD>Color paging, 628-629
<DD>Color path, VGA
<DL>
<DD>color paging, 628-629
<DD>DAC (Digital/Analog Converter), 626-628
<DD>palette RAM, 626
</DL>
<DD>Color planes. <I>See</I> Planes, VGA.
<DD>Color Select register, 628-629
<DD>Color selection
<DL>
<DD>EGA
<DL>
<DD>overscan, 555-556
<DD>palette registers, 548-551, <B>551-555</B>
<DD>screen blanking, <B>556-557</B>
</DL>
<DD>VGA, 557
</DL>
<DD><B>ColorBarsUp</B> subroutine, <B>604</B>
<DD>Color-forcing demo program, <B>474-476</B>
<DD>Color-patterned lines demo program, <B>509-515</B>
<DD>Compiled DLLs, Quake 2, 1293
<DD>Compiler-based optimization
<DL>
<DD>cautions for use of, 9
<DD>data recursion vs. code recursion, 1112-1113
<DD>in <B>FindIDAverage</B> function, <B>159</B>
</DL>
<DD>Compilers
<DL>
<DD>vs. assembly language programmers, 154-155
<DD>avoiding thinking like, 152, 154-155
<DD>bitblt compiler for Game of Life (David Stafford), 351-352, <B>353-363,</B> 363-365
<DD>handling of segments, 154
</DL>
<DD>Complex polygons
<DL>
<DD>defined, 710, 742
<DD>edges, keeping track of, 742-744, 753, 755, 756
<DD>polygon-filling programs, <B>745-752, 754</B>
</DL>
<DD><I>Computational Geometry, An Introduction</I> (book), 759-760
<DD><I>Computer Graphics: Principles and Practice</I> (book), 660, 934, 1121
<DD><I>Computer Graphics</I> (book), 1135, 1157
<DD><B>ConcatXforms</B> function
<DL>
<DD>assembly implementation, <B>997-999, 1019-1022</B>
<DD>C-language implementation, <B>944, 976</B>
</DL>
<DD><B>CONSTANT_TO_INDEXED_REGISTER</B> macro, <B>594</B>
<DD>Coordinate systems
<DL>
<DD>left-handed, 1140
<DD>right-handed, 935-937
</DL>
<DD><B>Copy_cells</B> method, 327, 333
<DD><B>CopyDirtyRectangles</B> function, 850
<DD><B>CopyDirtyRectangleToScreen</B> function, <B>866-867</B>
<DD>Copying
<DL>
<DD>bytes between registers, 172
<DD>pixels, using latches (Mode X), <B>905-907,</B> 908,
</DL>
<DD>
<B>871</B>
<DD><B>CopyScreenToScreenMaskedX</B> subroutine, 918, <B>919-921</B>
<DD><B>CopyScreenToScreenX</B> subroutine, <B>905-907,</B> 908
<DD><B>CopySystemToScreenMaskedX</B> subroutine, <B>916-918</B>
<DD><B>CopySystemToScreenX</B> subroutine, 908, <B>909-911</B>
<DD><B>CosSin</B> subroutine, <B>994-996,</B> 999, <B>1013-1015</B>
<DD><B>Count_neighbors</B> method, <B>334-335</B>
<DD>CPU reads from VGA memory, 526
<DD><B>CPUID</B> instruction, Pentium processor, 378
<DD><B>CreateAlignedMaskedImage</B> function, 922-923
<DD>Cross products
<DL>
<DD>calculating, 955-956, 1139-1140
<DD>floating point optimization, 1171, 1172
</DL>
<DD>CRT Controller, VGA. <I>See</I> CRTC (CRT Controller), VGA.
<DD>CRTC (CRT Controller), VGA
<DL>
<DD>addressing, 427-428
<DD>Line Compare register, 565
<DD>Overflow register, 565
<DD>shearing, 813-814
<DD>start address registers, setting, 583
</DL>
<DD>Cycle-eaters
<DL>
<DD>286 and 386 processors
<DL>
<DD>data alignment cycle-eater,
<DD>display adapter cycle-eater, 219-221
<DD>DRAM refresh cycle-eater, 219
<DD>overview, 209-210
<DD>prefetch queue cycle-eater, 211-212
<DD>system wait states, 210-212
</DL>
<DD>data alignment cycle-eater
<DL>
<DD>386 processor, 218
<DD>286 processor, 213-215
</DL>
<DD>display adapter cycle-eater
<DL>
<DD>286 and 386 processors, 219-221
<DD>8088 processor, 101-108
</DL>
<DD>DRAM refresh cycle-eater
<DL>
<DD>286 and 386 processors, 219
<DD>8088 processor, 95-99, 108
</DL>
<DD>8-bit bus cycle-eater, 79-85, 108
<DD>8088 processor
<DL>
<DD>display adapter cycle-eater, 101-108
<DD>DRAM refresh cycle-eater, 95-99, 108
<DD>8-bit bus cycle-eater, 79-85, 108
<DD>prefetch queue cycle-eater, 86-94, 108
<DD>wait states, 99-101
</DL>
<DD>overview
<DL>
<DD>286 and 386 processors, 209-210
<DD>8088 processor, 78-79, 80
</DL>
<DD>prefetch queue cycle-eater
<DL>
<DD>286 and 386 processors, 211-212
<DD>8088 processor, 86-94, 108
</DL>
<DD>system wait states, 210-212
<DD>wait states, 99-101
</DL>
<DD>Cycles. <I>See </I>Clock cycles; Cycle-eaters.
<DD><BIG><B>D</B></BIG>
<DD>DAC (Digital/Analog Converter)
<DL>
<DD>color cycling
<DL>
<DD>bit-by-bit loading, 650-651
<DD>color cycling demo program, 643, <B>644-648,</B> 648-649
<DD>interleaved loading, 649-650
<DD>problems, 640-643
<DD>using subset of, 649
</DL>
<DD>Data register, 642-643
<DD>index wrapping, 651
<DD>loading
<DL>
<DD>bit-by-bit loading, 650-651
<DD>directly, 642-643
<DD>interleaved loading, 649-650
<DD>via VGA BIOS, 641-642, 648
<DD>and Write Index register, 642-643, 651
</DL>
<DD>Mask register, blanking screen, 651
<DD>Read Index register, 651-652
<DD>reading, 651-652
<DD>setting registers, 630, 631-632
<DD>in VGA color path, 626-628
<DD>Write Index register
<DL>
<DD>DAC index wrapping, 651
<DD>loading DAC, 642-643
</DL>
</DL>
<DD>DAC registers demo program, 632-635
<DD>Data alignment cycle-eater
<DL>
<DD>386 processor, 218
<DD>286 processor, 213-215
</DL>
<DD>Data bus, 8-bit
<DL>
<DD><I>See also</I> 8-bit bus cycle-eater.
</DL>
<DD>Data manipulation instructions, and flags, 147
<DD>Data recursion
<DL>
<DD>vs. code recursion, 1108
<DD>Euclid&#146;s algorithm, 200
<DD>inorder tree traversal, 1108, <B>1109-1110,</B> 1110
</DL>
<DD>Data register, loading DAC, 642-643
<DD>Data Rotate register
<DL>
<DD>barrel shifter, controlling, 463
<DD>vs. CPU-based rotations, 489
<DD>effect on ALUs, 452
</DL>
<DD>Data rotation, VGA
<DL>
<DD>barrel shifter, 463-464
<DD>bit mask, 464-471
<DD>CPU vs. Data Rotate register, 489
</DL>
<DD>Data transfer rates
<DL>
<DD>display adapters, 220
<DD>8088 processor vs. 8086 processor, 81, 82
<DD>286 processor, 212
</DL>
<DD>DDA (digital differential analyzer) texture mapping
<DL>
<DD>assembly implementation, <B>1069-1073,</B> 1074
<DD>C implementation, <B>1053-1058</B>
<DD>disadvantages, 1052-1053, 1059
<DD><B>DrawTexturedPolygon,</B> 1055-1056</B>
<DD>hardware dependence, 1053
<DD>multiple adjacent polygons, 1068
<DD>optimized implementation, <B>1069-1073,</B> 1074
<DD>orientation independence, 1065-1067, <B>1067</B>
<DD>performance, 1074
<DD><B>ScanOutLine</B> function, <B>1058-1059, 1067, 1069-1073,</B> 1074
<DD><B>SetUpEdge</B> function, <B>1057-1058</B>
<DD>StepEdge function, 1056-1057
<DD>techniques, 1048-1051
</DL>
<DD><I>DDJ Essential Books on Graphics Programming</I> (CD), 1157
<DD><B>DEC</B> instruction
<DL>
<DD>and Carry flag, 148
<DD>memory accesses, 83
<DD>vs. <B>SUB,</B> 219
</DL>
<DD><B>DEC/JNZ</B> sequence, 139
<DD>Delay sequences
<DL>
<DD>loading palette RAM or DAC registers, 632
<DD>VGA programming, 558
</DL>
<DD><B>DeleteNodeAfter</B> function, <B>284</B>
<DD>Depth sorting of nonconvex objects, 1000, <B>1001-1002</B>
<DD>Diffuse shading, 1023-1025, <B>1025-1027</B>
<DD>Digital differential analyzer. <I>See</I> DDA (digital differential analyzer).
<DD>Direct far jumps, 186
<DD>Direct memory access. <I>See</I> DMA.
<DD>Directed lighting, and shading, 1023, 1028
<DD>Directives
<DL>
<DD><B>EVEN,</B> 214
<DD><B>NOSMART,</B> 72
</DL>
<DD>Dirty-rectangle animation
<DL>
<DD>demo program, C implementation, <B>847-851, 863-869</B>
<DD>description, 844-845
<DD>ordering rectangles, 873
<DD>overlapping rectangles, 872-873
<DD>vs. page flipping, 846, 862
<DD>performance, 873
<DD>system memory buffer size, 851
<DD>writing to display memory, 856-857
</DL>
<DD>Disk caches, 19
<DD>Display adapter cycle-eater
<DL>
<DD>286 and 386 processors, 219-221
<DD>data transfer rates, 220
<DD>8088 processor
<DL>
<DD>graphics routines, impact on, 106
<DD>optimizing for, 107
<DD>overview, 101-104
<DD>performance, impact on, 104
<DD>read/write/modify operations, 107
<DD>wait states, 99-101
</DL>
</DL>
<DD>Display memory
<DL>
<DD><I>See also</I> Bit mask; Displaymemory access.
<DD>Mode X
<DL>
<DD>copying between memory locations, <B>905-907,</B> 908
<DD>copying from system memory, 908, <B>909-911</B>
<DD>masked copy from system memory, <B>916-918,</B> 916
<DD>masked copying between locations, 918-919, <B>919-921</B>
<DD>memory allocation, 903-904
</DL>
<DD>running code from, 104
<DD>start address, changing, 857
<DD>VGA
<DL>
<DD>access times, 842-844
<DD>360x480 256-color mode, 621-622
<DD>320 x 400 256-color mode, 591-593, 605
</DL>
</DL>
<DD>Display memory access
<DL>
<DD><I>See also</I> Display memory; Memory access.
<DD>display adapter cycle-eater, 101-103, 105, 107
<DD>and string instructions, 107
<DD>VGA access times, 842-844
<DD>wait states, 101-103, 220, 733
</DL>
<DD>Display memory planes. <I>See</I> Planes, VGA.
<DD><B>DIV</B> instruction, 32-bit division, 181-184, 1008
<DD>Divide By Zero interrupt, 181
<DD>Divide-by-N timer mode, 45
<DD>Division, 32-bit, 181-184, 1008
<DD>DMA (direct memory access), and DRAM refresh, 95
<DD>&#147;Don&#146;t care&#148; planes, 535
<DD>DOS function calls
<DL>
<DD>overhead, 9
<DD>and restartable blocks, 123
</DL>
<DD>Dot products
<DL>
<DD>calculating, 1135-1137
<DD>calculating light intensity, 1137
<DD>floating point optimization, 1170, <B>1171</B>
<DD>line segments, clipping to planes, 1196-1197
<DD>projection, 1141-1142
<DD>rotation, 1143-1144
<DD>sign of, 1140-1141
<DD>of unit vectors, 1136
<DD>of vectors, 1135-1136
</DL>
<DD>Double-DDA texture mapping. <I>See</I> DDA (digital differential analyzer) texture mapping.
<DD><B>D_PolysetRecursiveTriangle</B> function, <B>1267-1270</B>
<DD><I>Dr. Dobbs Journal,</I> 1190
<DD>DRAM (dynamic RAM) refresh cycle-eater
<DL>
<DD>286 and 386 processors, 219
<DD>8088 processor
<DL>
<DD>impact on performance, 97-98
<DD>optimizing for, 98-99
<DD>overview, 95-97
<DD>vs. wait states, 100
</DL>
<DD>and 8253 timer chip, 95
<DD>and Zen timer, 99
</DL>
<DD><B>Draw360&#215;480Dot</B> subroutine, <B>613-614</B>
<DD><B>DrawBackground</B> function, <B>928</B>
<DD>Draw-buffers, and beam trees, 1187
<DD><B>DrawBumperList</B> function, <B>823</B>
<DD><B>DrawEntities</B> function, <B>849, 866</B>
<DD><B>DrawGridCross</B> subroutine, <B>808</B>
<DD><B>DrawGridVert</B> subroutine, <B>808-809</B>
<DD><B>DrawHorizontalLineList</B> function
<DL>
<DD>monotone-vertical polygons, filling, <B>765</B>
<DD>non-overlapping convex polygon
<DL>
<DD>assembly implementation, <B>734</B>
<DD>C implementation, <B>717,</B> 720-721
<DD>using memset() function, 727, <B>729</B>
</DL>
</DL>
<DD><B>DrawHorizontalLineList</B> subroutine, <B>941-943</B>
<DD><B>DrawHorizontalLineSeg</B> function
<DL>
<DD>assembly implementation, <B>754</B>
<DD>C implementation, <B>750-751</B>
</DL>
<DD><B>DrawHorizontalRun</B> function, <B>692</B>
<DD><B>DrawImage</B> subroutine, <B>828</B>
<DD>Drawing
<DL>
<DD><I>See also</I> Line-drawing algorithms; Lines; 3-D drawing.
<DD>fill patterns, using latches, 453
<DD>pixel drawing
<DL>
<DD><B>EVGADot</B> function, <B>661-662,</B> 669-670
<DD>optimization, 1074, 1086
<DD>painter&#146;s algorithm and overdraw problem, 1184
</DL>
<DD>single-color drawing with write mode 3, 831-832
<DD>speeding up, 727-729
<DD>text
<DL>
<DD>bitmapped text using bit mask, <B>466-469,</B> 470-471
<DD>bitmapped text using write mode 3, <B>484-489,</B> 489-490, <B>490-496</B>
<DD>solid text using latches, 1039-1041, <B>1042-1044</B>
<DD>using write mode 0, 832-833
</DL>
</DL>
<DD><B>DrawLine</B> function, <B>785</B>
<DD><B>DrawMasked</B> subroutine, <B>870</B>
<DD><B>DrawObject</B> subroutine, <B>809-810</B>
<DD><B>Draw_pixel</B> function, <B>328, 330</B>
<DD><B>DrawPObject</B> function, <B>978-979, 1025-1027</B>
<DD><B>DrawRect</B> subroutine, <B>826-827</B>
<DD><B>DrawSpans</B> function, <B>1236</B>
<DD><B>DrawSplitScreen</B> function, <B>824</B>
<DD><B>DrawTextString</B> subroutine, <B>1043-1044</B>
<DD><B>DrawTexturedPolygon</B> function, <B>1055-1056</B>
<DD><B>DrawVerticalRun</B> function, <B>692</B>
<DD><B>DrawVisibleFaces</B> function, <B>961</B>
<DD><B>DrawWuLine</B> function
<DL>
<DD>assembly implementation, <B>787-791</B>
<DD>C implementation, <B>780-781</B>
</DL>
<DD>Duntemann, Jeff, 127-128
<DD>Dynamic lighting
<DL>
<DD>in GLQuake, 1289-1290
<DD>in Quake 3-D engine, 1282-1283
</DL>
<DD>Dynamic objects, and BSP trees, 1100-1101
<DD>Dynamic palette adjustment, 1039
<DD>Dynamic RAM. <I>See</I> DRAM (dynamic RAM) refresh.
<DD><BIG><B>E</B></BIG>
<DD>EA (effective address) calculations
<DL>
<DD>286 and 386 processors, 223-225
<DD>8088 processor, 129
<DD>486 processor
<DL>
<DD>address calculation pipeline, 238-240
<DD>stack addressing, 241-242
</DL>
<DD>Pentium processor, 375-376
<DD>320&#215;400 256-color mode, 599-600
</DL>
<DD>EBP register, 257
<DD>Edge tracing
<DL>
<DD>overview, 711-713
<DD><B>ScanEdge</B> function
<DL>
<DD>assembly implementation, <B>735-738,</B> 735
<DD>floating-point C implementation, <B>716-717</B>
<DD>integer-based C implementation, <B>730-732</B>
</DL>
</DL>
<DD>Edge triggered devices, 316
<DD>Edges vs. spans, sorted span hidden surface removal, 1215-1220
<DD>EGA BIOS, video function 10H, 550-551, 555
<DD>EGA (Enhanced Graphics Adapter)
<DL>
<DD>color mapping, 548-551, <B>551-555</B>
<DD>and display adapter cycle-eater, 104-108
<DD>mode 10H, 515-517, <B>518-521</B>
<DD>palette registers, 549-550
<DD>registers, and high-level languages, 548
<DD>screens, capturing and restoring, 541-542, <B>543-547,</B> 547-548
<DD>split screens
<DL>
<DD>EGA bug, 573-574
<DD>horizontal panning, 574-575, <B>575-582,</B> 583
<DD>overview, 563-565
<DD>registers, setting, 573
<DD>safety of, 585
<DD>split screen demo program, 565, <B>566-572,</B> 572
<DD>text mode, 584
<DD>turning on and off, 565
</DL>
</DL>
<DD>8-bit bus cycle-eater
<DL>
<DD>286 and 386 processors, 210
<DD>8088 processor
<DL>
<DD>effects on performance, 82
<DD>optimizing for, 83-85
<DD>overview, 79-82
<DD>and registers, 85
</DL>
</DL>
<DD>8086 processor vs. 8088 processor, 79-81
<DD>8088 processor
<DL>
<DD><B>CMP</B> instruction, 161, 306
<DD>cycle-eaters
<DL>
<DD>8-bit bus cycle-eater, 79-85
<DD>display adapter cycle-eater, 101-108
<DD>DRAM refresh cycle-eater, 95-99
<DD>overview, 78-79, 80
<DD>prefetch queue cycle-eater, 86-94
<DD>wait states, 99-101
</DL>
<DD>display memory access, 220
<DD>vs. 8086 processor, 79-81
<DD>effective address calculation options, 129
<DD><B>LAHF</B> and <B>SAHF</B> instructions, 148
<DD><B>LEA</B> vs. <B>ADD,</B> 130
<DD><B>LODSB</B> instruction, 304
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>memory variables, size of, 83-85
<DD>stack-based variables, placement of, 184-184
</DL>
<DD>8253 timer chip
<DL>
<DD>and DRAM refresh, 95
<DD>reference material, 72
<DD>resetting, 43
<DD>system clock inaccuracies
<DL>
<DD>long-period Zen timer, 53, 54
<DD>Zen timer, 43, 45-46, 48
</DL>
<DD>timer 0
<DL>
<DD>operation, 44
<DD>stopping, 54, 65
</DL>
<DD>timer modes, 44, 45
<DD>timer operation, 43-45
<DD>undocumented features, 54, 65
</DL>
<DD>Emissive color, vs. reflective color, 1035
<DD>Enable Set/Reset register
<DL>
<DD>setting drawing color, 666
<DD>specifying plane, 474
</DL>
<DD><B>EnableSplitScreen</B> function, 824
<DD><B>ENTER</B> instruction
<DL>
<DD>486 processor, 241-242
<DD>Pentium processor, 377
<DD>286 processor, 221
</DL>
<DD><B>Enter_display_mode</B> function, <B>328, 362</B>
<DD>Entities, Quake 3-D engine
<DL>
<DD>BSP models, 1284
<DD>particles, 1287
<DD>polygon models, 1285-1286
<DD>sprites, 1287
<DD>subdivision rasterization, 1286
<DD>z-buffering, 1285-1286
</DL>
<DD><B>EraseEntities</B> function, <B>850, 867</B>
<DD>Error accumulation, Wu antialiasing algorithm, 778-779, 792
<DD>EU (Execution Unit)
<DL>
<DD>286 and 386 processors
<DL>
<DD>instruction execution times, 223-225
<DD>and prefetch queue, 210
</DL>
<DD>8088 processor
<DL>
<DD>8-bit bus cycle-eater, 80
<DD>prefetch queue cycle-eater, 86
<DD>wait states, 101
</DL>
</DL>
<DD>Euclid&#146;s algorithm
<DL>
<DD>algorithm, 197
<DD>optimized assembly implementation, <B>200-202</B>
<DD>recursive implementations, <B>198, 200</B>
</DL>
<DD><B>EVEN</B> directive, 214
<DD><B>EVGADot</B> function, <B>661-662,</B> 669-670
<DD><B>EVGALine</B> function
<DL>
<DD>Bresenham&#146;s algorithm
<DL>
<DD>assembly implementation, 671, <B>675-677</B>
<DD>C-language implementation, <B>664-665,</B> 665-668, 670-671
</DL>
<DD>360&#215;480 256-color mode line drawing program, <B>616-617</B>
</DL>
<DD>Execution times. <I>See </I>Clock cycles; Instruction execution time.
<DD><B>Exit_display_mode</B> function, <B>328, 329, 362</B>
<DD><BIG><B>F</B></BIG>
<DD><B>FADD</B> instruction, Pentium processor, 1167-1170
<DD>Far jumps, to absolute addresses, 186-187
<DD><B>FDIV</B> instruction, Pentium processor, 1167-1170
<DD>Fetch time
<DL>
<DD><I>See also</I> Instruction fetching.
<DD>286 and 386 processors, 210, 211
<DD>8088 processor, 86-93
</DL>
<DD>Files
<DL>
<DD>reading from
<DL>
<DD><B>getc()</B> function, 12, 14
<DD><B>read()</B> function, 12
</DL>
<DD>restartable blocks, 16
<DD>text, searching for. <I>See</I> Search engine.
</DL>
<DD>Fill patterns, drawing using latches, 453
<DD><B>FillConvexPolygon</B> function, <B>714-716</B>, 720-721
<DD><B>FillMonotoneVerticalPolygon</B> function, <B>763-764</B>
<DD><B>FillPatternX</B> subroutine, 899, <B>900-903</B>, 903-904
<DD><B>FillPolygon</B> function
<DL>
<DD>complex polygons, <B>746</B>
<DD>monotone-vertical polygons, <B>767</B>
</DL>
<DD><B>FillRect</B> subroutine, <B>869-870</B>
<DD><B>FillRectangleX</B> subroutine
<DL>
<DD>four-plane parallel processing, 888-891, <B>891-893</B>
<DD>pixel-by-pixel plane selection, <B>885-887</B>
<DD>plane-by-plane processing, <B>887-889</B>
</DL>
<DD><B>FindIDAverage</B> function
<DL>
<DD>assembly implementations
<DL>
<DD>based on compiler optimization, <B>160</B>
<DD>data structure reorganization, 163, <B>165-166</B>
<DD>unrolled loop, 161, <B>162</B>
</DL>
<DD>C language implementation, <B>158</B>
<DD>compiler optimization, <B>159</B>
</DL>
<DD><B>FindNodeBeforeValue</B> function, <B>289</B>
<DD><B>FindNodeBeforeValueNotLess</B> function, <B>286, 287</B>
<DD><B>FindString</B> function
<DL>
<DD>Boyer-Moore algorithm, <B>269, 271-274, 274-277</B>
<DD>overview, 175
<DD>scan-on-first-character approach, <B>176</B>
<DD>scan-on-specified-character approach, <B>178</B>
</DL>
<DD><B>FirstPass</B> function, <B>355-358</B>
<DD><B>Fix</B> function, <B>358,</B> 365
<DD><B>FixedDiv</B> subroutine, <B>982, 993, 1010-1012</B>
<DD>FIXED_MUL macro, <B>1016-1017</B>
<DD><B>FixedMul</B> subroutine, <B>981, 993-994, 1009-1010</B>
<DD>Fixed-point arithmetic
<DL>
<DD>vs. floating point, 985, 1206
<DD>vs. integer arithmetic, 730, 1065
<DD>32-bit fixed-point arithmetic, 1086-1089, <B>1090-1091,</B> 1092-1093
</DL>
<DD>Flags
<DL>
<DD>and <B>BSWAP</B> instruction, 254
<DD>Carry flag, 147-148, 185, 317-319
<DD><B>INC</B> vs. <B>ADD,</B> 147-148
<DD>and <B>LOOP</B> instruction, 148
<DD>and <B>NOT</B> instruction, 146-147
</DL>
<DD><B>FLD</B> instruction, Pentium processor, 1167-1170
<DD>Floating point optimization
<DL>
<DD>clock cycles, core instructions, 1167-1168
<DD>cross product optimization, 1171, <B>1172</B>
<DD>dot product optimization, 1170, <B>1171</B>
<DD><B>FXCH</B> instruction, 1169-1170
<DD>interleaved instructions, 1169-1170
<DD>matrix transformation optimization, 1172-1173, <B>1173-1174</B>
<DD>overview, 1167-1170
<DD>pipelining, 1168-1170
<DD>projection to screen space, 1174
<DD>rounding control, 1174-1175
</DL>
<DD>Floating-point calculations
<DL>
<DD>vs. fixed-point calculations, 985, 1206
<DD>vs. integer calculations, 730
</DL>
<DD><B>FMUL</B> instruction
<DL>
<DD>486 processor, 236
<DD>Pentium processor, 1167-1170
</DL>
<DD>486 processor
<DL>
<DD>AX register, setting to absolute value, 172
<DD>byte registers and lost cycles, 242-245
<DD><B>CMP</B> instruction
<DL>
<DD>operands, order of, 306
<DD>vs. <B>SCASW,</B> 161
</DL>
<DD>copying bytes between registers, 172
<DD>and display adapter cycle-eater, 107
<DD>indexed addressing, 237-238
<DD>internal cache
<DL>
<DD>effect on code timing, 246
<DD>optimization, 236
</DL>
<DD><B>LAHF</B> and <B>SAHF</B> instructions, 148
<DD><B>LEA</B> instruction, vs. <B>ADD,</B> 131
<DD><B>LODSB</B> instruction, 304
<DD><B>LODSD</B> instruction, vs. <B>MOV/LEA</B> sequence, 171
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction, vs. <B>DEC/JNZ</B> sequence, 139
<DD><B>MOV</B> instruction, vs. <B>XCHG,</B> 377
<DD>n-bit vs. 1-bit shift and rotate instructions, 255-256
<DD>Pentium code, running on, 411
<DD>pipelining
<DL>
<DD>address calculation, 238-240, 250
<DD>stack addressing, 241-242
</DL>
<DD>rotation instructions, clock cycles, 185-186
<DD>stack-based variables, 184-184
<DD>32-bit addressing modes, 256-258
<DD>timing code, 245-246
<DD>using 32-bit register as two 16-bit registers, 253-254
<DD><B>XCHG</B> instruction, vs. <B>MOV,</B> 377, 832
</DL>
<DD>FPU, Pentium processor
<DL>
<DD>clock cycles, core instructions, 1167-1168
<DD>cross product optimization, 1171, <B>1172</B>
<DD>dot product optimization, 1170, <B>1171</B>
<DD><B>FXCH</B> instruction, 1169-1170
<DD>interleaved instructions, 1169-1170
<DD>matrix transformation optimization, 1172-1173, <B>1173-1174</B>
<DD>overview, 1167-1170
<DD>pipelining, 1168-1170
<DD>projection to screen space, 1174
<DD>rounding control, 1174-1175
</DL>
<DD>Frustum, clipping to, 1200, <B>1201-1206,</B> 1206-1207
<DD><B>FST</B> instruction, Pentium processor, 1167-1170
<DD><B>FSUB</B> instruction, Pentium processor, 1167-1170
<DD>Function 13H, VGA BIOS, 459
<DD>Function calls, performance, 153
<DD><I>Fundamentals of Interactive Computer Graphics</I> (book), 660
<DD><B>FXCH</B> instruction, Pentium processor, 1169-1170
<DD><BIG><B>G</B></BIG>
<DD>Game of Life
<DL>
<DD>abstraction and performance, 330-332, 345-346
<DD>byte-per-cell implementation, 339-340, <B>341-345</B>
<DD>C++ implementation
<DL>
<DD>basic, 324, <B>325-328</B>
<DD>optimized, <B>336,</B> 337-338
</DL>
<DD>cellmap-wrapped implementation, 331-332, <B>333-335,</B> 336, <B>337-338</B>
<DD>challenge to readers
<DL>
<DD>rules, 346, 350
<DD>3-cell-per-word implementation (David Stafford), 351-352, <B>353-363,</B> 363-365
</DL>
<DD>change list, 363-366
<DD>performance analysis, 329-330, 332, 338, 340, 350
<DD>re-examining problem, 338-339, 363
<DD>rules, 324
<DD>3-cell-per-word implementation
<DL>
<DD>discussion, 363-365
<DD>listing, 352-363
<DD>overview, 351-352
</DL>
</DL>
<DD>GC (Graphics Controller), VGA
<DL>
<DD>addressing, 427-428
<DD>architecture
<DL>
<DD>ALUs, 451-452
<DD>barrel shifter, 463-464
<DD>bit mask, 464-471
<DD>latches, 452-453
<DD>set/reset circuitry, 471-479
</DL>
<DD>Bit Mask register
<DL>
<DD>bit mask, controlling, 465
<DD>drawing solid text, 1040
<DD>setting inside a loop, 429
<DD>vs. write mode 3, 832, 844
</DL>
<DD>Color Compare register, 531
<DD>Data Rotate register
<DL>
<DD>barrel shifter, controlling, 463
<DD>vs. CPU-based rotations, 489
<DD>effect on ALUs, 452
</DL>
<DD>Enable Set/Reset register
<DL>
<DD>setting drawing color, 666
<DD>specifying plane, 474
</DL>
<DD>Graphics Mode register
<DL>
<DD>read mode 0, selecting, 525
<DD>read mode 1, selecting, 531
</DL>
<DD>Read Map register
<DL>
<DD>plane, selecting, for CPU reads, 526
<DD>planes, specifying to be read, 542
</DL>
<DD>Set/Reset register, 666
</DL>
<DD><B>Gcd()</B> function
<DL>
<DD>brute-force approach, 195
<DD>Euclid&#146;s algorithm
<DL>
<DD>code recursive approach, 198
<DD>data recursion approach, 200
</DL>
<DD>subtraction approach, 196
</DL>
<DD>GCD (Greatest Common Denominator) problem
<DL>
<DD>brute-force approach, 193-196
<DD>Euclid&#146;s algorithm, 197-200
<DD>subtraction approach, 196-197
</DL>
<DD><B>Gcd_recurs()</B> function, <B>199</B>
<DD>Generality, vs. performance, 335
<DD>Gerrold, David, 298
<DD>GET (global edge table), 744
<DD><B>Getc()</B> function
<DL>
<DD>overhead, 14
<DD>vs. <B>read()</B> function, 12
</DL>
<DD><B>GetNextKey</B> subroutine, <B>598, 605</B>
<DD><B>GetUpAndDown</B> function, <B>355</B>
<DD>Global edge table (GET), 744
<DD>GLQuake, 1288-1290
<DD>Gouraud shading
<DL>
<DD>overview, 1246-1247
<DD>perspective correction, 1248-1250
<DD>problems with, 1247-1250
</DL>
<DD>Graphics cards, and surface caching, 1261-1262
<DD>Graphics Controller, VGA. <I>See</I> GC (Graphics Controller), VGA.
<DD>Graphics Mode register
<DL>
<DD>read mode 0, selecting, 525
<DD>read mode 1, selecting, 531
</DL>
<DD>Graphics screen capture demo program, <B>543-545</B>
<DD>Graphics screen restore demo program, <B>545-547</B>
<DD>Graphics-to-text demo program, <B>518-521</B>
<DD>Great Buffalo Sauna Fiasco, 137-138
<DD>GUIs, and future of programming profession, 725-726
<DD><BIG><B>H</B></BIG>
<DD>Hardware dependence, DDA (digital differential analyzer) texture mapping, 1053
<DD>Hecker, Chris
<DL>
<DD>texture mapping insight, 1083
<DD>underlying functionality of different approaches, 1189
</DL>
<DD>Heinlein, Robert A., 1079-1080
<DD>Herbert, Frank, 1193
<DD>HGC (Hercules Graphics Card), 104
<DD>Hidden surface removal (HSR)
<DL>
<DD>backface removal, 954-957
<DD>depth sorting, 1000, 1001-1002
<DD>sorted spans approach
<DL>
<DD>abutting span sorting, 1229-1230
<DD><B>AddPolygonEdges</B> function, <B>1232-1233,</B> 1238
<DD>BSP order vs. 1/z order, 1220, 1226
<DD><B>ClearEdgeLists</B> function, <B>1236-1237</B>
<DD><B>DrawSpans</B> function, <B>1236</B>
<DD>edge sorting, 1220-1222
<DD>edges vs. spans, 1215-1220
<DD>independent span sorting, 1230, <B>1231-1238,</B> 1239-1241
<DD>intersecting span sorting, 1228-1229
<DD>1/z sorting, 1220-1222, 1227-1231, <B>1231-1238,</B> 1239-1241
<DD>overview, 1214-1215
<DD><B>PolyFacesViewer</B> function, <B>1232</B>
<DD>rotation instructions, clock cycles, 185-186
<DD><B>ScanEdges</B> function, <B>1234-1236,</B> 1238-1239
<DD><B>UpdateWorld</B> function, <B>1237-1238</B>
</DL>
</DL>
<DD>High school graduates in Hawaii, 991-992
<DD>Horizontal Pel Panning register, 442
<DD>Horizontal resolution, 360&#215;480 256-color mode, 620
<DD>Horizontal smooth panning. <I>See</I> Panning.
<DD><BIG><B>I</B></BIG>
<DD>id Software, 1118, 1190
<DD>Ideas, selling, 1193-1194
<DD>Illowsky, Dan, 187, 315
<DD>Image precedence. <I>See</I> Bit-plane animation.
<DD><B>IMUL</B> instruction
<DL>
<DD>486 processor, 236
<DD>on 386 processor, 173-174
</DL>
<DD><B>INC</B> instruction
<DL>
<DD>vs. <B>ADD,</B> 147-148, 219
<DD>and Carry flag, 147-148
</DL>
<DD>Incremental transformations of 3-D objects, 964
<DD>Independent span sorting
<DL>
<DD><B>AddPolygonEdges</B> function, <B>1232-1233,</B> 1238
<DD><B>ClearEdgeLists</B> function, <B>1236-1237</B>
<DD><B>DrawSpans</B> function, <B>1236</B>
<DD>overview, 1230
<DD><B>PolyFacesViewer</B> function, <B>1232</B>
<DD><B>ScanEdges</B> function, <B>1234-1236,</B> 1238-1239
<DD>texture mapping, 1238
<DD><B>UpdateWorld</B> function, <B>1237-1238</B>
</DL>
<DD>Index registers, VGA
<DL>
<DD>AC Index register, 443
<DD>overview, 427-428
</DL>
<DD>Indexed addressing, 237-238
<DD>Indirect far jumps, 186
<DD>Information, sharing, 1190, 1194
<DD><B>InitCellmap</B> function, <B>361</B>
<DD><B>InitializeCubes</B> function, <B>980-981</B>
<DD><B>InitializeFixedPoint</B> function, <B>977</B>
<DD><B>InitializeObjectList</B> function, <B>1001</B>
<DD><B>InitializePalette</B> function, <B>1037</B>
<DD><B>InitLinkedList</B> function, <B>289</B>
<DD>Inorder tree traversal
<DL>
<DD>code recursion vs. data recursion, 1107-1108
<DD>data recursive implementation, 1108, <B>1109-1110,</B> 1110
<DD>performance, 1111-1113
</DL>
<DD><B>INS</B> instruction, 221
<DD><B>InsertNodeSorted</B> assembly routine, <B>290</B>
<DD><B>InsertNodeSorted</B> function, <B>289</B>
<DD>Instruction execution times
<DL>
<DD><I>See also</I> Clock cycles; Zen timer.
<DD>DRAM refresh cycle-eater, 97, 99
<DD>8-bit bus cycle-eater, 82-85
<DD>estimating, 93
<DD>and instruction fetching, 225
<DD>vs. instruction size, 90-92, 93, 211
<DD>memory-addressing vs. register-only instructions, 223-225
<DD>prefetch queue cycle-eater, 86-93
</DL>
<DD>Instruction fetching
<DL>
<DD><I>See also</I> Prefetch queue cycle-eater.
<DD>code alignment, 215-218
<DD>8088 processor, 86-93
<DD>and instruction execution times, 225
<DD>Pentium processor, 374
<DD>and system wait states, 211
<DD>286 processor, 215-218
<DD>and wait states, 101
</DL>
<DD>Instruction size, 32-bit addressing modes, 257
<DD>Instructions, assembly language
<DL>
<DD>optimizing, 23-24
<DD>Pentium processor
<DL>
<DD>pairable instructions, 388, 390-394
<DD>V-pipe-capable instructions, 386-387
</DL>
<DD>size vs. execution time, 90-92, 93
</DL>
<DD>Integer calculations, vs. fixed-point, 730, 1065
<DD>Integers, sorting, 180-181
<DD>Interleaved color cycling, 649-650
<DD>Interleaved operations, Pentium processor
<DL>
<DD><B>FXCH</B> instruction and floating point operations, 1169-1170
<DD>matrix transformation, 1172-1173, <B>1173-1174</B>
<DD>overview, 394-395
<DD>TCP/IP checksum program, <B>408</B>
</DL>
<DD>Internal animation, 872
<DD>Internal buffering
<DL>
<DD><I>See also</I> Restartable blocks.
<DD>in 16-bit checksum program, 15-16
<DD>in search engine, 114-115
</DL>
<DD>Internal cache
<DL>
<DD>486 processor
<DL>
<DD>effect on optimization, 236
<DD>timing code, 246
</DL>
<DD>Pentium processor
<DL>
<DD>instruction fetching, 374
<DD>organization, 374-375
<DD>paired instructions, 391, 396
</DL>
</DL>
<DD>Internal indexing, VGA, 427-429
<DD>Internet support
<DL>
<DD>Quake 2, 1293
<DD>QuakeWorld, 1291
</DL>
<DD>Interrupts
<DL>
<DD>DAC, loading, 643, 648
<DD>Divide By Zero interrupt, 181
<DD>and <B>IRET</B> instruction, 227
<DD>and long-period Zen timer, 53, 66
<DD>and page flipping, 446
<DD>and <B>POPF</B> instruction, 226
<DD>and Zen timer, 43, 45-46
</DL>
<DD>Intersecting lines, 1121-1123
<DD>Intersecting span sorting, 1228-1229
<DD>Intuitive leaps, 1098
<DD><B>IRET</B> instruction, vs. <B>POPF</B> instruction, 226-231
<DD>IRQ0 interrupts, and Zen timer, 45
<DD><B>IS_VGA</B> equate, 572, 575
<DD><BIG><B>J</B></BIG>
<DD>Jet Propulsion Lab, color perception research, 1035
<DD><B>JMP $+2</B> instructions, 558, 632
<DD><B>JMP DWORD PTR</B> instruction, 186-187
<DD>Jumps, to absolute addresses, 186-187
<DD><BIG><B>K</B></BIG>
<DD>Kennedy, John, 171-172
<DD>Kent, Jim
<DL>
<DD>dynamic palette adjustment, 1039
<DD>monotone-vertical polygons, filling, 760-761
</DL>
<DD>Kissing, learning to,
<DL>
<DD>281-282
</DL>
<DD>Kitchen floor story, 261-262
<DD>Klerings, Peter, 350
<DD>Knuth, Donald, 323
<DD><BIG><B>L</B></BIG>
<DD><B>LAHF</B> instruction, 148
<DD>Large code model
<DL>
<DD>linking Zen timer, 71
<DD>optimizing assemblers, 71-72
</DL>
<DD>Latches
<DL>
<DD>and bit mask, 470
<DD>and Color Don&#146;t Care register, <B>535-537,</B> 535
<DD>and CPU reads, 530
<DD>drawing solid text, 1039-1041, <B>1042-1044</B>
<DD>Mode X
<DL>
<DD>copying pixels, <B>905-907,</B> 908, <B>909-911</B>
<DD>loading, with double copying process, 903
<DD>masked copying, 918-919, 919-921, <B>922-923</B>
<DD>pattern fills, 899, <B>900-903,</B> 903-904
</DL>
<DD>overview, 452-453, 897-898
</DL>
<DD>Latency, in QuakeWorld, 1291-1292
<DD><B>LEA</B> instruction
<DL>
<DD>vs. <B>ADD,</B> 130, 170-171
<DD>multiplication operations, 132-133, 172, 375-376
<DD>32-bit registers
<DL>
<DD>addition, 131
<DD>multiplication, 132-133
</DL>
</DL>
<DD><B>LEAVE</B> instruction
<DL>
<DD>486 processor, 241-242
<DD>Pentium processor, 377
<DD>286 processor, 221
</DL>
<DD>Level performance, 1213-1214
<DD>Life, Game of. <I>See</I> Game of Life.
<DD>Lighting
<DL>
<DD><I>See also</I> Shading.
<DD>Gouraud shading
<DL>
<DD>overview, 1246-1247
<DD>perspective correction, 1248-1250
<DD>problems with, 1247-1250
</DL>
<DD>intensity, calculating, 1137
<DD>overlapping lights, 1247
<DD>perspective correctness, 1248-1250
<DD>in Quake 3-D engine, 1282-1283
<DD>rotational variance, 1249
<DD>surface-based lighting
<DL>
<DD>description, 1250-1251
<DD>mipmapping, 1254-1255
<DD>performance, 1251-1253
<DD>surface caching, 1253-1256, 1260-1262
</DL>
<DD>two-pass approach, 1262
<DD>viewing variance, 1249
</DL>
<DD>Limits, transcending, in creative design, 1179-1180
<DD>Lindley, Bill, 854-855
<DD>LINE1 macro, <B>672-674</B>
<DD>LINE2 macro, <B>674-675</B>
<DD>Line Compare register, 565
<DD>Line segments
<DL>
<DD>clipping to planes, 1195-1197
<DD>representation, 1195, <B>1196</B>
</DL>
<DD>Linear addressing, VGA, 430
<DD>Linear-time sorting, 1099
<DD><B>LineDraw</B> function
<DL>
<DD>assembly implementation, <B>699-704,</B> 704-706
<DD>C-language implementation, <B>688-691</B>
</DL>
<DD>Line-drawing algorithms
<DL>
<DD>accumulated pixels approach (Jim Mackraz), 678
<DD>Bresenham&#146;s algorithms
<DL>
<DD>basic line-drawing algorithm, 655-661, <B>661-665,</B> 665-671, <B>671-677</B>
<DD>run-length slice algorithm, 683-693, <B>698-704,</B> 705
</DL>
<DD>characteristics of, 656-657
<DD>run-length slice algorithm, 683-693, <B>698-704,</B> 705
<DD>Wu antialiasing algorithm, 776-779, <B>780-791,</B> 791-792
</DL>
<DD>Line-drawing demo program, <B>615-618,</B> 618-619
<DD><B>LineIntersectPlane</B> function, <B>1142-1143</B>
<DD>Lines
<DL>
<DD>drawing
<DL>
<DD><I>See also</I> Line-drawing algorithms.
<DD>color-patterned lines demo program, <B>509-515</B>
<DD>320<I>See also</I> Restartable blocks.400 256-color mode, 600
<DD>write mode 2, 509
</DL>
<DD>intersecting, 1121-1123
<DD>parametric lines
<DL>
<DD>clipping, 1121-1123
<DD>overview, 1119-1120
</DL>
</DL>
<DD>Linked lists
<DL>
<DD>basic implementation, 283-285
<DD>circular lists, 288-292
<DD>dummy nodes, 285-287
<DD>head pointers, 284, 285
<DD><B>InsertNodeSorted</B> assembly routine, <B>290</B>
<DD>overview, 282
<DD>sentinels, 285-287
<DD>sorting techniques, 755
<DD>tail nodes, 286
<DD>test-bed program, <B>291</B>
</DL>
<DD>Little endian format, 252
<DD>Local optimization
<DL>
<DD><I>See also</I> Assembly language optimization; Optimization.
<DD>bit flipping and flags, 146-147
<DD>defined, 140
<DD>incrementing and decrementing, 147-148
<DD>lookup tables, 145-146
<DD>unrolling loops, 143-145, 305, 312, 377-378, 410
</DL>
<DD><B>LOCK</B> instruction, 377
<DD>Lockstep execution, Pentium processor, 390-394, 400-403
<DD><B>LODSB</B> instruction, 304, 312
<DD><B>LODSD</B> instruction, 171
<DD><B>LODSW</B> instruction, 312
<DD>Logical functions, ALU, 458
<DD>Logical height, virtual screen, 442
<DD>Logical width, virtual screen, 442
<DD>Long-period Zen timer
<DL>
<DD><I>See also</I> Zen timer.
<DD>calling from C code, 69-72
<DD>and interrupts, 53
<DD>LZTEST.ASM listing, <B>66-67</B>
<DD>LZTIME.BAT listing, <B>67-68</B>
<DD>LZTIMER.ASM listing, <B>55-65</B>
<DD>overview, 53
<DD><B>PS2</B> equate, 65-66
<DD>system clock inaccuracies, 43, 45-46, 48
<DD>test-bed program, 66-69
<DD>TESTCODE listing, <B>69</B>
<DD><B>ZTimerOff</B> subroutine, <B>59-63</B>
<DD><B>ZTimerOn</B> subroutine, <B>58-59</B>
<DD><B>ZTimerReport</B> subroutine, <B>63-65</B>
</DL>
<DD>Lookup tables
<DL>
<DD>CosSin subroutine, 994-996, 999
<DD>vs. rotating or shifting, 145-146
<DD>3-cell-per-word implementation, Game of Life, 365
<DD>word count program
<DL>
<DD>author&#146;s implementation, 303, 304
<DD>David Stafford&#146;s implementation, <B>309-311,</B> 317-319
<DD>WC50 (Terje Mathisen), 307
</DL>
</DL>
<DD><B>LOOP</B> instruction
<DL>
<DD><I>See also</I> Loops.
<DD>vs. <B>DEC/JNZ</B> sequence, 139, 140-141
<DD>and flags, 148
</DL>
<DD>Loops
<DL>
<DD><I>See also</I> <B>LOOP</B> instruction.
<DD>avoiding, 140
<DD>and branch prediction, Pentium processor, 377-378
<DD>unrolling, 143-145, 305, 312, 377-378, 410
<DD><BIG><B>M</B></BIG>
</DL>
<DD>Mackraz, Jim, 678
<DD>Map Mask register
<DL>
<DD>demo program, <B>472-473</B>
<DD>drawing text, 833
<DD>optimizing Mode X, 1074
<DD>vs. Read Map register, 526
<DD>selecting planes for CPU writes, 443-444, 471-472
<DD>with set/reset circuitry, 474
<DD>write mode 1, 443
</DL>
<DD>Map Mask register demo program, <B>472-473</B>
<DD>Mask register, blanking screen, 651
<DD>Masked copying, Mode X
<DL>
<DD>clipping, 923
<DD>between display memory locations, 918-919, <B>919-921</B>
<DD>image and mask alignments, generating, <B>922-923</B>
<DD>performance, 924
<DD>system memory to display memory, <B>916-918,</B> 916
</DL>
<DD>Masked images, 871-872
<DD>MASM (Microsoft Assembler), 187
<DD>Math, 3-D
<DL>
<DD>cross products, 1139-1140
<DD>dot products
<DL>
<DD>calculating, 1135-1137
<DD>calculating light intensity, 1137
<DD>projection, 1141-1142
<DD>rotation, 1143-1144
<DD>sign of, 1140-1141
<DD>of unit vectors, 1136
<DD>of vectors, 1135-1136
</DL>
<DD>matrix math
<DL>
<DD>assembly routines, 992, <B>996-999</B>
<DD>C-language implementations, <B>974-976</B>
<DD>normal vectors, calculating, 955-956
<DD>rotation of 3-D objects, 938-939, <B>943-944,</B> 948
<DD>transformation, optimized, 1172-1173, <B>1173-1174</B>
</DL>
<DD>vector length, 1135
</DL>
<DD>Mathiew, Serge, 855-857
<DD>Mathisen, Terje, 250-252, 306, 319
<DD>Matrices
<DL>
<DD>incremental transformations, 964
<DD>optimization of, 986, 1172-1173, <B>1173-1174</B>
<DD>3-D rotation, representation of, 938-939
</DL>
<DD>Matrix math
<DL>
<DD>assembly routines, 992, <B>996-999</B>
<DD>C-language implementations, <B>974-976</B>
<DD>normal vectors, calculating, 955-956
<DD>rotation of 3-D objects, 938-939, <B>943-944,</B> 948
<DD>transformation, optimized, 1172-1173, <B>1173-1174</B>
</DL>
<DD>MDA (Monochrome Display Adapter), 104
<DD><B>Memchr()</B> function, 116
<DD><B>Memcmp()</B> function, 116
<DD><B>Memcpy()</B> function, 1147-1148
<DD>Memory access
<DL>
<DD><I>See also</I> Display memory access.
<DD>clock cycles, bytes vs. words, 82, 83-85
<DD><B>DEC</B> instruction, 83
<DD>and DRAM refresh, 98
<DD>8-bit bus cycle-eater, 82
<DD>performance, 286 and 386 processors, 223-225
<DD>prefetch queue cycle-eater, 86
<DD>system wait states, 210-213
<DD>and wait states, 100
</DL>
<DD>Memory addressing, 221
<DD>Memory addressing modes, and arithmetic operations, 130-133
<DD>Memory allocation
<DL>
<DD>display memory, 903-904
<DD>page flipping, 834
</DL>
<DD>Memory locations, pushing and popping, 254-255
<DD>Memory variables
<DL>
<DD>data alignment, 213-215
<DD>8088 processor, optimization, 83-85
</DL>
<DD>Memory-addressing instructions, 223-225
<DD><B>Memset()</B> C library function, 727
<DD>Miles, John, 1081, 1093
<DD>Mipmapping, 1254-1255
<DD>Mode 12H (hi-res mode), 851-855
<DD>Mode 13H, 515, 590
<DD>Mode Control register, 575
<DD>Mode register
<DL>
<DD>color paging, 628-629
<DD>256-color modes, 629
</DL>
<DD>Mode X
<DL>
<DD><I>See also</I> X-Sharp 3-D animation package.
<DD>animation demo programs
<DL>
<DD>page-flipped animation, 924-925, <B>925-930</B>
<DD>3-D polygon rotation, 939, <B>940-945,</B> 948
</DL>
<DD>bitmap organization, 882-883
<DD>features, 878-879
<DD><B>FillRectangleX</B> subroutine
<DL>
<DD>four-plane parallel processing, 888-891, <B>891-893</B>
<DD>pixel-by-pixel plane selection, <B>885-887</B>
<DD>plane-by-plane processing, <B>887-889</B>
</DL>
<DD>four-plane parallel processing, 888-891, <B>891-893</B>
<DD>latches
<DL>
<DD>copying pixels, <B>905-907,</B> 908, <B>909-911</B>
<DD>loading, with double copying process, 903
<DD>overview, 897-898
<DD>pattern fills, 899, 900-903, 903-904
</DL>
<DD>masked copying
<DL>
<DD>animation demo program, 924-925, <B>925-930</B>
<DD>clipping, 923
<DD>between display memory locations, 918-919, <B>919-921</B>
<DD>image and mask alignments, generating, <B>922-923</B>
<DD>performance, 924
<DD>system memory to display memory, <B>916-918,</B> 916
</DL>
<DD>memory allocation, 903-904
<DD>mode set routine, <B>880-881,</B> 882
<DD>optimization, 1074
<DD>pattern fills, 899, <B>900-903,</B> 903-904
<DD>pixel access and hardware planes, 1082
<DD><B>ReadPixelX</B> subroutine, <B>884-885</B>
<DD>vertical scanlines vs. horizontal, 1084-1086
<DD><B>WritePixelX</B> subroutine, <B>883-884</B>
</DL>
<DD><B>ModelColor</B> structure, <B>1035</B>
<DD><B>ModelColorToColorIndex</B> function, 1036, <B>1038</B>
<DD>Mod-R/M byte, 257
<DD>Modular code
<DL>
<DD>and future of programming profession, 725-726
<DD>optimizing, 153
</DL>
<DD>Monotone-vertical polygons, filling, 760-761, <B>761-771,</B> 771
<DD><B>MOV</B> instruction, 236, 377, 832
<DD><B>MoveBouncer</B> function, <B>824-825</B>
<DD><B>MoveObject</B> function, <B>929</B>
<DD><B>MoveXSortedToAET</B> function
<DL>
<DD>complex polygons, <B>749</B>
<DD>monotone-vertical polygons, <B>770</B>
</DL>
<DD><B>MOVSD</B> instruction, 222, 386
<DD><B>MUL</B> instruction, 97, 173-174
<DD>Multiplication
<DL>
<DD>increasing speed of, 173-174
<DD>using <B>LEA,</B> 132-133, 172
</DL>
<DD>Multi-word arithmetic, 147-148
<DD><BIG><B>N</B></BIG>
<DD><B>NEG</B> EAX instruction, 222
<DD>Negation, two&#146;s complement, 171
<DD><B>Next1</B> function, <B>353</B>
<DD><B>Next2</B> function, <B>353</B>
<DD><B>Next_generation</B> method, <B>327-328,</B> <B>335,</B> 336, 337-338, <B>344</B>
<DD>Nonconvex objects, depth sorting, 1000, <B>1001-1002</B>
<DD>Normal vectors
<DL>
<DD>building BSP trees, 1106
<DD>calculating, 955-956
<DD>direction of, 1140
</DL>
<DD>Normals. <I>See</I> Normal vectors.
<DD><B>NOSMART</B> assembler directive, 72
<DD><B>NOT</B> instruction, 146-147, 147
<DD><BIG><B>O</B></BIG>
<DD>Object collisions, detecting, <B>531-534</B>
<DD>Object space, 935, 1135
<DD>Object-oriented programming, 725-726
<DD><B>Octant0</B> function
<DL>
<DD>360&#215;480 256-color mode line drawing demo program, <B>615</B>
<DD>Bresenham&#146;s line-drawing algorithm, <B>662,</B> 668-669
</DL>
<DD><B>Octant1</B> function
<DL>
<DD>360x480 256-color mode line drawing demo program, <B>616</B>
<DD>Bresenham&#146;s line-drawing algorithm, <B>663,</B> 668-669
</DL>
<DD>Octants, and line orientations, 666-667
<DD>1/z sorting
<DL>
<DD>abutting span sorting, 1229-1230
<DD><B>AddPolygonEdges</B> function, <B>1232-1233,</B> 1238
<DD>vs. BSP-order sorting, 1226-1227
<DD>calculating 1/z value, 1220-1222
<DD><B>ClearEdgeLists</B> function, <B>1236-1237</B>
<DD>DrawSpans function, 1236
<DD>independent span sorting, 1230, <B>1231-1238,</B> 1239-1241
<DD>intersecting span sorting, 1228-1229
<DD><B>PolyFacesViewer</B> function, <B>1232</B>
<DD>reliability, 1227
<DD><B>ScanEdges</B> function, <B>1234-1236,</B> 1238-1239
<DD><B>UpdateWorld</B> function, <B>1237-1238</B>
</DL>
<DD>On-screen object collisions, detecting, <B>531-534</B>
<DD>OpenGL API, GLQuake, 1288-1290
<DD>Operands, order of, 173-174
<DD><B>OPT2.ASM</B> listing, <B>313-315</B>
<DD>Optimization
<DL>
<DD><I>See also</I> Assembly language optimization; Local optimization.
<DD>32-bit registers, 187
<DD>and abstraction, 330-332, 345-346
<DD>and application parameters, 122
<DD>assemblers, optimizing, 71-72
<DD>avoiding thinking like a compiler, 152, 154-155
<DD>and biased perceptions, 1080, 1085
<DD>breakthrough level, 316
<DD>BSP trees, 1128-1129
<DD>buffer-filling routine, 416-420
<DD>C library functions, 15
<DD>compiler-based
<DL>
<DD>data recursion vs. code recursion, 1112-1113
<DD>on vs. off, 9
</DL>
<DD>data recursion, 1108-1113
<DD>data structures, 155-166
<DD>disk caches, 19
<DD>display adapter cycle-eater, 107
<DD>DRAM refresh, 98-99
<DD>8-bit bus cycle-eater, 83-85
<DD>fine-tuning existing code, 312-313
<DD>floating point operations
<DL>
<DD>clock cycles, core instructions, 1167-1168
<DD>cross product optimization, 1171, <B>1172</B>
<DD>dot product optimization, 1170, 1171
<DD><B>FXCH</B> instruction, 1169-1170
<DD>interleaved instructions, 1169-1170
<DD>matrix transformation optimization, 1172-1173, <B>1173-1174</B>
<DD>overview, 1167-1170
<DD>pipelining, 1168-1170
<DD>projection to screen space, 1174
<DD>rounding control, 1174-1175
</DL>
<DD>486 processor
<DL>
<DD>addressing pipeline penalty, 238-240, 243, 250-252
<DD>internal cache, 236
<DD>vs. Pentium processor, 378-379
<DD>pushing and popping, 254-255
<DD>reference materials, 236
<DD>shift and rotate instructions, 255-256
<DD>single cycle, importance of, 238
<DD>stack addressing, 241-242
</DL>
<DD>general rules, 223
<DD>generality, decreasing, 335
<DD>hardware efficiency, 1084-1086
<DD>knowing when to stop, 735
<DD>local optimization, 138-148
<DD>Mode X, 1074
<DD>modular code, 153
<DD>objectives and rules, 7-19, 156
<DD>pattern matching, 191-192, 202
<DD>Pentium processor
<DL>
<DD>and branch prediction, 378
<DD>code size and performance, 390
<DD>floating point operations, 1167-1175
<DD>interleaving operations, 394-395
<DD>pairing instructions, 390-394
<DD>pixel-drawing code, 1086
<DD>prefix bytes, 376, 395, 407
<DD>reference material, 374
<DD>superscalar execution, 384-396
<DD>vs. 386 and 486 processors, 378-379, 384
</DL>
<DD>perspective on problem, changing, 315-316, 1084
<DD>pixel drawing, 1074
<DD>pointer advancement optimization, 1086-1089, <B>1090-1091,</B> 1092-1093
<DD>prefetch queue cycle-eater, 93
<DD>problem definition, changing, 332
<DD>rearranging instructions, 418-419
<DD>reducing size of code, 416-418
<DD>redundant calculations, 682-683
<DD>re-examining problem, 338-339
<DD>register variables, 338
<DD>restartable blocks, 118
<DD>sorting techniques, 755
<DD>stack addressing, 420
<DD>sufficient, 312
<DD>superscalar execution
<DL>
<DD>initial pipe, effect of, 405
<DD>overview, 384-386
<DD>pairable instructions, 388
<DD>V-pipe-capable instructions, 386-387
</DL>
<DD>texture-mapping optimization
<DL>
<DD>inner-loop optimizations, <B>1069-1073,</B> 1074, 1081-1084
<DD>instruction-by-instruction optimizations, 1086-1092
<DD>pointer advancement optimization, 1086-1089, <B>1090-1091</B>
<DD>vertical scanlines, 1084-1086
</DL>
<DD>32-bit fixed-point arithmetic, 1086-1089, 1090-1091, 1092-1093
<DD>32-bit instructions, 1091
<DD>386 processor, 378-379
<DD>time vs. space tradeoff, 187
<DD>transformation inefficiencies, 25-26
<DD>transformation matrices, 986
<DD>understanding data, importance of, 122, 175, 180, 305
<DD>understanding how things work, 726
<DD>unifying model, developing, 1110-1111
<DD>unrolling loops, 143-145, 410
<DD>using restartable blocks, 118
<DD>and VGA memory speed, 704-705
</DL>
<DD>Optimized searching, 174-180
<DD>Optimizing assemblers, 71-72
<DD><B>OR</B> instruction, 377
<DD>Orientation-independent texture mapping, 1065-1066, <B>1067</B>
<DD><B>OUT</B> instruction
<DL>
<DD>clock cycles, 1082-1083
<DD>loading DAC, 640, 642-643
<DD>loading palette RAM or DAC registers, 632
<DD>performance, 444, 843
<DD>word-<B>OUT</B> vs. byte-<B>OUT,</B> 429, 479
<DD>vs. write mode 3, 483-484
</DL>
<DD><B>OUTS</B> instruction, 221
<DD>OUT_WORD macro, <B>566,</B> 594
<DD>Overdraw problem, VSD
<DL>
<DD>and beam trees, 1185-1186
<DD>painter&#146;s algorithm, 1184-1185
<DD>sorted spans, 1215
</DL>
<DD>Overflow register, split screen operation, 565
<DD>Overhead
<DL>
<DD>DOS function calls
<DL>
<DD>in 16-bit checksum program, 12
<DD>in search engine, 121
</DL>
<DD><B>memcmp()</B> function, 116
<DD><B>strstr()</B> function, 115
<DD>of Zen timer, timing, 46, 72
</DL>
<DD>Overlapping rectangles, in dirty-rectangle animation, 872-873
<DD>Overscan, 555-556, 641
<DD><BIG><B>P</B></BIG>
<DD>Page flipping
<DL>
<DD>and bit-plane animation, 814
<DD>color cycling, 650
<DD>vs. dirty-rectangle animation, 846, 862
<DD>display memory start address, changing, 857
<DD>mechanics of, 833-836
<DD>memory allocation, 834, 903-904
<DD>overview, 444-446
<DD>single-page technique, 855-857
<DD>640&#215;480 mode, 836-837
<DD>with split screen, 836-837
<DD>320&#215;400 256-color mode, <B>600-605</B>
<DD>timing updates, 835-836
<DD>VGA mode 12H (hi-res mode), 851-855
</DL>
<DD>Page flipping animation demo programs
<DL>
<DD>Mode X, 924-925, <B>925-930</B>
<DD>split screen and page flipping, <B>820-825,</B> <B>825-830,</B> 836-837
<DD>320&#215;400 256-color mode, <B>600-605</B>
</DL>
<DD>Painter&#146;s algorithm
<DL>
<DD><I>See also</I> 3-D animation; 3-D drawing.
<DD>and BSP trees, 1099, 1104-1105
<DD>overdraw problem, 1184-1185
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
<DD>Pairable instructions, Pentium processor, 388
<DD>Palette adjustment, dynamic, 1039
<DD>Palette RAM
<DL>
<DD><I>See also</I> Palette registers.
<DD>color paging, 628-629
<DD>setting registers, 629-630, 631-632
<DD>VGA color path, 626
</DL>
<DD>Palette registers
<DL>
<DD><I>See also</I> Palette RAM.
<DD>EGA, 549-550
<DD>setting for bit-plane animation, 799-801, 811-813
</DL>
<DD>Panning
<DL>
<DD>byte-by-byte vs. pixel-by-pixel, 574
<DD>overview, 441-442
<DD>in split screens, 574-575, <B>575-582,</B> 582-583
<DD>in text mode, 442
</DL>
<DD><B>PanRight</B> subroutine, <B>582</B>
<DD>Parametric lines
<DL>
<DD>clipping, 1121-1123
<DD>overview, 1119-1120
</DL>
<DD>Particles, Quake 3-D engine, 1287
<DD>Pattern fills, 899, 900-903, 903-904
<DD>Pattern matching, 191-192, 202
<DD>PC compatibility, Zen timer, 48-49
<DD>Pel panning. <I>See</I> Panning.
<DD>Pel Panning register, 574, 583
<DD>Pentium processor
<DL>
<DD>AGIs (Address Generation Interlocks), 400-403
<DD>alignment, 376
<DD>branch instructions, pairing, 404-405
<DD>branch prediction, 377-378
<DD>bus, locking, 377
<DD>cache lines, 374
<DD>code size and performance, 390
<DD>data cache and paired instructions, 391
<DD>display adapter cycle-eater, 107
<DD>EA (effective address) calculations, 375-376
<DD>floating point optimization
<DL>
<DD>clock cycles, core instructions, 1167-1168
<DD>cross product optimization, 1171, <B>1172</B>
<DD>dot product optimization, 1170, <B>1171</B>
<DD><B>FXCH</B> instruction, 1169-1170
<DD>interleaved instructions, 1169-1170
<DD>matrix transformation optimization, 1172-1173, <B>1173-1174</B>
<DD>overview, 1167-1170
<DD>pipelining, 1168-1170
<DD>projection to screen space, 1174
<DD>rounding control, 1174-1175
</DL>
<DD>FPU pipelining, 1168-1170
<DD>instruction fetching, 374
<DD>internal cache, 374-375, 396
<DD><B>LAHF</B> and <B>SAHF</B> instructions, 148
<DD><B>LEA</B> vs. <B>ADD</B> instructions, 131
<DD><B>LODSB</B> instruction, 304
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD><B>MOV</B> vs. <B>XCHG</B> instructions, 377
<DD>optimization
<DL>
<DD>pairing instructions, 390-394
<DD>pixel-drawing code, 1086
<DD>reference material, 374
</DL>
<DD>overview, 373-375
<DD>pipeline stalls
<DL>
<DD>FPU, 1168-1170
<DD>overview, 375
<DD>texture-mapping code, 1092
</DL>
<DD>prefix bytes, 376, 395, 407
<DD>running Pentium code on 386 or 486, 411
<DD>superscalar execution
<DL>
<DD>initial pipe, effect of, 405
<DD>interleaving operations, 394-395
<DD>internal cache, 396
<DD>lockstep execution, 390-394, 400-403
<DD>overview, 384-386
<DD>pairable instructions, 388
<DD>prefix bytes, 395
<DD>register contention, 403-405
<DD>registers, small set, 395
</DL>
<DD>U-pipe, 385-386
<DD>V-pipe, 385-386, 386-387
<DD><B>XCHG</B> vs. <B>MOV</B> instructions, 377, 832
</DL>
<DD><I>Pentium Processor Optimization Tools</I> (book), 1148
<DD>Performance
<DL>
<DD><I>See also</I> Assembly language optimization; Clock cycles; Cycle-eaters; Local optimization; Optimization; Zen timer.
<DD>and abstraction, 330-332, 345-346
<DD>beam trees, 1186
<DD>Boyer-Moore algorithm, 266-268
<DD>branching, 140
<DD>BSP (Binary Space Partitioning) trees, 1100, 1111-1113
<DD>bubble sort, 755
<DD>complex polygons, filling, 753
<DD>dirty-rectangle animation, 873
<DD>display adapter cycle-eater, 221
<DD>DRAM refresh, 97
<DD>function calls, 153
<DD>Game of Life
<DL>
<DD>byte-per-cell implementation, 340
<DD>cellmap-wrapped implementation, 332, 338
<DD>challenge results, 351
<DD>general analysis, 329-330
</DL>
<DD>and generality, 335
<DD>level performance, 1213-1214
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD>masked copying, Mode X, 924
<DD>measuring, importance of, 34, 396
<DD>memory access, 223-225
<DD><B>OUT</B> instruction, 444
<DD><B>OUT</B> instructions, 843
<DD>PC-compatible computers, 48-49
<DD>polygon-filling implementations, 728
<DD>precalculated potentially visible set (PVS), 1213-1214
<DD>profiling and 80x87 emulator, Borland C++, 999
<DD>stack frames, 153
<DD>SuperVGA, with 486 processor, 842-844
<DD>texture mapping, 1074-1074
<DD>3-D polygon rotation demo programs, 949
<DD>360x480 256-color mode, 618
<DD>320x400 256-color mode, 599-600
<DD>time-critical code, 13
<DD>vertical scanlines in texture mapping, 1084
<DD>video performance, 104
<DD>Wu antialiasing algorithm, 777-778
<DD>z-buffers, 1213
</DL>
<DD>Perspective correction in texture mapping, 1093
<DD>Perspective correctness problem, Gouraud shading, 1248-1250
<DD>Perspective projection, 937, 1135
<DL>
<DD><I>See also</I> Projection.
</DL>
<DD>Pipeline stalls, Pentium processor, 375
<DL>
<DD><I>See also</I> Addressing pipeline penalty; AGIs (Address Generation Interlocks).
</DL>
<DD>Pipelining
<DL>
<DD>486 processor
<DL>
<DD>addressing pipeline penalty, 238-240, 250
<DD>stack addressing, 241-242
</DL>
<DD>FPU, Pentium processor, 1168-1170
</DL>
<DD>Pitch angle, in polygon clipping, 1206
<DD>Pixel bits, rotating, 252
<DD>Pixel drawing
<DL>
<DD><I>See also</I> Pixels.
<DD><B>EVGADot</B> function, <B>661-662,</B> 669-670
<DD>optimization, 1074, 1086
<DD>painter&#146;s algorithm and overdraw problem, 1184
</DL>
<DD>Pixel intensity calculations, Wu&#146;s antialiasing algorithm, 778-779
<DD>Pixel values, mapping to colors, 548-551, <B>551-555</B>
<DD>Pixels
<DL>
<DD><I>See also</I> Boundary pixels, polygons; Pixel drawing.
<DD>copying, using latches (Mode X), <B>905-907,</B> 908, <B>909-911</B>
<DD>reading (320&#215;400 256-color mode), 599
<DD>redrawing, display adapter cycle-eater, 102
<DD>rotating bits, 252
<DD>writing (320&#215;400 256-color mode), 599, 600
</DL>
<DD>Plane mask, 1074
<DD>Plane-manipulation demo program, <B>476-478</B>
<DD>Planes
<DL>
<DD>clipping line segments to, 1195-1197
<DD>1/z value, calculating, 1221
<DD>representation, <B>1196</B>
</DL>
<DD>Planes, VGA
<DL>
<DD><I>See also</I> Bit-plane animation.
<DD>ALUs and latches, 451-453
<DD>and bit mask, 465
<DD>capturing and restoring screens, 541-542, <B>543-547,</B> 547-548
<DD>and Color Don&#146;t Care register, 534-535, <B>535-537</B>
<DD>fonts, in text modes, 516
<DD>manipulating, 443-444, 476-478
<DD>and Map Mask register, 471-472
<DD>Mode X
<DL>
<DD>bitmap organization, 882-883
<DD>four-plane parallel processing, 888-891, <B>891-893</B>
<DD>pixel-by-pixel plane selection, <B>885-887</B>
<DD>plane-by-plane processing, <B>887-889</B>
</DL>
<DD>Mode X pixel access, 1082
<DD>overview, 430
<DD>and Read Map register, 542
<DD>read mode 0, 525-526
<DD>and set/reset circuitry, 471-478
<DD>setting all to single color, 473-474
<DD>single-color drawing with write mode 3, 831-832
<DD>write mode 2, 502-504, 509
</DL>
<DD>Pohl, Frederick, 1275
<DD>Pointer advancement optimization, 1086-1089, <B>1090-1091,</B> 1092-1093
<DD>Pointer arithmetic, 171
<DD>Points, representation of, <B>1196</B>
<DD><B>PolyFacesViewer</B> function, <B>1203,</B> 1232
<DD>Polygon clipping
<DL>
<DD><B>BackRotateVector</B> function, <B>1203</B>
<DD>clipping to frustum, 1200, <B>1201-1206,</B> 1206-1207
<DD><B>ClipToFrustum</B> function, <B>1204</B>
<DD><B>ClipToPlane</B> function, <B>1199</B>
<DD>optimization, 1207
<DD>overview, 1197-1200
<DD><B>PolyFacesViewer</B> function, <B>1203</B>
<DD><B>ProjectPolygon</B> function, <B>1201</B>
<DD><B>SetUpFrustum</B> function, <B>1204</B>
<DD><B>SetWorldspace</B> function, <B>1204</B>
<DD><B>TransformPoint</B> function, <B>1203</B>
<DD><B>TransformPolygon</B> function, <B>1203</B>
<DD><B>UpdateViewPos</B> function, <B>1202</B>
<DD><B>UpdateWorld</B> function, <B>1205</B>
<DD>viewspace clipping, 1207
<DD><B>ZSortObjects</B> function, <B>1201</B>
</DL>
<DD>POLYGON.H header file
<DL>
<DD>complex polygons, <B>751</B>
<DD>monotone-vertical polygons, filling, <B>771</B>
<DD>non-overlapping convex polygons, <B>719-720</B>
<DD>texture mapped polygons, <B>1054</B>
<DD>3-D polygon rotation, <B>945-946</B>
<DD>3-D solid cube rotation program, <B>965</B>
<DD>X-Sharp 3-D animation package, <B>982-984</B>
</DL>
<DD>Polygon models, Quake 3-D engine, 1285-1286
<DD>Polygon-filling programs
<DL>
<DD><I>See also</I> Polygons, filling.
<DD>complex polygons, 742-744, <B>745-752,</B> 753, <B>754,</B> 755-756
<DD>monotone-vertical polygons, 760, <B>761-771</B>
<DD>non-overlapping convex polygons
<DL>
<DD>assembly implementations, 732-733, <B>733-734,</B> <B>735-739</B>
<DD>C-language implementations, <B>713-720,</B> 720-721, <B>729-732</B>
</DL>
</DL>
<DD>PolygonIsMonotoneVertical function, 761
<DD>Polygons
<DL>
<DD><I>See also</I> Texture mapping.
<DD>adjacent, and 1/z span sorting, 1230
<DD>backface removal, 954-957, 1160-1161
<DD>categories of, 710, 742, 759-760
<DD>clipping, 1158-1159
<DD>Gouraud shading, 1247
<DD>hidden surface removal, 1214-1222
<DD>normal vector, calculating, 955-956
<DD>projection in 3-D space, 937, <B>944-945,</B> 948
<DD>representation, <B>1196</B>
<DD>3-D polygon rotation demo program
<DL>
<DD>matrix multiplication functions, <B>943-944,</B> 948
<DD>overview, 939
<DD>performance, 949
<DD>polygon filling with clipping support, <B>940-943</B>
<DD>transformation and projection, <B>944-945,</B> 948
</DL>
<DD>transformation to 3-D space, 935
<DD>unit normal, calculating, 1027-1028, 1137-1140
<DD>visibility, calculating, 955-956
<DD>visible surface determination (VSD)
<DL>
<DD>beam trees, 1185-1189
<DD>overdraw problem, 1184-1185
<DD>polygon culling, 1181-1184
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
<DD>visible surface determination (VSD)culling to frustum, 1181-1184
<DD>wall orientation testing, BSP tree rendering, 1160-1161
</DL>
<DD>Polygons, filling
<DL>
<DD><I>See also</I> Polygon-filling programs; Polygons; Texture mapping.
<DD>active edges, 742-744, 753, 755, 756
<DD>boundary pixels, selecting, 712
<DD>with clipping support, 940-943
<DD>complex polygons, 742
<DD>drawing, speeding up, 727-729
<DD>edge tracing
<DL>
<DD>overview, 711-713
<DD><B>ScanEdge</B> function, <B>716-717,</B> 720-721, <B>730-732,</B> <B>735-738</B>
</DL>
<DD>fitting adjacent polygons, 712-713
<DD>flat vs. pointed top, 720
<DD>integer vs. fixed-point arithmetic, 1065
<DD>in Mode X, <B>940-943</B>
<DD>monotone-vertical polygons, 760-761, 771
<DD>nonconvex polygons, 755
<DD>non-overlapping convex polygons, 720-721
<DD>performance, comparison of implementations, 728
<DD>rasterization, 710-712
<DD>scan conversion, 710, 720-721
<DL>
<DD>active edges, 721, 742-744, 753, 755, 756
<DD>C-language implementation, <B>713-717,</B> 720-721
<DD>defined, 710
<DD>zero-length segments, 721
</DL>
</DL>
<DD>Polyhedrons
<DL>
<DD>hidden surfaces, 955, 1000, <B>1001-1002</B>
<DD>representation of, 962
<DD>3-D solid cube rotation demo program
<DL>
<DD>basic implementation, <B>957-961,</B> 962-963
<DD>incremental transformations, <B>964-966</B>
<DD>object representation, 967
</DL>
</DL>
<DD><B>POP</B> instruction, 241-242, 404
<DD><B>POPA</B> instruction, 221
<DD><B>POPF</B> instruction, 226, 226-231
<DD>Popping, memory locations vs. registers, 254-255
<DD>Portable code, and future of programming profession, 725-726
<DD>Portals
<DL>
<DD>and beam trees, 1188
<DD>in Quake 3-D engine, 1279-1280
</DL>
<DD>Potentially visible set (PVS)
<DL>
<DD>vs. portals, 1279-1280
<DD>precalculating, 1188-1189, 1213-1214
<DD>Quake 3-D engine, 1278-1279
</DL>
<DD>Precalculated results
<DL>
<DD>BSP trees and potentially visible set (PVS), 1188-1189
<DD>lookup tables, 146
</DL>
<DD>Precision
<DL>
<DD>long-period Zen timer, 53
<DD>rounding vs. truncation, 1002-1003
<DD>Zen timer, 48, 52
</DL>
<DD>Prefetch queue
<DL>
<DD>286 and 386 processors, 225
</DL>
<DD>Prefetch queue cycle-eater
<DL>
<DD>286 and 386 processors, 210
<DD>instruction execution times, 87-93
<DD>optimizing for, 93
<DD>overview, 86
<DD>system wait states, 210
<DD>and Zen timer, 88, 92
</DL>
<DD>Prefix bytes
<DL>
<DD>Pentium processor, 376, 395, 407
<DD>and stack-based variables, 184
</DL>
<DD>Prefixes. <I>See</I> Prefix bytes.
<DD><I>Principles of Interactive Computer Graphics</I> (book), 934
<DD>Problems, quick responses to, 1166
<DD>Profiling, and 80&#215;87 emulator, Borland C++, 999
<DD>Program size vs. clock cycles, 28
<DD><I>Programmer&#146;s Guide to PC Video Systems</I> (book), 651
<DD>Projection
<DL>
<DD>defined, 1135
<DD>floating point optimization, 1174
<DD><B>LineIntersectPlane</B> function, <B>1142-1143</B>
<DD>overview, 937, 948
<DL>
<DD><B>XformAndProjectPoly</B> function, <B>944-945</B>
</DL>
<DD>rotation without matrices, 1143-1144
<DD>using dot product, 1141-1142
</DL>
<DD><B>ProjectPolygon</B> function, <B>1201</B>
<DD>Proportional text, 489
<DD>Protected mode
<DL>
<DD>addressable memory, 221
<DD>486 processor
<DL>
<DD>addressing calculation pipeline, 239
<DD>indexed addressing, 237-238
</DL>
<DD>general tips, 140
<DD>overview, 208-209
<DD>32-bit addressing modes, 256-258
</DL>
<DD><B>PS2</B> equate, long-period Zen timer, 65-66
<DD>PS/2 computers, 54, 66
<DD><B>PUSH</B> instruction, 222, 241-242, 404
<DD><B>PUSHA</B> instruction, 221
<DD>Pushing, memory locations vs. registers, 254-255
<DD>PZTEST.ASM listing, Zen timer, <B>49</B>
<DD>PZTIME.BAT listing, Zen timer, <B>51</B>
<DD>PZTIMER.ASM listing, Zen timer, <B>35-42</B>
<DD><BIG><B>Q</B></BIG>
<DD>QLife program, <B>352-363</B>
<DD><B>QSCAN3.ASM</B> listing, <B>309-311</B>
<DD>Quake 2, 1293
<DD>Quake
<DL>
<DD>surface caching, 1253-1256, 1260-1262
<DD>surface-based lighting
<DL>
<DD>description, 1250-1251
<DD>mipmapping, 1254-1255
<DD>performance, 1251-1253
<DD>surface caching, 1253-1256, 1260-1262
<DD>texture mapping, 1261-1262
</DL>
<DD>3-D engine
<DL>
<DD>BSP trees, 1276-1277
<DD>lighting, 1282-1283
<DD>model overview, 1276-1277
<DD>portals, 1279-1280
<DD>potentially visible set (PVS), 1278-1279
<DD>rasterization, 1282
<DD>world, drawing, 1280-1281
</DL>
<DD>and visible surface determination (VSD), 1181
</DL>
<DD>QuakeWorld, 1291-1292
<DD><BIG><B>R</B></BIG>
<DD>Radiosity lighting, Quake 2, 1293
<DD>Rasterization of polygons
<DL>
<DD><I>See also</I> Polygons, filling.
<DD>boundary pixels, selecting, 712
<DD>efficient implementation, 711
<DD>in Quake 3-D engine, 1282
</DL>
<DD>Rate of divergence, in 3-D drawing, 937
<DD>Raycast, subdividing, and beam trees, 1187
<DD><B>RCL</B> instruction, 185-186
<DD><B>RCR</B> instruction, 185-186
<DD><B>Read360&#215;480Dot</B> subroutine, <B>614-615</B>
<DD><B>Read()</B> C library function
<DL>
<DD>vs. <B>getc()</B> function, 12
<DD>overhead, 121
</DL>
<DD>Read Index register, 651-652
<DD>Read Map register
<DL>
<DD>demo program, <B>526-530</B>
<DD>planes, specifying to be read, 542
<DD>read mode, 0, 526
</DL>
<DD>Read Map register demo program, <B>526-530</B>
<DD>Read mode, 0, 521
<DD>Read mode 1
<DL>
<DD>Color Don&#146;t Care register, 534
<DD>overview, 525-526
<DD>vs. read mode 0, 521
<DD>selecting, 525
</DL>
<DD>Read/write/modify operations, 107
<DD>Read-after-write register contention, 404
<DD><B>ReadPixel</B> subroutine, <B>598</B>, 599
<DD><B>ReadPixelX</B> subroutine, <B>884-885</B>
<DD>Real mode. <I>See</I> 386 processor.
<DD>Real mode
<DL>
<DD>addressing calculation pipeline, 239
<DD>32-bit addressing modes, 256-258
</DL>
<DD>Rectangle fill, Mode X
<DL>
<DD>four-plane parallel processing, 888-891, <B>891-893</B>
<DD>pixel-by-pixel plane selection, <B>885-887</B>
<DD>plane-by-plane processing, <B>887-889</B>
</DL>
<DD>Recursion
<DL>
<DD>BSP trees
<DL>
<DD>building BSP trees, 1101-1104
<DD>data recursive inorder traversal, 1107-1113
<DD>visibility ordering, 1104-1106
</DL>
<DD>code recursion
<DL>
<DD>vs. data recursion, 1108-1110
<DD>Euclid&#146;s algorithm, 198-199
</DL>
<DD>compiler-based optimization, 1112-1113
<DD>data recursion
<DL>
<DD>vs. code recursion, 1108-1110
<DD>compiler-based optimization, 1112-1113
<DD>Euclid&#146;s algorithm, 200
<DD>inorder tree traversal, 1108-1110
<DD>performance, 1111-1113
</DL>
<DD>performance, 1111-1113
</DL>
<DD>Reference materials
<DL>
<DD>3-D drawing, 934-935
<DD>3-D math, 1135
<DD>bitmapped text, drawing, 471
<DD>Bresenham&#146;s line-drawing algorithm, 660
<DD>BSP trees, 1114, 1157
<DD>circle drawing, 626
<DD>color perception, 625
<DD>8253 timer chip, 72
<DD>486 processor, 236
<DD>parametric line clipping, 1121
<DD>Pentium processor, 374, 1148
<DD>SVGA programming, 626
<DD>VGA registers, 583
</DL>
<DD><B>ReferenceZTimerOff</B> subroutine, 41
<DD><B>ReferenceZTimerOn</B> subroutine, 40
<DD>Reflections, in GLQuake, 1290
<DD>Reflective color, vs. emissive color, 1035
<DD>Register contention, Pentium processor, 403-405
<DD>Register-only instructions, 223-225
<DD>Registers
<DL>
<DD><I>See also</I> 32-bit registers; VGA registers.
<DD>AX register, 171
<DD>copying bytes between, 172
<DD>EGA palette registers, 549-550
<DD>8-bit bus cycle-eater, 85
<DD>486 processor
<DL>
<DD>addressing pipeline penalty, 238-240, 250
<DD>byte registers and lost cycles, 242-245
<DD>indexed addressing, 237-238
<DD>pushing or popping, vs. memory locations, 254-255
<DD>scaled, 256-258
<DD>stack addressing, 241-242
<DD>32-bit addressing modes, 256-258
</DL>
<DD>prefetch queue cycle-eater, 94
<DD>and split screen operations, 573
<DD>and stack frames, 153
<DD>VGA architecture, 427-429
</DL>
<DD>Relocating bitmaps, 516-517
<DD>Rendering BSP trees
<DL>
<DD>backface removal, 1160-1161
<DD>clipping, 1158-1159
<DD><B>ClipWalls</B> function, <B>1152-1155</B>, 1158-1159
<DD><B>DrawWallsBackToFront</B> function, <B>1155-1156</B>, 1160-1161
<DD>overview, 1149
<DD>reference materials, 1157
<DD><B>TransformVertices</B> function, <B>1151-1152</B>, 1158
<DD><B>UpdateViewPos</B> function, <B>1151</B>, 1157
<DD><B>UpdateWorld</B> function, <B>1156-1157</B>, 1157
<DD>viewspace, transformation of objects to, 1158
<DD>wall orientation testing, 1160-1161
<DD><B>WallFacingViewer</B> function, <B>1150-1151</B>, 1161
</DL>
<DD><I>RenderMan Companion</I> (book), 742
<DD><B>REP MOVS</B> instruction, 148
<DD><B>REP MOVSW</B> instruction, 82, 105, 220
<DD><B>REP SCASW</B> instruction, 166
<DD><B>REP STOS</B> instruction, 727, 735
<DD><B>REPNZ SCASB</B> instruction
<DL>
<DD>vs. Boyer-Moore algorithm, 267-268, 271, 274
<DD>in string searching problem, 121-122, 174-175, 262-263
</DL>
<DD><B>REPZ CMPS</B> instruction
<DL>
<DD>vs. Boyer-Moore algorithm, 267-268, 271, 274
<DD>in string searching problem, 121-122, 174-175, 262-263
</DL>
<DD>Restartable blocks
<DL>
<DD>in 16-bit checksum program, 16
<DD>optimizing file processing, 118
<DD>performance, 122
<DD>in search engine, 117-118
<DD>size of, 114, 121
</DL>
<DD>Results, precalculating
<DL>
<DD><I>See also</I> lookup tables.
<DD>BSP trees and potentially visible set (PVS), 1188-1189
</DL>
<DD><B>RET</B> instruction, 241-242
<DD>Reusable code, and future of programming profession, 725-726
<DD>RGB (red, green, blue) color model
<DL>
<DD>mapping to 256-color mode, 1036, <B>1037-1038</B>, 1039
<DD>overview, 1034-1035
</DL>
<DD>Richardson, John, 316
<DD>Right-handed coordinate system, 935-937
<DD><B>ROL</B> instruction, 185-186
<DD>Roll angle, in polygon clipping, 1206
<DD><B>ROR</B> instruction, 185-186
<DD>Rotate instructions
<DL>
<DD>hand assembling, 255-256
<DD>n-bit vs. 1-bit, 255-256
<DD>286 processor, 222
</DL>
<DD><B>RotateAndMovePObject</B> function, 977-978
<DD>Rotation, 3-D animation
<DL>
<DD><B>ConcatXforms</B> function, 944
<DD>matrix representation, 938-939
<DD>multiple axes of rotation, 948
<DD>using dot product, 1143-1144
<DD><B>XformVec</B> function, 943
</DL>
<DD>Rotational variance, 1249
<DD>Rotations, bitwise
<DL>
<DD>vs. lookup tables, 145-146
<DD>multi-bit vs. single-bit, 185-186
</DL>
<DD>Rounding vs. truncation
<DL>
<DD>in 3-D animation, 1002-1003
<DD>floating point optimization, 1174-1175
<DD>texture mapping, 1066-1067
</DL>
<DD>Run-length slice algorithm
<DL>
<DD>assembly implementation, <B>698-704</B>
<DD>C-language implementations, <B>688-692</B>, <B>692-693</B>
<DD>description, 683-684
<DD>implementation details, 685-687
<DD>integer-based implementation, 685-687
<DD>potential optimizations, 705
</DL>
<DD>Ruts, mental, staying out of, 1147-1148
<DD><BIG><B>S</B></BIG>
<DD><B>SAHF</B> instruction, 148
<DD>Sam the Golden Retriever, 841-842
<DD>SC (Sequence Controller), VGA
<DL>
<DD>addressing, 427-428
<DD>Map Mask register
<DL>
<DD>CPU writes, selecting planes, 443-444, 471-472
<DD>drawing text, 833
<DD>optimizing Mode X, 1074
<DD>vs. Read Map register, 526
<DD>with set/reset circuitry, 474
<DD>write mode 1, 444
</DL>
</DL>
<DD>Scaled registers, 256-258
<DD>Scan conversion, polygons
<DL>
<DD>active edges, 721, 742-744, 753, 755, 756
<DD>C-language implementation, <B>713-717</B>, 720-721
<DD>defined, 710
<DD>zero-length segments, 721
</DL>
<DD>Scan lines
<DL>
<DD>redefining length of, 442
<DD>in split screens, 564-565, 573
<DD>360&#215;480 256-color mode, 619
<DD>vertical, in texture mapping, 1084-1086
</DL>
<DD><B>ScanBuffer</B> assembly routine
<DL>
<DD>author&#146;s implementation, <B>301-302</B>, <B>303-304</B>
<DD>hand-optimized implementation(Willem Clements), <B>313-315</B>
<DD>lookup table implementation (David Stafford), <B>309-311</B>, 317-319
</DL>
<DD><B>ScanEdge</B> function
<DL>
<DD>assembly implementation, <B>735-738</B>, 735
<DD>floating-point C implementation, <B>716-717</B>, 720-721
<DD>integer-based C implementation, <B>730-732</B>
</DL>
<DD><B>ScanEdges</B> function, <B>1234-1236</B>, 1238-1239
<DD><B>ScanOutAET</B> function
<DL>
<DD>complex polygons, <B>749-750</B>
<DD>monotone-vertical polygons, <B>770</B>
</DL>
<DD><B>ScanOutLine</B> function
<DL>
<DD>assembly implementation, <B>1069-1073</B>, 1074
<DD>C-language implementation, <B>1058-1059</B>, <B>1067-1069</B>
</DL>
<DD><B>SCASW</B> instruction, 161
<DD>Screen blanking
<DL>
<DD>demo program, <B>556-557</B>
<DD>using DAC Mask register, 651
</DL>
<DD>Screen blanking demo program, <B>556-557</B>
<DD>Screen capture programs, 541-548
<DD>Screen redraws, and display adapter cycle-eater, 101, 102
<DD>Screen refresh rate, 619
<DD>Screenspace
<DL>
<DD>defined, 1135
<DD>and normals of polygons, 1137-1138
<DD>projecting to, BSP tree rendering, 1159
<DD>uses for, 967
</DL>
<DD>SEARCH.C listing, <B>118-121</B>
<DD>Search engine
<DL>
<DD><I>See also</I> Searching.
<DD>Boyer-Moore algorithm, 263-277
<DD>design considerations, 114
<DD>execution profile, 121
<DD><B>FindString</B> function, 175, <B>176</B>, <B>178</B>, <B>269</B>
<DD>optimization, 174-180
<DD>restartable blocks, 117-118
<DD>search space and optimization, 122, 175
<DD>search techniques, 115-116, 175
</DL>
<DD><B>SearchForString</B> function, <B>118</B>
<DD>Searching
<DL>
<DD><I>See also</I> Search engine.
<DD>Boyer-Moore algorithm, 263-277
<DD>in linked list of arrays, 156-166
<DD>for specified byte in buffer, 141-145
<DD>using <B>REP SCASW</B>, 166
</DL>
<DD><B>SecondPass</B> function, <B>358-360</B>
<DD>Sedgewick, Robert (<I>Algorithms</I>), 192, 196
<DD>Segments
<DL>
<DD>compiler handling of, 154
<DD>and far jumps, 186
<DD>protected mode, 208-209
<DD>386 processor, 222
</DL>
<DD><B>SelectBSPTree</B> function, <B>1124-1125</B>
<DD>Selling ideas, 1193-1194
<DD>Sentinels, in linked lists, 286
<DD>Sequence Controller, VGA. <I>See</I> SC (Sequence Controller), VGA.
<DD><B>Set320&#215;400Mode</B> subroutine, 593, <B>596-597</B>, 599, <B>602-604</B>
<DD><B>Set320&#215;240Mode</B> subroutine, <B>881-882</B>
<DD><B>Set360&#215;480Mode</B> subroutine, <B>612</B>, 620-621
<DD><B>Set640x400</B> function, <B>855</B>
<DD>Set/reset circuitry, VGA
<DL>
<DD>color-forcing demo program, 474-476
<DD>and CPU data, 474
<DD>emulating write mode 3, 490
<DD>overview, 471-472, 478-479
<DD>plane-manipulation demo program, <B>476-478</B>
<DD>planes, setting all to single color, 473-474
<DD>and write mode 2, 501-502, 509, 515
</DL>
<DD>Set/Reset register, 666
<DD><B>SetBIOS8&#215;8Font</B> subroutine, <B>830</B>
<DD><B>Set_cell</B> method, <B>327</B>, <B>334</B>, <B>342</B>
<DD>SETGC macro, 454, 475
<DD><B>SetPalette</B> function, <B>783-784</B>
<DD><B>SetPelPan</B> subroutine, <B>580</B>
<DD>SETSC macro, 474
<DD><B>SetSplitScreenScanLine</B> subroutine, <B>570-571</B>, <B>581</B>
<DD><B>SetStartAddress</B> subroutine, <B>570</B>, <B>580</B>
<DD><B>SetUpEdge</B> function, <B>1057-1058</B>
<DD><B>SetWorldspace</B> function, <B>1204</B>
<DD>Shading
<DL>
<DD><I>See also</I> Lighting; 3-D drawing.
<DD>ambient shading, 1023
<DD>diffuse shading, 1023-1024
<DD>directed light sources, 1028
<DD>effects, 360x480 256-color mode, 618
<DD>overall shading, calculating, 1025
<DD>of polygons, <B>1025-1026</B>, 1027-1029
</DL>
<DD>Shearing
<DL>
<DD>cause of, 813
<DD>in dirty-rectangle animation, 846
<DD>page flipping, 814
<DD>sheep, 1063
</DL>
<DD>Shift instructions, 222, 255-256
<DD>Shifting bits, vs. lookup tables, 145-146
<DD><B>SHL</B> instruction, 376
<DD><B>ShowBounceCount</B> function, <B>823-824</B>
<DD><B>ShowPage</B> subroutine
<DL>
<DD>masked copying animation, Mode X, <B>929-930</B>
<DD>page flipping animation, <B>827</B>
</DL>
<DD><B>Show_text</B> function, <B>329</B>, <B>363</B>
<DD><B>SHR</B> instruction, 88-91, 97
<DD>SIB byte, 257
<DD>640&#215;400 mode, mode set routine, <B>852-853</B>
<DD>640&#215;480 mode, page flipping, 836-837
<DD>16-bit checksum program
<DL>
<DD><I>See also</I> TCP/IP checksum program.
<DD>assembly implementation, <B>10-12</B>, <B>17-18</B>
<DD>C language implementation, <B>8-9</B>, <B>15-16</B>
<DD>overview, 8
<DD>redesigning, 9
</DL>
<DD>16-color VGA modes
<DL>
<DD>color paging, 628-629
<DD>DAC (Digital/Analog Converter), 626-628
<DD>palette RAM, 626
</DL>
<DD>Small code model, linking Zen timer, 70
<DD>Software patents, 1194
<DD>Sorted span hidden surface removal
<DL>
<DD>abutting span sorting, 1229-1230
<DD><B>AddPolygonEdges</B> function, <B>1232-1233</B>, 1238
<DD>BSP order vs. 1/z order, 1220, 1226
<DD><B>ClearEdgeLists</B> function, <B>1236-1237</B>
<DD><B>DrawSpans</B> function, <B>1236</B>
<DD>edge sorting, 1220-1222
<DD>edges vs. spans, 1215-1220
<DD>independent span sorting, 1230, <B>1231-1238</B>, 1239-1241
<DD>intersecting span sorting, 1228-1229
<DD>1/z sorting, 1220-1222, 1227-1231, <B>1231-1238</B>, 1239-1241
<DD>overview, 1214-1215
<DD><B>PolyFacesViewer</B> function, <B>1232</B>
<DD><B>ScanEdges</B> function, <B>1234-1236</B>, 1238-1239
<DD><B>UpdateWorld</B> function, <B>1237-1238</B>
</DL>
<DD>Sorting techniques
<DL>
<DD>25-byte sorting routine, 180-181
<DD>BSP trees, 1099
<DD>moving models in 3-D drawings, 1212-1222
<DD>1/z sorting for hidden surface removal, 1220-1222
<DD>and optimization, 755
<DD>z-buffers, 1212-1213
</DL>
<DD><B>SortObjects</B> function, <B>1002</B>
<DD>Span-based drawing, and beam trees, 1187
<DD>Specular reflection, 1023
<DD>Split screens
<DL>
<DD>EGA bug, 573-574
<DD>horizontal panning, 574-575, <B>575-582</B>, 583
<DD>overview, 563-565
<DD>page flipping, 640&#215;480 mode, 836-837
<DD>registers, setting, 573
<DD>safety of, 585
<DD>split screen demo program, 565, <B>566-572</B>, 572
<DD>text mode, 584
<DD>turning on and off, 565
</DL>
<DD><B>SplitScreenDown</B> subroutine, <B>572</B>
<DD><B>SplitScreenUp</B> subroutine, <B>572</B>
<DD>Spotlights
<DL>
<DD>Gouraud shading, 1247
<DD>shading implementation, 1028
</DL>
<DD>Sprites
<DL>
<DD>masked images, 871-872
<DD>Quake 3-D engine, 1287
</DL>
<DD>Square wave timer mode, 44
<DD>Stack addressing
<DL>
<DD>address pipeline effects, 241-242
<DD>assembly language optimization, 420
</DL>
<DD>Stack frames, performance, 153
<DD>Stack pointer alignment, 218-219
<DD>Stack-based variables, placement of, 184-185
<DD>Stacks, <B>POPF</B> vs. <B>IRET</B>, 226-231
<DD>Stafford, David
<DL>
<DD>25-byte sorting routine, 180-181
<DD>Game of Life implementation, 351-352, <B>353-363</B>, 363-365
<DD><B>ScanBuffer</B> assembly routine, word count program, <B>309-311</B>, 317-319
<DD>24-byte hi/lo function, 292-293
</DL>
<DD>Start Address High and Low registers, 834-836
<DD>State machines
<DL>
<DD>3-cell-per-word implementation, Game of Life, 363-366
<DD>word count program, 315
</DL>
<DD><B>StepEdge</B> function, <B>1056-1057</B>
<DD><B>STOSB</B> instruction, 236
<DD>String instructions, 107
<DD>String searching. <I>See</I> Search engine; Searching.
<DD><B>Strstr()</B> function, 115
<DD><B>SUB</B> instruction, 219
<DD>Subdivision rasterization, 1266-1267, <B>1267-1270</B>, 1286
<DD>Superscalar execution
<DL>
<DD>initial pipe, effect of, 405
<DD>interleaving operations, 394-395
<DD>lockstep execution, 390-394, 400-403
<DD>overview, 384-386
<DD>register contention, 403-405
<DD>V-pipe-capable instructions, 386-387
</DL>
<DD>SuperVGA, 104, 107, 842-844
<DD>Surface caching
<DL>
<DD>hardware interactions, 1260-1262
<DD>surface-based lighting, 1253-1256
<DD>in VQuake, 1288
</DL>
<DD>Surface-based lighting
<DL>
<DD>description, 1250-1251
<DD>mipmapping, 1254-1255
<DD>performance, 1251-1253
<DD>surface caching, 1253-1256, 1260-1262
<DD>texture mapping, 1261-1262
</DL>
<DD>System clock
<DL>
<DD>inaccuracies
<DL>
<DD>long-period Zen timer, 53, 54
<DD>Zen timer, 43, 45-46, 48
</DL>
<DD>timer 0, 8253 chip, 44, 54
</DL>
<DD>System memory, Mode X
<DL>
<DD>copying to display memory, 908, <B>909-911</B>
<DD>masked copy to display memory, <B>916-918</B>, 916
</DL>
<DD>System wait states, 210-213
<DD><BIG><B>T</B></BIG>
<DD>Table-driven state machines, 316-319
<DD>Tail nodes, in linked lists, 286
<DD>TASM (Turbo Assembler), 71-72
<DD>TCP/IP checksum program
<DL>
<DD>basic implementation, <B>406</B>
<DD>dword implementation, <B>409</B>
<DD>interleaved implementation, <B>408</B>
<DD>unrolled loop implementation, <B>410</B>
</DL>
<DD><B>Test</B> function, <B>358</B>, 365
<DD><B>TEST</B> instruction, 377, 401-402
<DD>Texels
<DL>
<DD>Gouraud shading, 1247
<DD>mipmapping, 1254-1255
</DL>
<DD>Text, drawing
<DL>
<DD>bitmapped text demo program
<DL>
<DD>using bit mask, <B>466-469</B>, 470-471
<DD>using write mode 3, <B>484-489</B>, 489-490, <B>490-496</B>
</DL>
<DD>high-speed text demo program, using write mode 3, <B>490-496</B>
<DD>solid text demo program, using latches, 1039-1041, <B>1042-1044</B>
<DD>using write mode 0, 832-833
</DL>
<DD>Text mode
<DL>
<DD>display adapter cycle-eater, 104
<DD>horizontal resolution, 620
<DD>panning, 443
<DD>split screen operations, 584-585
</DL>
<DD>Text pages, flipping from graphics to text, 517
<DD>TEXT_UP macro, <B>454</B>, 459
<DD><B>TextUp</B> subroutine, <B>829</B>
<DD>Texture mapping
<DL>
<DD><I>See also</I> DDA (digital differential analyzer) texture mapping.
<DD>boundary pixels, polygons, 1049-1052, 1066, <B>1067</B>
<DD>C implementation, <B>1053-1058</B>
<DD>independent span sorting, 1238
<DD>onto 2-D transformed polygons, 1050
<DD>onto 3-D transformed polygons, 1051
<DD>onto untransformed polygon, 1049
<DD>optimization
<DL>
<DD>inner-loop optimizations, <B>1069-1073</B>, 1074, 1081-1084
<DD>instruction-by-instruction optimizations, 1086-1092
<DD>pointer advancement optimization, 1086-1089, <B>1090-1091</B>
<DD>vertical scanlines, 1084-1086
</DL>
<DD>orientation independence, 1065-1066, <B>1067</B>
<DD>overview, 1048
<DD>Pentium pipeline stalls, 1092
<DD>perspective correction, 1093
<DD>surface-based lighting, 1261-1262
<DD>vertical scanlines, 1084-1086
</DL>
<DD>32-bit addressing modes, 256-258
<DD>32-bit division, 181-184, 1008
<DD>32-bit fixed-point arithmetic, optimizing, 1086-1089, <B>1090-1091</B>, 1092-1093
<DD>32-bit instructions, optimizing, 1091
<DD>32-bit registers
<DL>
<DD><I>See also</I> Registers; VGA registers.
<DD>adding with <B>LEA</B>, 131
<DD><B>BSWAP</B> instruction, 252
<DD>multiplying with <B>LEA</B>, 132-133
<DD>386 processor, 222
<DD>time vs. space tradeoff, 187
<DD>using as two 16-bit registers, 253-254
</DL>
<DD>3-D animation
<DL>
<DD><I>See also</I> Hidden surface removal; 3-D drawing; 3-D polygon rotation demo program; X-Sharp 3-D animation package.
<DD>demo programs
<DL>
<DD>solid cube rotation program, <B>957-961</B>, 962-963, <B>964-966</B>, 967
<DD>3-D polygon rotation program, 939, <B>940-945</B>, 948-949
<DD>12-cube rotation program, 972, <B>973-984</B>, 985-987
</DL>
<DD>depth sorting, 1000, <B>1001-1002</B>
<DD>rotation
<DL>
<DD><B>ConcatXforms</B> function, <B>944</B>
<DD>matrix representation, 938-939
<DD>multiple axes of rotation, 948
<DD><B>XformVec</B> function, <B>943</B>
</DL>
<DD>rounding vs. truncation, 1002-1003
<DD>translation of objects, 937-938
</DL>
<DD>3-D clipping
<DL>
<DD>arithmetic imprecision, handling, 1240
<DD>line segments, clipping to planes, 1195-1197
<DD>overview, 1195
<DD>polygon clipping
<DL>
<DD><B>BackRotateVector</B> function, <B>1203</B>
<DD>clipping to frustum, 1200, <B>1201-1206</B>, 1206-1207
<DD><B>ClipToFrustum</B> function, <B>1204</B>
<DD><B>ClipToPlane</B> function, <B>1199</B>
<DD>optimization, 1207
<DD>overview, 1197-1200
<DD><B>PolyFacesViewer</B> function, <B>1203</B>
<DD><B>ProjectPolygon</B> function, <B>1201</B>
<DD><B>SetUpFrustum</B> function, <B>1204</B>
<DD><B>SetWorldspace</B> function, <B>1204</B>
<DD><B>TransformPoint</B> function, <B>1203</B>
<DD><B>TransformPolygon</B> function, <B>1203</B>
<DD><B>UpdateViewPos</B> function, <B>1202</B>
<DD><B>UpdateWorld</B> function, <B>1205</B>
<DD>viewspace clipping, 1207
<DD><B>ZSortObjects</B> function, <B>1201</B>
</DL>
</DL>
<DD>3-D drawing
<DL>
<DD><I>See also</I> BSP (Binary Space Partitioning) trees; Hidden surface removal; Polygons, filling; Shading; 3-D animation.
<DD>backface removal
<DL>
<DD>BSP tree rendering, 1160-1161
<DD>calculations, 955-957
<DD>motivation for, 954-955
<DD>and sign of dot product, 1140
<DD>solid cube rotation demo program, <B>957-961</B>, 962-963, <B>964-966</B>, 967
</DL>
<DD>background surfaces, 1240
<DD>draw-buffers, and beam trees, 1187
<DD>and dynamic objects, 1100-1101
<DD>Gouraud shading, 1246-1250
<DD>lighting
<DL>
<DD>Gouraud shading, 1246-1250
<DD>overlapping lights, 1247
<DD>perspective correctness, 1248-1250
<DD>rotational variance, 1249
<DD>surface-based lighting, 1250-1256, 1260-1262
<DD>viewing variance, 1249
</DL>
<DD>moving models in 3-D drawings, 1212-1222
<DD>painter&#146;s algorithm, 1099, 1104-1105
<DD>perspective correctness problem, 1248-1250
<DD>portals, and beam trees, 1188
<DD>projection
<DL>
<DD>dot products, 1141-1142
<DD>overview, 937, 948
</DL>
<DD>raycast, subdividing, and beam trees, 1187
<DD>reference materials, 934-935
<DD>rendering BSP trees
<DL>
<DD>backface removal, 1160-1161
<DD>clipping, 1158-1159
<DD><B>ClipWalls</B> function, <B>1152-1155</B>, 1158-1159
<DD><B>DrawWallsBackToFront</B> function, <B>1155-1156</B>, 1160-1161
<DD>overview, 1149
<DD>reference materials, 1157
<DD><B>TransformVertices</B> function, <B>1151-1152</B>, 1158
<DD><B>UpdateViewPos</B> function, <B>1151</B>, 1157
<DD><B>UpdateWorld</B> function, <B>1156-1157</B>, 1157
<DD>viewspace, transformation of objects to, 1158
<DD>wall orientation testing, 1160-1161
<DD><B>WallFacingViewer</B> function, <B>1150-1151</B>, 1161
</DL>
<DD>span-based drawing, and beam trees, 1187
<DD>transformation of objects, 935-936
<DD>triangle model drawing
<DL>
<DD>fast triangle drawing, 1263-1265
<DD>overview, 1262-1263
<DD>precision, 1265
<DD>subdivision rasterization, 1266-1267, <B>1267-1270</B>
</DL>
<DD>vertex-free surfaces, and beam trees, 1187
<DD>visibility determination, 1099-1106
<DD>visible surface determination (VSD)
<DL>
<DD>beam trees, 1185-1189
<DD>culling to frustum, 1181-1184
<DD>overdraw problem, 1184-1185
<DD>polygon culling, 1181-1184
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
</DL>
<DD>3-D engine, Quake
<DL>
<DD>BSP trees, 1276-1277
<DD>lighting, 1282-1283
<DD>model overview, 1276-1277
<DD>portals, 1279-1280
<DD>potentially visible set (PVS), 1278-1279
<DD>rasterization, 1282
<DD>world, drawing, 1280-1281
</DL>
<DD>3-D math
<DL>
<DD>cross products, 1139-1140
<DD>dot products
<DL>
<DD>calculating, 1135-1137
<DD>calculating light intensity, 1137
<DD>projection, 1141-1142
<DD>rotation, 1143-1144
<DD>sign of, 1140-1141
<DD>of unit vectors, 1136
<DD>of vectors, 1135-1136
</DL>
<DD>matrix math
<DL>
<DD>assembly routines, 992, <B>996-999</B>
<DD>C-language implementations, <B>974-976</B>
<DD>normal vectors, calculating, 955-956
<DD>rotation of 3-D objects, 938-939, <B>943-944</B>, 948
<DD>transformation, optimized, 1172-1173, <B>1173-1174</B>
</DL>
<DD>vector length, 1135
</DL>
<DD>3-D polygon rotation demo program
<DL>
<DD>matrix multiplication functions, <B>943-944</B>, 948
<DD>overview, 939
<DD>performance, 949
<DD>polygon filling with clipping support, <B>940-943</B>
<DD>transformation and projection, <B>944-945</B>, 948
</DL>
<DD>3-D solid cube rotation demo program
<DL>
<DD>basic implementation, <B>957-961</B>, 962-963
<DD>incremental transformations, <B>964-966</B>
<DD>object representation, 967
</DL>
<DD>386 native mode, 32-bit displacements, 187
<DD>386 processor
<DL>
<DD>alignment, stack pointer, 218-219
<DD><B>CMP</B> instruction, 161, 306
<DD>cycle-eaters, 209-210
<DD>data alignment, 213, 218
<DD>and display adapter cycle-eater, 107
<DD>display adapter cycle-eater, 219-221
<DD>doubleword alignment, 218
<DD>DRAM refresh cycle-eater, 219
<DD>effective address calculations, 129, 223-225
<DD><B>LEA</B> instruction, 130-133, 172
<DD><B>LODSD</B> vs. <B>MOV/LEA</B> sequence, 171
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>memory access, performance, 223-225
<DD><B>MUL</B> and <B>IMUL</B> instructions, 173-174
<DD>multiplication operations, increasing speed of, 173-174
<DD>new instructions and features, 222
<DD>Pentium code, running on, 411
<DD>protected mode, 208-209
<DD>rotation instructions, clock cycles, 185-186
<DD>system wait states, 210-212
<DD>32-bit addressing modes, 256-258
<DD>32-bit multiply and divide operations, 985
<DD>using 32-bit register as two 16-bit registers, 253-254
<DD><B>XCHG</B> vs. <B>MOV</B> instructions, 377, 832
</DL>
<DD>386SX processor, 16-bit bus cycle-eater, 81
<DD>360&#215;480 256-color mode
<DL>
<DD>display memory, accessing, 621-622
<DD><B>Draw360&#215;480Dot</B> subroutine, 613-614
<DD>drawing speed, 618
<DD>horizontal resolution, 620
<DD>line drawing demo program, <B>615-618</B>, 618-619
<DD>mode set routine (John Bridges), 609, <B>612</B>, 620-621
<DD>on VGA clones, 610-611
<DD><B>Read360&#215;480Dot</B> subroutine, <B>614-615</B>
<DD>256-color resolution, 619-620
<DD>vertical resolution, 619
</DL>
<DD>320x400 256-color mode
<DL>
<DD>advantages of, 590-591
<DD>display memory organization, 591-593
<DD>line drawing, 600
<DD>page flipping demo program, <B>600-605</B>
<DD>performance, 599-600
<DD>pixel drawing demo program, <B>593-598</B>, 599-600
</DL>
<DD>320&#215;240 256-color mode. <I>See</I> Mode X.
<DD>Time perception, subjectivity of, 972
<DD>Time-critical code, 13
<DD>Timer 0, 8253 timer chip
<DL>
<DD>operation, 44
<DD>stopping, 54, 65
</DL>
<DD>Timer modes, 44, 45
<DD><B>TIMER_INT</B> BIOS routine, 44
<DD>Timers
<DL>
<DD><I>See also</I> 8253 timer chip; Long-period Zen timer; Zen timer.
<DD>divide-by-N mode, 45
<DD>square wave mode, 44
</DL>
<DD>Timeslicing delays, 446
<DD>Timing intervals
<DL>
<DD>long-period Zen timer, 53
<DD>Zen timer, 45
</DL>
<DD>Transformation inefficiencies, 25-26
<DD>Transformation matrices. <I>See</I> Matrices; Matrix math.
<DD>Transformation of 3-D objects
<DL>
<DD>defined, 1135
<DD>floating point optimization, 1172-1173, <B>1173-1174</B>
<DD>incremental transformations, 964
<DD>steps in, 935-936
</DL>
<DD><B>TransformPolygon</B> function, <B>1203</B>
<DD>Translation in 3-D space, 937-938
<DD>Treuenfels, Anton, 756
<DD>Triangle model drawing
<DL>
<DD>fast triangle drawing, 1263-1265
<DD>overview, 1262-1263
<DD>precision, 1265
<DD>subdivision rasterization, 1266-1267, <B>1267-1270</B>
</DL>
<DD>Triangles, and rotational variance, 1249-1250
<DD>Trinity, 1294
<DD>Truncation errors, in 3-D animation, 1002-1003
<DD>Truncation vs. rounding
<DL>
<DD>floating point optimization, 1174-1175
<DD>texture mapping, 1066-1067
</DL>
<DD>TSRs, and DAC, loading, 643, 648
<DD>Turbo Profiler, and 80&#215;87 emulator, Borland C++, 999
<DD>12-cube rotation demo program
<DL>
<DD>limitations of, 986
<DD>optimizations in, 985-986
<DD>performance, 986
<DD>X-Sharp animation package, 972, <B>973-984</B>, 984-985
</DL>
<DD>24-byte hi/lo function, 292-293
<DD>286 processor
<DL>
<DD><B>CMP</B> instruction, 161, 306
<DD>code alignment, 215-218
<DD>cycle-eaters, 209-210
<DD>data alignment, 213-215
<DD>data transfer rates, 212
<DD>display adapter cycle-eater, 219-221
<DD>display memory wait states, 220
<DD>DRAM refresh cycle-eater, 219
<DD>effective address calculations, 129, 223-225
<DD>instruction fetching, 215-218
<DD><B>LEA</B> vs. <B>ADD</B> instructions, 130
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>memory access, performance, 223-225
<DD>new features, 221
<DD><B>POPF</B> instruction, and interrupts, 226
<DD>protected mode, 208-209
<DD>stack pointer alignment, 218-219
<DD>system wait states, 210-212
</DL>
<DD>256-color modes
<DL>
<DD><I>See also</I> 320x400 256-color mode.
<DD>DAC settings, 629
<DD>mapping RGB model to, 1036, <B>1037-1038</B>, 1039
<DD>resolution, 360x480 256-color mode, 619-620
</DL>
<DD>Two-pass lighting, 1262
<DD>Two&#146;s complement negation, 171
<DD><BIG><B>U</B></BIG>
<DD>Unifying models, and optimization, 1110-1111
<DD>Unit normal of polygons, calculating, 1027-1028, 1137-1140
<DD>Unit vectors, dot product, 1136-1137
<DD>Unrolling loops, 143-145, 305, 312, 377-378, 410
<DD><B>UpdateViewPos</B> function, <B>1202</B>
<DD><B>UpdateWorld</B> function, <B>1205</B>, <B>1237-1238</B>
<DD>U-pipe, Pentium processor
<DL>
<DD>branch instructions, 404-405
<DD>overview, 385-386
<DD>pairable instructions, 388
<DD><BIG><B>V</B></BIG>
</DL>
<DD>Variables, word-sized vs. byte-sized, 82, 83-85
<DD>Vectors
<DL>
<DD>cross product, 1139-1140
<DD>cross-products, calculating, 955-956
<DD>dot product, 1135-1137
<DD>length equation, 1135
<DD>optimization of, 986
<DD>unit vectors, dot product, 1136-1137
</DL>
<DD><B>VectorsUp</B> function
<DL>
<DD>Bresenham&#146;s line-drawing algorithm, <B>664-665</B>
<DD>360x480 256-color mode line drawing program, <B>617-618</B>
</DL>
<DD>Verite Quake, 1287-1280
<DD>Vertex-free surfaces, and beam trees, 1187
<DD>Vertical blanking, loading DAC, 641
<DD>Vertical resolution, 360x480 256-color mode, 619
<DD>Vertical scanlines, in texture mapping, 1084-1086
<DD>Vertical sync pulse
<DL>
<DD>loading DAC, 641, 648
<DD>and page flipping, 444-446, 835-836
<DD>split screens, 573
</DL>
<DD>VGA BIOS
<DL>
<DD>DAC (Digital/Analog Converter)
<DL>
<DD>loading, 641-642, 648
<DD>setting registers, 630, 631-632
</DL>
<DD>vs. direct hardware programming, 458-459
<DD>function 13H, 459
<DD>and nonstandard modes, 854-855
<DD>palette RAM, setting registers, 629-630, 631-632
<DD>reading from DAC, 652
<DD>text routines, in 320&#215;400 256-color mode, 592
<DD>and VGA registers, 458
</DL>
<DD>VGA clones
<DL>
<DD>potential incompatibilities, 446-447
<DD>360&#215;480 256-color mode, 610-611
</DL>
<DD>VGA color path
<DL>
<DD>color paging, 628-629
<DD>DAC (Digital/Analog Converter), 626-628, 630, 631-632
<DD>palette RAM, 626, 629-630, 631-632
</DL>
<DD>VGA compatibility, 446-447, 610-611
<DD>VGA memory
<DL>
<DD>Color Don&#146;t Care register, <B>535-537</B>, 535
<DD>CPU reads, 520, 526
</DL>
<DD>VGA modes
<DL>
<DD>bit-plane animation, 811
<DD>color compare mode, <B>531-534</B>, 531
<DD>mode 0, set/reset circuitry, 471-472, 474-479
<DD>mode 12H (hi-res mode), page flipping, 851-855
<DD>mode 13H
<DL>
<DD>converting to 320&#215;400 256-color mode, 593
<DD>overview, 515
<DD>resolution, 590
</DL>
<DD>Mode X
<DL>
<DD>bitmap organization, 882-883
<DD>copying pixels using latches, <B>905-907</B>, 908, <B>909-911</B>
<DD>features, 878-879
<DD>four-plane parallel processing, 888-891, <B>891-893</B>
<DD>masked copying, <B>916-918</B>, 916, 918-919, <B>919-921</B>
<DD>memory allocation, 903-904
<DD>mode set routine, <B>880-881</B>, 882
<DD>pattern fills, 899, <B>900-903</B>, 903-904
<DD>pixel-by-pixel plane selection, <B>885-887</B>
<DD>plane-by-plane processing, <B>887-889</B>
<DD><B>ReadPixelX</B> subroutine, <B>884-885</B>
<DD><B>WritePixelX</B> subroutine, <B>883-884</B>
</DL>
<DD>and page flipping, 444-445
<DD>read mode 1
<DL>
<DD>Color Don&#146;t Care register, 534
<DD>overview, 525-526, 531
<DD>selecting, 525
</DL>
<DD>and set/reset circuitry, 478
<DD>640&#215;400 mode set routine, <B>852-853</B>
<DD>split screen operations, 584-585
<DD>text mode, panning, 443
<DD>320&#215;400 256-color mode
<DL>
<DD>advantages, 590-591
<DD>converting mode 13H to, 593
<DD>display memory organization, 591-593
<DD>page flipping demo program, <B>600-605</B>
</DL>
<DD>and virtual screens, 441
<DD>write mode 0, drawing text, 832-833
<DD>write mode 1, overview, 444
<DD>write mode 2
<DL>
<DD>chunky bitmaps, converting to planar, 504-505, <B>505-508</B>
<DD>mechanics, 502
<DD>overview, 501-502
<DD>selecting, 504
</DL>
<DD>write mode 3
<DL>
<DD>vs. Bit Mask register, 844
<DD>drawing bitmapped text, <B>484-489</B>, 489-490, <B>490-496</B>
<DD>overview, 483-484, 496
<DD>single-color drawing, 831-832
<DD>vs. write mode 0, 490
</DL>
</DL>
<DD>VGA registers
<DL>
<DD>AC Index register, bit 5 settings, 443
<DD>Bit Mask register
<DL>
<DD>bit mask, controlling, 465
<DD>drawing solid text, 1040
<DD>setting inside a loop, 429
<DD>vs. write mode 3, 832, 844
</DL>
<DD>Color Compare register, in read mode 1, 531
<DD>Color Don&#146;t Care register, in read mode 1, 534
<DD>Color Select register, color paging, 628-629
<DD>Data register, loading DAC, 642-643
<DD>Data Rotate register
<DL>
<DD>barrel shifter, controlling, 463
<DD>vs. CPU-based rotations, 489
<DD>effect on ALUs, 452
</DL>
<DD>Enable Set/Reset register
<DL>
<DD>setting drawing color, 666
<DD>specifying plane, 474
</DL>
<DD>Graphics Mode register
<DL>
<DD>read mode 0, selecting, 525
<DD>read mode 1, selecting, 531
</DL>
<DD>and high-level languages, 548
<DD>Horizontal Pel Panning register, 442
<DD>internal indexing, 427-429
<DD>Line Compare register, split screen operation, 565
<DD>Map Mask register
<DL>
<DD>drawing text, 833
<DD>optimizing Mode X, 1074
<DD>vs. Read Map register, 526
<DD>selecting planes for CPU writes, 443-444, 471-472
<DD>with set/reset circuitry, 474
<DD>write mode 1, 444
</DL>
<DD>Mask register, blanking screen, 651
<DD>Mode Control register, pel panning in split screen, 575
<DD>Mode register
<DL>
<DD>color paging, 628-629
<DD>256-color modes, 629
</DL>
<DD>Overflow register, split screen operation, 565
<DD>palette RAM registers, setting, 631-632
<DD>Pel Panning register, 574, 583
<DD>Read Index register, 651-652
<DD>Read Map register
<DL>
<DD>plane, selecting, for CPU reads, 526
<DD>planes, specifying to be read, 542
</DL>
<DD>Set/Reset register, setting drawing color, 666
<DD>setting, 504, 558
<DD>setting and reading, 582
<DD>Start Address High and Low registers, 834-836
<DD>and VGA BIOS, 458
<DD>Write Index register
<DL>
<DD>DAC index wrapping, 651
<DD>loading DAC, 642-643
</DL>
</DL>
<DD>VGA (Video Graphics Adapter)
<DL>
<DD>ALU and latch demo program, <B>453-457</B>, 458-460
<DD>architecture, 426-429
<DL>
<DD>ALUs, 451-452
<DD>barrel shifter, 463-464
<DD>bit mask, 464-471
<DD>latches, 452-453
<DD>set/reset circuitry, 471-479
</DL>
<DD>ball animation demo program, <B>431-441</B>
<DD>CGA compatibility, 430
<DD>delay sequences, 558
<DD>and display adapter cycle-eater, 104-108
<DD>display memory, 446
<DD>fill patterns, drawing, 453
<DD>GC (Graphics Controller), architecture, 451-453, 463-479
<DD>I/O access times, 842-844
<DD>linear addressing, 430
<DD>memory access times, 842-844
<DD>overview, 426
<DD>page flipping, 444-446
<DD>panning, 441-443
<DD>performance, with 486 processor, 842-844
<DD>potential incompatibilities, 446-447
<DD>registers, internal indexing, 426-429
<DD>screens, capturing and restoring, 541-542, <B>543-547</B>, 547-548
<DD>split screens
<DL>
<DD>horizontal panning, 574-575, <B>575-582</B>, 583
<DD>overview, 563-565
<DD>registers, setting, 573
<DD>safety of, 585
<DD>split screen demo program, 565, <B>566-572</B>, 572
<DD>text mode, 584
<DD>turning on and off, 565
</DL>
<DD>25 MHz clock and 28 MHz clock, switching between, 620-621
<DD>virtual screens
<DL>
<DD>overview, 430
<DD>panning, 441-443
</DL>
</DL>
<DD>Video function 10H, EGA BIOS, 550-551, 555
<DD>Viewing angle, and BSP tree rendering, 1157-1158
<DD>Viewing variance, 1249
<DD>Viewspace
<DL>
<DD>defined, 1135
<DD>and normals of polygons, 1137-1138
<DD>in 3-D transformation, 935
<DD>transformation to, BSP rendering, 1158
<DD>uses for, 967
</DL>
<DD>Viewspace clipping, 1207
<DD>Virtual screens
<DL>
<DD>overview, 430
<DD>panning, 441-443
</DL>
<DD>Visibility determination
<DL>
<DD><I>See also</I> Visible surface determination.
<DD>and BSP trees, 1099-1106
</DL>
<DD>Visibility of polygons, calculating, 955-956
<DD>Visible surface determination (VSD)
<DL>
<DD>beam trees, 1185-1189
<DD>culling to frustum, 1181-1184
<DD>overdraw problem, 1184-1185
<DD>polygon culling, 1181-1184
<DD>and portals, 1279-1280
<DD>potentially visible set (PVS), precalculating, 1188-1189
</DL>
<DD>V-pipe, Pentium processor
<DL>
<DD>branch instructions, 404-405
<DD>overview, 385-386
<DD>V-pipe-capable instructions, 386-387
</DL>
<DD>VQuake, 1287-1280
<DD>VSD. <I>See</I> Visible surface determination (VSD).
<DD><BIG><B>W</B></BIG>
<DD><B>Wait30Frames</B> function, <B>854</B>
<DD>Wait states
<DL>
<DD>display memory wait states
<DL>
<DD>8088 processor, 101-103
<DD>286 processor, 220
</DL>
<DD>vs. DRAM refresh, 100
<DD>overview, 99
<DD>system memory wait states, 210-213
</DL>
<DD><B>WaitForVerticalSyncEnd</B> subroutine, <B>569</B>, <B>579-580</B>
<DD><B>WaitForVerticalSyncStart</B> subroutine, <B>569</B>, <B>579</B>
<DD><B>WalkBSPTree</B> function, <B>1106</B>
<DD><B>WalkTree</B> function
<DL>
<DD>code recursive version, <B>1108</B>
<DD>data recursive version, <B>1109-1110</B>
</DL>
<DD>Wall orientation testing, BSP tree rendering, 1160-1161
<DD>WC word counting program (TerjeMathisen), optimization, 250-252, 306, 319
<DD>Williams, Rob, 174
<DD>Winnie the Pooh orbiting Saturn, 1047
<DD>WinQuake, 1290
<DD>Word alignment, 286 processor
<DL>
<DD>code alignment, 215-218
<DD>data alignment, 213-215
<DD>stack pointer alignment, 218-219
</DL>
<DD>Word count program
<DL>
<DD>edge triggered device, 316
<DD>fine-tuning optimization, 312-313
<DD>initial C implementation, <B>299</B>
<DD>lookup table, <B>303</B>, 304, 317-319
<DD><B>ScanBuffer</B> assembly routine
<DL>
<DD>author&#146;s implementation, <B>301-302</B>
<DD>Stafford, David&#146;s, <B>309-311</B>, 317-319
<DD>Willem Clements&#146; implementation, <B>313-315</B>
</DL>
<DD>as state machine, 315
<DD>theoretical maximum performance, 319
</DL>
<DD>Word-<B>OUT</B> instruction, 429
<DD>Word-sized variables, 8088 processor
<DL>
<DD>memory access, 82
<DD>optimization, 83-85
</DL>
<DD>World, drawing, in Quake 3-D engine, 1280-1281
<DD>Worldspace
<DL>
<DD>defined, 1135
<DD>in 3-D transformation, 935
<DD>uses for, 967
</DL>
<DD>Write Index register
<DL>
<DD>DAC index wrapping, 651
<DD>loading DAC, 642-643
</DL>
<DD>Write mode 0
<DL>
<DD>drawing text, 832-833
<DD>vs. write mode 2, 503
</DL>
<DD>Write mode 1
<DL>
<DD>overview, 444
<DD>vs. write mode 3, 490
</DL>
<DD>Write mode 2
<DL>
<DD>chunky bitmaps, converting to planar, 504-505, <B>505-508</B>
<DD>color-patterned lines demo program, <B>509-515</B>
<DD>mechanics, 502
<DD>overview, 501-502
<DD>selecting, 504
<DD>vs. set/reset circuitry, 509, 515
<DD>vs. write mode 0, 503
</DL>
<DD>Write mode 3
<DL>
<DD>vs. Bit Mask register, 844
<DD>character/attribute map, 517
<DD>drawing bitmapped text, <B>484-489</B>, 489-490, <B>490-496</B>
<DD>drawing solid text, 1039-1041, <B>1042-1044</B>
<DD>graphics, preserving on switch to, 515-517, <B>518-521</B>
<DD>overview, 483-484, 496
<DD>single-color drawing, 831-832
<DD>vs. write mode 1, 490
</DL>
<DD>Write mode 3 demo program, <B>484-489</B>, 489-490, <B>490-496</B>
<DD>Write modes, VGA
<DL>
<DD>and set/reset circuitry, 478
<DD>text, drawing, 484, 490, 496
</DL>
<DD>Write-after-write register contention, 404
<DD><B>WritePixel</B> subroutine, <B>597</B>, 599
<DD><B>WritePixelX</B> subroutine, <B>883-884</B>
<DD>Writing pixels
<DL>
<DD>320&#215;400 256-color mode, 599, 600
</DL>
<DD>Wu antialiasing algorithm
<DL>
<DD>assembly implementation, <B>787-791</B>
<DD>C-language implementation, <B>780-786</B>
<DD>description, 776-778, 791-792
<DD>error accumulation, 778-779, 792
<DD>performance, 777-778
<DD>pixel intensity calculations, 778-779
</DL>
<DD>Wu, Xiaolin. <I>See</I> Wu antialiasing algorithm.
<DD><BIG><B>X</B></BIG>
<DD>X86 family CPUs
<DL>
<DD><I>See also</I> 8088 processor.
<DD>32-bit division, 181-184, 1008
<DD>branching, performance, 140
<DD>copying bytes between registers, 172
<DD>interrupts, 9
<DD>limitations for assembly programmers, 27
<DD>lookup tables, vs. rotating or shifting, 145-146
<DD><B>LOOP</B> instruction vs. <B>DEC/JNZ</B> sequence, 139
<DD>machine instructions, versatility, 128
<DD>memory addressing modes, 129-133
<DD>overview, 208
<DD>transformation inefficiencies, 26
</DL>
<DD><B>XCHG</B> instruction, 377, 832
<DD>X-clipping, in BSP tree rendering, 1159
<DD><B>XformAndProjectPObject</B> function, <B>974</B>
<DD><B>XformAndProjectPoints</B> function, <B>960</B>
<DD><B>XformAndProjectPoly</B> function, <B>944-945</B>
<DD><B>XformVec</B> function
<DL>
<DD>assembly implementation, <B>996-997</B>, <B>1017-1019</B>
<DD>C implementation, <B>943</B>, <B>976</B>
</DL>
<DD><B>XLAT</B> instruction
<DL>
<DD>in Boyer-Moore algorithm, 274-277
<DD>byte registers, 243
<DD>with lookup table, 304
</DL>
<DD><B>XOR</B> instruction, vs. <B>NOT</B>, 147
<DD>X-Sharp 3-D animation package
<DL>
<DD><B>AppendRotationX</B> function, <B>975</B>
<DD><B>AppendRotationY</B> function, <B>964-965</B>, <B>975</B>
<DD><B>AppendRotationZ</B> function, <B>965</B>, <B>976</B>
<DD>code archives on diskette, 985
<DD><B>ConcatXforms</B> function
<DL>
<DD>assembly implementation, <B>997-999</B>, <B>1019-1022</B>
<DD>C implementations, <B>944</B>, <B>976</B>
</DL>
<DD><B>CosSin</B> subroutine, <B>994-996</B>, 999, <B>1013-1015</B>
<DD>DDA (digital differential analyzer) texture mapping
<DL>
<DD>assembly implementation, <B>1069-1073</B>, 1074
<DD>C implementation, <B>1053-1058</B>
<DD>disadvantages, 1052-1053, 1059
<DD><B>DrawTexturedPolygon</B>, <B>1055-1056</B>
<DD>hardware dependence, 1053
<DD>multiple adjacent polygons, 1068
<DD>optimized implementation, <B>1069-1073</B>, 1074
<DD>orientation independence, 1065-1067, <B>1067</B>
<DD>performance, 1074
<DD><B>ScanOutLine</B> function, <B>1058-1059</B>, <B>1067</B>
<DD><B>SetUpEdge</B> function, <B>1057-1058</B>
<DD><B>StepEdge</B> function, <B>1056-1057</B>
<DD>techniques, 1048-1051
</DL>
<DD><B>DrawPObject</B> function, <B>978-979</B>
<DL>
<DD>ambient and diffuse shading support, <B>1025-1027</B>
</DL>
<DD><B>FixedDiv</B> subroutine, <B>982</B>, <B>993</B>, <B>1010-1012</B>
<DD>FIXED_MUL macro, 1016-1017
<DD><B>FixedMul</B> subroutine, <B>981</B>, <B>993-994</B>, <B>1009-1010</B>
<DD><B>InitializeCubes</B> function, <B>980-981</B>
<DD><B>InitializeFixedPoint</B> function, <B>977</B>
<DD>matrix math, assembly routines, 992, <B>996-999</B>
<DD><B>ModelColorToColorIndex</B> function, 1036, <B>1038</B>
<DD>older processors, support for, 1007-1008, <B>1008-1023</B>
<DD>overview, 984-985
<DD>POLYGON.H header file, <B>982-984</B>
<DD>RGB color model
<DL>
<DD>mapping to 256-color mode, 1036, <B>1037-1038</B>, 1039
<DD>overview, 1034-1035
</DL>
<DD><B>RotateAndMovePObject</B> function, <B>977-978</B>
<DD><B>XformAndProjectPObject</B> function, <B>974</B>
<DD><B>XformVec</B> function
<DL>
<DD>assembly implementation, <B>996-997</B>, <B>1017-1019</B>
<DD>C implementation, <B>976</B>
</DL>
</DL>
<DD><B>XSortAET</B> function
<DL>
<DD>complex polygons, <B>748</B>
<DD>monotone-vertical polygons, <B>769</B>
<DD><BIG><B>Y</B></BIG>
</DL>
<DD>Yaw angle, in polygon clipping, 1206
<DD>Y-clipping, in BSP tree rendering, 1159
<DD><BIG><B>Z</B></BIG>
<DD>Z-buffers
<DL>
<DD>performance, 1213
<DD>Quake 3-D engine, 1285-1286
<DD>vs. sorted spans, 1215
<DD>sorting moving models, 1212-1213
</DL>
<DD>Z-clipping, in BSP tree rendering, 1158
<DD>Zen timer
<DL>
<DD><I>See also</I> Long-period Zen timer.
<DD>calling, 48
<DD>calling from C code, 69-72
<DD>and DRAM refresh, 99
<DD>and interrupts, 43
<DD>interval length, 45
<DD>overhead of, timing, 46, 72
<DD>PC compatibility, 48-49
<DD>precision, 48, 52
<DD>prefetch queue cycle-eater, 88, 92
<DD>PS/2 compatibility, 66
<DD>PZTEST.ASM listing, <B>49</B>
<DD>PZTIME.BAT listing, <B>51</B>
<DD>PZTIMER.ASM listing, <B>35-42</B>
<DD><B>ReferenceZTimerOff</B> subroutine, <B>41</B>
<DD><B>ReferenceZTimerOn</B> subroutine, <B>40</B>
<DD>reporting results, 47
<DD>starting, 43
<DD>stopping, 46
<DD>system clock inaccuracies, 43, 45-46, 48
<DD>test-bed program, 48-52
<DD>TESTCODE listing, <B>50</B>
<DD>timing 486 code, 245-246
<DD><B>ZTimerOff</B> subroutine, <B>38-41</B>, 46-47
<DD><B>ZTimerOn</B> subroutine, <B>37-38</B>, 43
<DD><B>ZTimerReport</B> subroutine, <B>41-42</B>, 47-48
</DL>
<DD>Zero-wait-state memory, 211
<DD>Z-order display, masked images, 872
<DD>Z-sorting, for hidden surface removal, 1220-1222
<DD><B>ZSortObjects</B> function, <B>1201</B>
<DD><B>ZTimerOff</B> subroutine
<DL>
<DD>long-period Zen timer, <B>59-63</B>
<DD>Zen timer, <B>38-41</B>, 46-47
</DL>
<DD><B>ZTimerOn</B> subroutine
<DL>
<DD>long-period Zen timer, <B>58-59</B>
<DD>Zen timer, <B>37-38</B>, 43
</DL>
<DD><B>ZTimerReport</B> subroutine
<DL>
<DD>long-period Zen timer, <B>63-65</B>
<DD>Zen timer, <B>41-42</B>, 47-48
</DL>
</DL>
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