151 lines
8.6 KiB
HTML
151 lines
8.6 KiB
HTML
<HTML>
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<HEAD>
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<META name=vsisbn content="1576101746">
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<META name=vstitle content="Michael Abrash's Graphics Programming Black Book, Special Edition">
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<META name=vsauthor content="Michael Abrash">
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<META name=vspublisher content="The Coriolis Group">
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<META name=vspubdate content="07/01/97">
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<META name=vscategory content="Web and Software Development: Game Development,Web and Software Development: Graphics and Multimedia Development">
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<TITLE>Michael Abrash's Graphics Programming Black Book Special Edition: Unleashing the Pentium's</TITLE>
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<!-- HEADER -->
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<!-- Empty Reference Subhead -->
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<!--ISBN=1576101746//-->
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<!--TITLE=Michael Abrash's Graphics Programming Black Book Special Edition//-->
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<!--AUTHOR=Michael Abrash//-->
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<!--PUBLISHER=The Coriolis Group, Inc.//-->
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<!--CHAPTER=21//-->
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<!--PAGES=407-409//-->
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<!--UNASSIGNED1//-->
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<!--UNASSIGNED2//--></HEAD><BODY LINK=#0000FF ALINK=#000099 VLINK=#0000FF BGCOLOR=#FFFFFF>
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<TR>
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<TD><A HREF="21-03.html">Previous</A></TD>
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<TD><A HREF="index.html">Table of Contents</A></TD>
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<TD><A HREF="21-05.html">Next</A></TD>
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<P><BR></P>
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<P>The first, obvious thing we can do to Listing 21.1 is change <B>ADC AX,0</B> to <B>ADC EAX,0</B>, eliminating a prefix byte and saving a full cycle. Now we’re down from five to four cycles. What next?</P>
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<P>Listing 21.2 shows one interesting alternative that doesn’t really buy us anything. Here, we’ve eliminated all size prefixes by doing byte-sized <B>MOVs</B> and <B>ADDs</B>, but because the size prefix on <B>ADD AX,[ESI]</B>, for whatever reason, didn’t cost anything in Listing 21.1, our efforts are to no avail—Listing 21.2 still takes 4 cycles per checksummed word. What’s worth noting about Listing 21.2 is the extent to which the code is broken into simple instructions and reordered so as to avoid size prefixes, register contention, AGIs, and data bank conflicts (the latter because both <B>[ESI]</B> and <B>[ESI+1]</B> are in the same cache data bank, as discussed in the last chapter).</P>
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<P><B>LISTING 21.2 L21-2.ASM</B></P>
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<!-- CODE //-->
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<PRE>
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; Calculates TCP/IP (16-bit carry-wrapping) checksum for buffer
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; starting at ESI, of length ECX words.
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; Returns checksum in AX.
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; High word of EAX, DX, ECX and ESI destroyed.
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; All cycle counts assume 32-bit protected mode.
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; Assumes buffer length > 0.
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sub eax,eax ;initialize the checksum
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mov dx,[esi] ;first word to checksum
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dec ecx ;we’ll do 1 checksum outside the loop
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jz short ckloopend ;only 1 checksum to do
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add esi,2 ;point to the next word to checksum
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ckloop:
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add al,dl ;cycle 1 U-pipe
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mov dl,[esi] ;cycle 1 V-pipe
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adc ah,dh ;cycle 2 U-pipe
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mov dh,[esi+1] ;cycle 2 V-pipe
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adc eax,0 ;cycle 3 U-pipe
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add esi,2 ;cycle 3 V-pipe
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dec ecx ;cycle 4 U-pipe
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jnz ckloop ;cycle 4 V-pipe
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ckloopend:
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add ax,dx ;checksum the last word
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adc eax,0
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</PRE>
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<!-- END CODE //-->
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<P>Listing 21.3 is a more sophisticated attempt to speed up the checksum calculation. Here we see a hallmark of Pentium optimization: two operations (the checksumming of the current and next pair of words) interleaved together to allow both pipes to run at near maximum capacity. Another hallmark that’s apparent in Listing 21.3 is that Pentium-optimized code tends to use more registers and require more instructions than 486-optimized code. Again, note the careful mixing of byte-sized reads to avoid AGIs, register contention, and cache bank collisions, in particular the way in which the byte reads of memory are interspersed with the additions to avoid register contention, and the placement of <B>ADD ESI,4</B> to avoid an AGI.</P>
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<P><B>LISTING 21.3 L21-3.ASM</B></P>
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<!-- CODE //-->
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<PRE>
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; Calculates TCP/IP (16-bit carry-wrapping) checksum for buffer
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; starting at ESI, of length ECX words.
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; Returns checksum in AX.
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; High word of EAX, BX, EDX, ECX and ESI destroyed.
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; All cycle counts assume 32-bit protected mode.
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; Assumes buffer length > 0.
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sub eax,eax ;initialize the checksum
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sub edx,edx ;prepare for later ORing
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shr ecx,1 ;we’ll do two words per loop
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jnc short ckloopsetup ;even number of words
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mov ax,[esi] ;do the odd word
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jz short ckloopdone ;no more words to checksum
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add esi,2 ;point to the next word
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ckloopsetup:
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mov dx,[esi] ;load most of 1st word to
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mov bl,[esi+2] ; checksum (last byte loaded in loop)
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dec ecx ;any more dwords to checksum?
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jz short ckloopend ;no
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ckloop:
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mov bh,[esi+3] ;cycle 1 U-pipe
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add esi,4 ;cycle 1 V-pipe
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shl ebx,16 ;cycle 2 U-pipe
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;cycle 2 V-pipe idle
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; (register contention)
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or ebx,edx ;cycle 3 U-pipe
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mov dl,[esi] ;cycle 3 V-pipe
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add eax,ebx ;cycle 4 U-pipe
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mov bl,[esi+2] ;cycle 4 V-pipe
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adc eax,0 ;cycle 5 U-pipe
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mov dh,[esi+1] ;cycle 5 V-pipe
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dec ecx ;cycle 6 U-pipe
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jnz ckloop ;cycle 6 V-pipe
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ckloopend:
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mov bh,[esi+3] ;checksum the last dword
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add ax,dx
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adc ax,bx
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adc ax,0
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mov edx,eax ;compress the 32-bit checksum
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shr edx,16 ; into a 16-bit checksum
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add ax,dx
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adc eax,0
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ckloopdone:
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</PRE>
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<!-- END CODE //-->
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<P>The checksum loop in Listing 21.3 takes longer than the loop in Listing 21.2, at 6 cycles versus 4 cycles for Listing 21.2—but Listing 21.3 does two checksum operations in those 6 cycles, so we’ve cut the time per checksum addition from 4 to 3 cycles. You might think that this small an improvement doesn’t justify the additional complexity of Listing 21.3, but it is a one-third speedup, well worth it if this is a critical loop—and, in general, if it isn’t critical, there’s no point in hand-tuning it. That’s why I haven’t bothered to try to optimize the non-inner-loop code in Listing 21.3; it’s only executed once per checksum, so it’s unlikely that a cycle or two saved there would make any real-world difference.
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</P>
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<P>Listing 21.3 could be made a bit faster yet with some loop unrolling, but that would make the code quite a bit more complex for relatively little return. Instead, why not make the code more complex and get a <I>big</I> return? Listing 21.4 does exactly that by loading one dword at a time to eliminate both the word prefix of Listing 21.1 and the multiple byte-sized accesses of Listing 21.3. An obvious drawback to this is the considerable complexity needed to ensure that the dword accesses are dword-aligned (remember that unaligned dword accesses cost three cycles each), and to handle buffer lengths that aren’t dword multiples. I’ve handled these problems by requiring that the buffer be dword-aligned and a dword multiple in length, which is of course not always the case in the real world. However, the point of these listings is to illustrate Pentium optimization—dword issues, being non-inner-loop stuff, are solvable details that aren’t germane to the main focus. In any case, the complexity and assumptions are well justified by the performance of this code: three cycles per loop, or 1.5 cycles per checksummed word, more than three times the speed of the original code. Again, note that the actual order in which the instructions are arranged is dictated by the various optimization hazards of the Pentium.</P><P><BR></P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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