112 lines
8.3 KiB
HTML
112 lines
8.3 KiB
HTML
<HTML>
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<META name=vsisbn content="1576101746">
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<META name=vstitle content="Michael Abrash's Graphics Programming Black Book, Special Edition">
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<META name=vsauthor content="Michael Abrash">
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<META name=vspublisher content="The Coriolis Group">
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<META name=vspubdate content="07/01/97">
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<META name=vscategory content="Web and Software Development: Game Development,Web and Software Development: Graphics and Multimedia Development">
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<TITLE>Michael Abrash's Graphics Programming Black Book Special Edition: Pentium Rules</TITLE>
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<!--ISBN=1576101746//-->
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<!--TITLE=Michael Abrash's Graphics Programming Black Book Special Edition//-->
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<!--AUTHOR=Michael Abrash//-->
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<TD><A HREF="20-02.html">Previous</A></TD>
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<P><BR></P>
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<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Lockstep Execution</FONT></H3>
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<P>You may wonder why anyone would bother breaking <B>ADD [MemVar],EAX</B> into three instructions, given that this instruction can go through either pipe with equal ease. The answer is that while the memory-accessing instructions other than <B>MOV, PUSH</B>, and <B>POP</B> listed in Table 20.1 (that is, <B>INC/DEC [<I>mem</I>], ADD/SUB/XOR/AND/OR/CMP/ADC/SBB <I>reg</I>,[<I>mem</I>]</B>, and <B>ADD/SUB/XOR/AND/OR/CMP/ADC/SBB [<I>mem</I>],<I>reg/immed</I></B>) can be paired, they do not provide the 100 percent overlap that we seek. If you look at Tables 20.1 and 20.2, you will see that instructions taking from 1 to 3 cycles can pair. However, any pair of instructions goes through the two pipes in lockstep. This means, for example, that if <B>ADD [EBX],EDX</B> is going through the U-pipe, and <B>INC EAX</B> is going through the V-pipe, the V-pipe will be idle for 2 of the 3 cycles that the U-pipe takes to execute its instruction, as shown in Figure 20.4. Out of the theoretical 6 cycles of work that can be done during this time, we actually get only 4 cycles of work, or 67 percent utilization. Even though these instructions pair, then, this sequence fails to make maximum use of the Pentium’s horsepower.</P>
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<P>The key here is that when two instructions pair, both execution units are tied up until both instructions have finished (which means at least for the amount of time required for the longer of the two to execute, plus possibly some extra cycles for pairable instructions that can’t fully overlap, as described below). The logical conclusion would seem to be that we should strive to pair instructions of the same lengths, but that is often not correct.</P>
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<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/20-04i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>The actual rule is that we should strive to pair one-cycle instructions (or, at most, two-cycle instructions, but not three-cycle instructions), which in turn leads to the corollary that we should, in general, use mostly one-cycle instructions when optimizing.</I></SMALL>
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</TABLE>
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<P><A NAME="Fig4"><!-- </A><A HREF="javascript:displayWindow('images/20-04.jpg',411,224 )"> --><IMG SRC="images/20-04.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/20-04.jpg',411,224)"> --><FONT COLOR="#000077"><B>Figure 20.4</B></FONT></A> <I>Lockstep execution and idle time in the V-pipe.</I>
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</P>
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<P>Here’s why. The Pentium is fully capable of handling instructions that use memory operands in either pipe, or, if necessary, in both pipes at once. Each pipe has its own write FIFO, which buffers the last few writes and takes care of writing the data out while the Pentium continues processing. The Pentium also has a write-back internal data cache, so data that is frequently changed doesn’t have to be written to external memory (which is much slower than the cache) very often. This combination means that unless you write large blocks of data at a high speed, the Pentium should be able to keep up with both pipes’ memory writes without stalling execution.
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</P>
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<P>The Pentium is also designed to satisfy both pipes’ needs for reading memory operands with little waiting. The data cache is constructed so that both pipes can read from the cache <I>on the same cycle</I>. This feat is accomplished by organizing the data cache as eight-banked memory, as shown in Figure 20.5, with each 32-byte cache line consisting of 8 dwords, 1 in each bank. The banks are independent of one another, so as long as the desired data is in the cache and the U- and V-pipes don’t try to read from the same bank on the same cycle, both pipes can read memory operands on the same cycle. (If there is a cache bank collision, the V-pipe instruction stalls for one cycle.)</P>
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<P>Normally, you won’t pay close attention to which of the eight dword banks your paired memory accesses fall in—that’s just too much work—but you might want to watch out for simultaneously read addresses that have the same values for address</P>
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<P><A NAME="Fig5"><!-- </A><A HREF="javascript:displayWindow('images/20-05.jpg',409,162 )"> --><IMG SRC="images/20-05.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/20-05.jpg',409,162)"> --><FONT COLOR="#000077"><B>Figure 20.5</B></FONT></A> <I>The Pentium’s eight bank data cache.</I>
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</P>
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<P>bits 2, 3, and 4 (fall in the same bank) in tight loops, and you should also avoid sequences like
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</P>
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<!-- CODE SNIP //-->
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<PRE>
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mov bl,[esi]
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mov bh,[esi+1]
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</PRE>
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<!-- END CODE SNIP //-->
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<P>because both operands will generally be in the same bank. An alternative is to place another instruction between the two instructions that access the same bank, as in this sequence:
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</P>
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<!-- CODE SNIP //-->
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<PRE>
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mov bl,[esi]
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mov edi,edx
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mov bh,[esi+1]
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</PRE>
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<!-- END CODE SNIP //-->
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<P>By the way, the reason a code sequence that takes two instructions to load a single word is attractive in a 32-bit segment is because it takes only one cycle when the two instructions can be paired with other instructions; by contrast, the obvious way of loading BX
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</P>
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<!-- CODE SNIP //-->
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<PRE>
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mov bx,[esi]
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</PRE>
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<!-- END CODE SNIP //-->
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<P>takes 1.5 to two cycles because the size prefix can’t pair, as described below. This is yet another example of how different Pentium optimization can be from everything we’ve learned about its predecessors.
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</P>
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<P>The problem with pairing non-single-cycle instructions arises when a pipe executes an instruction other than <B>MOV</B> that has an explicit memory operand. (I’ll call these <I>complex memory instructions</I>. They’re the only pairable instructions, other than branches, that take more than one cycle.) We’ve already seen that, because instructions go through the pipes in lockstep, if one pipe executes a complex memory instruction such as <B>ADD EAX,[EBX]</B> while the other pipe executes a single-cycle instruction, the pipe with the faster instruction will sit idle for part of the time, wasting cycles. You might think that if both pipes execute complex instructions of the same length, then neither would lie idle, but that turns out to not always be the case. Two two-cycle instructions (instructions with register destination operands) can indeed pair and execute in two cycles, so it’s okay to pair two instructions such as these:</P>
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<!-- CODE SNIP //-->
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<PRE>
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add esi,[SourceSkip] ;U-pipe cycles 1 and 2
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add edi,[DestinationSkip] ;V-pipe cycles 1 and 2
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</PRE>
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<!-- END CODE SNIP //-->
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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