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63-02.md

@@ -23,9 +23,11 @@ instructions, an FDIV and two integer instructions, executing at the
 same time. That's exactly what happens, for example, during the second
 cycle of this code:
 
-    FDIV ST(0),ST(1)
-    ADD  EAX,ECX
-    INC  EDX
+```nasm
+FDIV ST(0),ST(1)
+ADD  EAX,ECX
+INC  EDX
+```
 
 There's an important limitation, though; if the instruction stream
 following the FDIV reaches a FP instruction (or an IMUL), then that
@@ -38,8 +40,10 @@ exception: If the instruction that attempts to use the result is an FST
 to memory, there's an extra cycle lost, so it's 4 cycles from the start
 of an arithmetic instruction until an FST of that value can begin, so
 
-    FMUL ST(0),ST(1)
-    FST  [temp]
+```nasm
+FMUL ST(0),ST(1)
+FST  [temp]
+```
 
 takes 6 cycles in all.) Again, it's possible to execute integer-unit
 instructions during the 2 (or 3, for FST) cycles after one of these FP
@@ -57,10 +61,12 @@ to start on the next cycle, though: FADD, FSUB, and FMUL are pipelined,
 but FST and FDIV are not. (FLD executes in a single cycle, so pipelining
 is not an issue.) Thus, in the code sequence
 
-    FADD1
-    FSUB
-    FADD2
-    FMUL
+```nasm
+FADD1
+FSUB
+FADD2
+FMUL
+```
 
 FADD~1~ can start on cycle N, FSUB can start on cycle N+1, FADD~2~ can
 start on cycle N+2, and FMUL can start on cycle N+3. At the start of
@@ -77,29 +83,37 @@ throughput—the rate at which the FPU can start new instructions—is 1
 cycle. An exception is that the FPU is capable of starting an FMUL only
 every 2 cycles, so between these two instructions
 
-    FMUL ST(1),ST(0)
-    FMUL ST(2),ST(0)
+```nasm
+FMUL ST(1),ST(0)
+FMUL ST(2),ST(0)
+```
 
 there's a 1-cycle stall, and the following three instructions execute
 just as fast as the above pair:
 
-    FMUL ST(1),ST(0)
-    FLD  ST(4)
-    FMUL ST(0),ST(1)
+```nasm
+FMUL ST(1),ST(0)
+FLD  ST(4)
+FMUL ST(0),ST(1)
+```
 
 There's a caveat here, though: A FP instruction can't be issued until
 its operands are available. The FPU can reach a throughput of 1 cycle
 per instruction on this code
 
-    FADD ST(1),ST(0)
-    FLD  [temp]
-    FSUB ST(1),ST(0)
+```nasm
+FADD ST(1),ST(0)
+FLD  [temp]
+FSUB ST(1),ST(0)
+```
 
 because neither the FLD nor the FSUB needs the result from the FADD.
 Consider, however
 
-    FADD ST(0),ST(2)
-    FSUB ST(0),ST(1)
+```nasm
+FADD ST(0),ST(2)
+FSUB ST(0),ST(1)
+```
 
 where the ST(0) operand to FSUB is calculated by FADD. Here, FSUB can't
 start until FADD has completed, so there are 2 stall cycles between the
@@ -134,15 +148,17 @@ multiplications, without incurring any stalls, as shown in Listing 63.1.
 
 **Listing 63.1 L63-1.ASM**
 
-    ; use of fxch to allow addition of first two; products to start while third : multiplication finishes
-            fld     [vec0+0]        ;starts & ends on cycle 0
-            fmul    [vec1+0]        ;starts on cycle 1
-            fld     [vec0+4]        ;starts & ends on cycle 2
-            fmul    [vec1+4]        ;starts on cycle 3
-            fld     [vec0+8]        ;starts & ends on cycle 4
-            fmul    [vec1+8]        ;starts on cycle 5
-            fxch    st(1)           ;no cost
-            faddp   st(2),st(0)     ;starts on cycle 6
+```nasm
+; use of fxch to allow addition of first two; products to start while third : multiplication finishes
+        fld     [vec0+0]        ;starts & ends on cycle 0
+        fmul    [vec1+0]        ;starts on cycle 1
+        fld     [vec0+4]        ;starts & ends on cycle 2
+        fmul    [vec1+4]        ;starts on cycle 3
+        fld     [vec0+8]        ;starts & ends on cycle 4
+        fmul    [vec1+8]        ;starts on cycle 5
+        fxch    st(1)           ;no cost
+        faddp   st(2),st(0)     ;starts on cycle 6
+```
 
 ### The Dot Product {#Heading7}