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James Gregory 2013-12-31 11:38:48 +11:00
commit f658bfbb40
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20-02.md
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@ -40,43 +40,45 @@ waits until the first instruction is done, then executes in the U-pipe,
possibly pairing with the next instruction in line if all pairing
conditions are met.
MOV reg,reg (1 cycle)
mem,reg (1 cycle)
reg,mem (1 cycle)
reg,immediate (1 cycle)
mem,immediate (1 cycle)†
```nasm
MOV reg,reg (1 cycle)
mem,reg (1 cycle)
reg,mem (1 cycle)
reg,immediate (1 cycle)
mem,immediate (1 cycle)†
AND/OR/XOR/ADD/SUB reg,reg (1 cycle)
mem,reg (3 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (3 cycles)†
AND/OR/XOR/ADD/SUB reg,reg (1 cycle)
mem,reg (3 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (3 cycles)†
INC/DEC reg (1 cycle)
mem (3 cycles)
INC/DEC reg (1 cycle)
mem (3 cycles)
CMP reg,reg (1 cycle)
mem,reg (2 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (2 cycles)†
CMP reg,reg (1 cycle)
mem,reg (2 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (2 cycles)†
TEST reg,reg (1 cycle)
EAX,immediate (1 cycle)
TEST reg,reg (1 cycle)
EAX,immediate (1 cycle)
PUSH/POP reg (1 cycle)
immediate (1 cycle)
PUSH/POP reg (1 cycle)
immediate (1 cycle)
LEA reg,mem (1 cycle)
LEA reg,mem (1 cycle)
JCC near (1 cycle if predicted correctly;
5 cycles otherwise in V-pipe,
4 cycles otherwise in U-pipe)
JCC near (1 cycle if predicted correctly;
5 cycles otherwise in V-pipe,
4 cycles otherwise in U-pipe)
JMP/CALL near (1 cycle if predicted correctly;
3 cycles otherwise)
JMP/CALL near (1 cycle if predicted correctly;
3 cycles otherwise)
```
† Can't execute in V-pipe if address contains a displacement
† Can't execute in V-pipe if address contains a displacement
**Table 20.1 Instructions that can execute in the V-pipe.**
@ -100,41 +102,43 @@ each of 2 cycles, for 2\*0.5 = 1 cycle total execution time), as shown
in Figure 20.3—a full cycle *faster* than **PUSH [*mem*]**, which takes
2 cycles.
MOV reg,reg (1 cycle)
mem,reg (1 cycle)
reg,mem (1 cycle)
reg,immediate (1 cycle)
mem,immediate (1 cycle)†
```nasm
MOV reg,reg (1 cycle)
mem,reg (1 cycle)
reg,mem (1 cycle)
reg,immediate (1 cycle)
mem,immediate (1 cycle)†
AND/OR/XOR/ADD/SUB/ADC/SBB reg,reg (1 cycle)
mem,reg (3 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (3 cycles)†
AND/OR/XOR/ADD/SUB/ADC/SBB reg,reg (1 cycle)
mem,reg (3 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (3 cycles)†
INC/DEC reg (1 cycle)
mem (3 cycles)
INC/DEC reg (1 cycle)
mem (3 cycles)
CMP reg,reg (1 cycle)
mem,reg (2 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (2 cycles)†
CMP reg,reg (1 cycle)
mem,reg (2 cycles)
reg,mem (2 cycles)
reg,immediate (1 cycle)
mem,immediate (2 cycles)†
TEST reg,reg (1 cycle)
EAX,immediate (1 cycle)
TEST reg,reg (1 cycle)
EAX,immediate (1 cycle)
PUSH/POP reg (1 cycle)
immediate (1 cycle)
PUSH/POP reg (1 cycle)
immediate (1 cycle)
LEA reg,mem (1 cycle)
LEA reg,mem (1 cycle)
SHL/SHR/SAL/SAR reg,immediate (1 cycle)††
SHL/SHR/SAL/SAR reg,immediate (1 cycle)††
ROL/ROR/RCL/RCR reg,1 (1 cycle)
ROL/ROR/RCL/RCR reg,1 (1 cycle)
```
† Can't pair if address contains a displacement
†† Includes shift-by-1 forms of instructions
† Can't pair if address contains a displacement\
†† Includes shift-by-1 forms of instructions
**Table 20.2 Instructions that, when executed in the U-pipe, allow
V-pipe-executable instructions to execute simultaneously (pair) in the
@ -155,25 +159,33 @@ One downside of this "RISCification" (turning complex instructions into
simple, RISC-like ones) of Pentium-optimized code is that it makes for
substantially larger code. For example,
push dword ptr [esi]
```nasm
push dword ptr [esi]
```
is one byte smaller than this sequence:
mov eax,[esi]
push eax
```nasm
mov eax,[esi]
push eax
```
![**Figure 20.3**  *Pushing a value from memory effectively in one
cycle.*](images/20-03.jpg)
A more telling example is the following
add [MemVar],eax
```nasm
add [MemVar],eax
```
versus the equivalent:
mov edx,[MemVar]
add edx,eax
mov [MemVar],edx
```nasm
mov edx,[MemVar]
add edx,eax
mov [MemVar],edx
```
The single complex instruction takes 3 cycles and is 6 bytes long; with
proper sequencing, interleaving the simple instructions with other