Use backtick code blocks for syntax highlighting

04-03.md

@@ -16,12 +16,16 @@ strive to use byte-sized memory variables whenever possible. That does
 manipulate a word-sized memory variable in preference to 1 word-sized
 memory access, as, for instance,
 
-    mov  dl,byte ptr [MemVar]
-    mov  dh,byte ptr [MemVar+1]
+```nasm
+mov  dl,byte ptr [MemVar]
+mov  dh,byte ptr [MemVar+1]
+```
 
 versus:
 
-    mov  dx,word ptr [MemVar]
+```nasm
+mov  dx,word ptr [MemVar]
+```
 
 Recall that every access to a memory byte takes at least 4 cycles; that
 limitation is built right into the 8088. The 8088 is also built so that
@@ -48,25 +52,29 @@ the second byte of each word.
 
 **LISTING 4.3 LST4-3.ASM**
 
-    ; Measures the performance of reading 1,000 words
-    ; from memory with 1,000 word-sized accesses.
-    ;
-         sub  si,si
-         mov  cx,1000
-         call ZTimerOn
-         rep  lodsw
-         call ZTimerOff
+```nasm
+; Measures the performance of reading 1,000 words
+; from memory with 1,000 word-sized accesses.
+;
+     sub  si,si
+     mov  cx,1000
+     call ZTimerOn
+     rep  lodsw
+     call ZTimerOff
+```
 
 **LISTING 4.4 LST4-4.ASM**
 
-    ; Measures the performance of reading 1000 words
-    ; from memory with 2,000 byte-sized accesses.
-    ;
-         sub  si,si
-         mov  cx,2000
-         call ZTimerOn
-         rep  lodsb
-         call ZTimerOff
+```nasm
+; Measures the performance of reading 1000 words
+; from memory with 2,000 byte-sized accesses.
+;
+     sub  si,si
+     mov  cx,2000
+     call ZTimerOn
+     rep  lodsb
+     call ZTimerOff
+```
 
 In short, if you must perform a 16-bit memory access, let the 8088 break
 the access into two byte-sized accesses for you. The 8088 is more
@@ -142,17 +150,21 @@ What makes the prefetch queue cycle-eater tricky is that it's
 undocumented and unpredictable. That is, with a word-sized memory
 access, such as
 
-    mov  [bx],ax
+```nasm
+mov  [bx],ax
+```
 
 it's well-documented that an extra 4 cycles will always be required to
 write the upper byte of AX to memory. Not so with the prefetch queue
 cycle-eater lurking nearby. For instance, the instructions
 
-    shr  ax,1
-    shr  ax,1
-    shr  ax,1
-    shr  ax,1
-    shr  ax,1
+```nasm
+shr  ax,1
+shr  ax,1
+shr  ax,1
+shr  ax,1
+shr  ax,1
+```
 
 should execute in 10 cycles, since each **SHR** takes 2 cycles to
 execute, according to Intel's specifications. Those specifications