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[Previous](04-06.html) [Table of Contents](index.html) [Next](04-08.html)
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#### The Impact of DRAM Refresh {#Heading17}
Let's look at examples from opposite ends of the spectrum in terms of
@ -143,12 +139,4 @@ Wait states are cycles during which a bus access by the CPU to a device
on the PC's bus is temporarily halted by that device while the device
gets ready to complete the read or write. Wait states are well and truly
the lowest level of code performance. Everything we have discussed (and
will discuss)—even DMA accesses—can be affected by wait states.
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[Previous](04-06.html) [Table of Contents](index.html) [Next](04-08.html)
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* * * * *
Graphics Programming Black Book © 2001 Michael Abrash
will discuss)—even DMA accesses—can be affected by wait states.