Remove colour attributes from body and strip most of the font tags out
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James Gregory
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362 changed files with 1632 additions and 1706 deletions
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63-02.html
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63-02.html
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@ -24,7 +24,7 @@
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<!--CHAPTER=63//-->
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<!--PAGES=1168-1170//-->
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<!--UNASSIGNED1//-->
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<!--UNASSIGNED2//--></HEAD><BODY LINK=#0000FF ALINK=#000099 VLINK=#0000FF BGCOLOR=#FFFFFF>
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<!--UNASSIGNED2//--></HEAD><body>
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<CENTER>
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<TABLE BORDER>
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@ -55,7 +55,7 @@ FST [temp]
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<!-- END CODE SNIP //-->
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<P>takes 6 cycles in all.) Again, it’s possible to execute integer-unit instructions during the 2 (or 3, for FST) cycles after one of these FP instructions starts. There’s a more exciting possibility here, though: Given properly structured code, the FPU is capable of averaging 1 cycle per FADD, FSUB, or FMUL. The secret is pipelining.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">Pipelining, Latency, and Throughput</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading5"></A>Pipelining, Latency, and Throughput</H4>
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<P>The Pentium’s FPU is the first pipelined x86 FPU. <I>Pipelining</I> means that the FPU is capable of starting an instruction every cycle, and can simultaneously handle several instructions in various stages of completion. Only certain x86 FP instructions allow another instruction to start on the next cycle, though: FADD, FSUB, and FMUL are pipelined, but FST and FDIV are not. (FLD executes in a single cycle, so pipelining is not an issue.) Thus, in the code sequence</P>
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<!-- CODE SNIP //-->
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<PRE>
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@ -100,7 +100,7 @@ FSUB ST(0),ST(1)
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<!-- END CODE SNIP //-->
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<P>where the ST(0) operand to FSUB is calculated by FADD. Here, FSUB can’t start until FADD has completed, so there are 2 stall cycles between the two instructions. When dependencies like this occur, the FPU runs at latency rather than throughput speeds, and performance can drop by as much as two-thirds.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">FXCH</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading6"></A>FXCH</H4>
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<P>One piece of the puzzle is still missing. Clearly, to get maximum throughput, we need to interleave FP instructions, such that at any one time ideally three instructions are in the pipeline at once. Further, these instructions must not depend on one another for operands. But ST(0) must always be one of the operands; worse, FLD can only push into ST(0), and FST can only store from ST(0). How, then, can we keep three independent instructions going?
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</P>
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<P>The easy answer would be for Intel to change the FP registers from a stack to a set of independent registers. Since they couldn’t do that, thanks to compatibility issues, they did the next best thing: They made the FXCH instruction, which swaps ST(0) and any other FP register, virtually free. In general, if FXCH is both preceded and followed by FP instructions, then it takes <I>no</I> cycles to execute. (Application Note 500, “Optimizations for Intel’s 32-bit Processors,” February 1994, available from <A HREF="http://www.intel.com">http://www.intel.com</A>, describes all .the conditions under which FXCH is free.) This allows you to move the target of a pending operation from ST(0) to another register, at the same time bringing another register into ST(0) where it can be used, all at no cost. So, for example, we can start three multiplications, then use FXCH to swap back to start adding the results of the first two multiplications, without incurring any stalls, as shown in Listing 63.1.</P>
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@ -118,7 +118,7 @@ FSUB ST(0),ST(1)
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faddp st(2),st(0) ;starts on cycle 6
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</PRE>
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<!-- END CODE //-->
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<H3><A NAME="Heading7"></A><FONT COLOR="#000077">The Dot Product</FONT></H3>
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<H3><A NAME="Heading7"></A>The Dot Product</H3>
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<P>Now we’re ready to look at fast FP for common 3-D operations; we’ll start by looking at how to speed up the dot product. As discussed in Chapter 30, the dot product is heavily used in 3-D to calculate cosines and to project points along vectors. The dot product is calculated as d = u<SUB>1</SUB>v<SUB>1</SUB> + u<SUB>2</SUB>v<SUB>2</SUB> + u<SUB>3</SUB>v<SUB>3</SUB>; with three loads, three multiplies, two adds, and a store, the theoretical minimum time for this calculation is 10 cycles.</P>
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<P>Listing 63.2 shows a straightforward dot product implementation. This version loses 7 cycles to stalls. Listing 63.3 cuts the loss to 5 cycles by doing all three FMULs first, then using FXCH to set the third FXCH aside to complete while the results of the first two FMULs, which have completed, are added. Listing 43.3 still loses 50 percent to stalls, but unless some other code is available to be interleaved with the dot product code, that’s all we can do to speed things up. Fortunately, dot products are often used in contexts where there’s plenty of interleaving potential, as we’ll see when we discuss transformation.</P><P><BR></P>
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<CENTER>
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@ -133,7 +133,7 @@ FSUB ST(0),ST(1)
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<hr width="90%" size="1" noshade>
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<div align="center">
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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</div>
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<!-- all of the reference materials (books) have the footer and subfoot reveresed -->
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<!-- reference_subfoot = footer -->
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