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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 27<BR>Yet Another VGA Write Mode
</FONT></H2>
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Write Mode 2, Chunky Bitmaps,and Text-Graphics Coexistence</FONT></H3>
<H2><A NAME="Heading1"></A>Chapter 27<BR>Yet Another VGA Write Mode</H2>
<H3><A NAME="Heading2"></A>Write Mode 2, Chunky Bitmaps,and Text-Graphics Coexistence</H3>
<P>In the last chapter, we learned about the markedly peculiar write mode 3 of the VGA, after having spent three chapters learning the ins and outs of the VGA&rsquo;s data path in write mode 0, touching on write mode 1 as well in Chapter 23. In all, the VGA supports four write modes&mdash;write modes 0, 1, 2, and 3&mdash;and read modes 0 and 1 as well. Which leaves two burning questions: What is write mode 2, and how the heck do you <I>read</I> VGA memory?</P>
<P>Write mode 2 is a bit unusual but not really hard to understand, particularly if you followed the description of set/reset in Chapter 25. Reading VGA memory, on the other hand, can be stranger than you could ever imagine.</P>
<P>Let&rsquo;s start with the easy stuff, write mode 2, and save the read modes for the next chapter.</P>
<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Write Mode 2 and Set/Reset</FONT></H3>
<H3><A NAME="Heading3"></A>Write Mode 2 and Set/Reset</H3>
<P>Remember how set/reset works? Good, because that&rsquo;s pretty much how write mode 2 works. (You <I>don&rsquo;t</I> remember? Well, I&rsquo;ll provide a brief refresher, but I suggest that you go back through Chapters 23 through 25 and come up to speed on the VGA.)</P>
<P>Recall that the set/reset circuitry for each of the four planes affects the byte written by the CPU in one of three ways: By replacing the CPU byte with 0, by replacing it with 0FFH, or by leaving it unchanged. The nature of the transformation for each plane is controlled by two bits. The enable set/reset bit for a given plane selects whether the CPU byte is replaced or not, and the set/reset bit for that plane selects the value with which the CPU byte is replaced if the enable set/reset bit is 1. The net effect of set/reset is to independently force any, none, or all planes to either of all ones or all zeros on CPU writes. As we discussed in Chapter 25, this is a convenient way to force a specific color to appear no matter what color the pixels being overwritten are. Set/reset also allows the CPU to control the contents of some planes while the set/reset circuitry controls the contents of other planes.</P>
<P>Write mode 2 is basically a set/reset-type mode with enable set/reset always on for all planes and the set/reset data coming directly from the byte written by the CPU. Put another way, the lower four bits written by the CPU are written across the four planes, thereby becoming a color value. Put yet another way, bit 0 of the CPU byte is expanded to a byte and sent to the plane 0 ALU (if bit 0 is 0, a 0 byte is the CPU-side input to the plane 0 ALU, while if bit 0 is 1, a 0FFH byte is the CPU-side input); likewise, bit 1 of the CPU byte is expanded to a byte for plane 1, bit 2 is expanded for plane 2, and bit 3 is expanded for plane 3.</P>
<P>It&rsquo;s possible that you understand write mode 2 thoroughly at this point; nonetheless, I suspect that some additional explanation of an admittedly non-obvious mode wouldn&rsquo;t hurt. Let&rsquo;s follow the CPU byte through the VGA in write mode 2, step by step.</P>
<H4 ALIGN="LEFT"><A NAME="Heading4"></A><FONT COLOR="#000077">A Byte&rsquo;s Progress in Write Mode 2</FONT></H4>
<H4 ALIGN="LEFT"><A NAME="Heading4"></A>A Byte&rsquo;s Progress in Write Mode 2</H4>
<P>Figure 27.1 shows the write mode 2 data path. The CPU byte comes into the VGA and is split into four separate bits, one for each plane. Bits 7-4 of the CPU byte vanish into the bit bucket, never to be heard from again. Speculation long held that those 4 unused bits indicated that IBM would someday come out with an 8-plane adapter that supported 256 colors. When IBM did finally come out with a 256-color mode (mode 13H of the VGA), it turned out not to be planar at all, and the upper nibble of the CPU byte remains unused in write mode 2 to this day.
</P>
<P>The bit of the CPU byte sent to each plane is expanded to a 0 or 0FFH byte, depending on whether the bit is 0 or 1, respectively. The byte for each plane then becomes the CPU-side input to the respective plane&rsquo;s ALU. From this point on, the write mode 2 data path is identical to the write mode 0 data path. As discussed in earlier articles, the latch byte for each plane is the other ALU input, and the ALU either ANDs, ORs, or XORs the two bytes together or simply passes the CPU-side byte through. The byte generated by each plane&rsquo;s ALU then goes through the bit mask circuitry, which selects on a bit-by-bit basis between the ALU byte and the latch byte. Finally, the byte from the bit mask circuitry for each plane is written to that plane if the corresponding bit in the Map Mask register is set to 1.</P>
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/27-01.jpg',409,401 )"> --><IMG SRC="images/27-01.jpg"><BR><!-- </A>
<BR><A HREF="javascript:displayWindow('images/27-01.jpg',409,401)"> --><FONT COLOR="#000077"><B>Figure 27.1</B></FONT></A>&nbsp;&nbsp;<I>VGA data flow in write mode 2.</I>
<BR><A HREF="javascript:displayWindow('images/27-01.jpg',409,401)"> --><B>Figure 27.1</B></A>&nbsp;&nbsp;<I>VGA data flow in write mode 2.</I>
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<TD WIDTH="5%" VALIGN="TOP"><IMG SRC="images/i.jpg"><TD WIDTH="95%"><SMALL><I>It&rsquo;s worth noting two differences between write mode 2 and write mode 0, the standard write mode of the VGA. First, rotation of the CPU data byte does not take place in write mode 2. Second, the Set/Reset and Enable Set/Reset registers have no effect in write mode 2.</I></SMALL>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book &copy; 2001 Michael Abrash</font>
Graphics Programming Black Book &copy; 2001 Michael Abrash
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