Remove colour attributes from body and strip most of the font tags out
This commit is contained in:
James Gregory
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7e957c0bb4
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362 changed files with 1632 additions and 1706 deletions
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01-01.html
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<P><BR></P>
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<H2 ALIGN="CENTER"><FONT COLOR="#000077"><I>Part I
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</I></FONT></H2>
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 1<BR>The Best Optimizer Is between Your Ears
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</FONT></H2>
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<H3><A NAME="Heading2"></A><FONT COLOR="#000077">The Human Element of Code Optimization</FONT></H3>
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<H2 ALIGN="CENTER"><I>Part I</I></H2>
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<H2><A NAME="Heading1"></A>Chapter 1<BR>The Best Optimizer Is between Your Ears</H2>
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<H3><A NAME="Heading2"></A>The Human Element of Code Optimization</H3>
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<P>This book is devoted to a topic near and dear to my heart: writing software that pushes PCs to the limit. Given run-of-the-mill software, PCs run like the 97-pound-weakling minicomputers they are. Give them the proper care, however, and those ugly boxes are capable of miracles. The key is this: Only on microcomputers do you have the run of the whole machine, without layers of operating systems, drivers, and the like getting in the way. You can do <I>anything</I> you want, and you can understand everything that’s going on, if you so wish.</P>
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<P>As we’ll see shortly, you should indeed so wish.</P>
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<P>Is performance still an issue in this era of cheap 486 computers and super-fast Pentium computers? You bet. How many programs that <I>you</I> use really run so fast that you wouldn’t be happier if they ran faster? We’re so used to slow software that when a compile-and-link sequence that took two minutes on a PC takes just ten seconds on a 486 computer, we’re ecstatic—when in truth we should be settling for nothing less than instantaneous response.</P>
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<P>Impossible, you say? Not with the proper design, including incremental compilation and linking, use of extended and/or expanded memory, and well-crafted code. PCs can do just about anything you can imagine (with a few obvious exceptions, such as applications involving super-computer-class number-crunching) if you believe that it can be done, if you understand the computer inside and out, and if you’re willing to think past the obvious solution to unconventional but potentially more fruitful approaches.</P>
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<P>My point is simply this: PCs can work wonders. It’s not easy coaxing them into doing that, but it’s rewarding—and it’s sure as heck fun. In this book, we’re going to work some of those wonders, starting...</P>
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<P>...now.</P>
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<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Understanding High Performance</FONT></H3>
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<H3><A NAME="Heading3"></A>Understanding High Performance</H3>
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<P>Before we can create high-performance code, we must understand what high performance is. The objective (not always attained) in creating high-performance software is to make the software able to carry out its appointed tasks so rapidly that it responds instantaneously, as far as the user is concerned. In other words, high-performance code should ideally run so fast that any further improvement in the code would be pointless.
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</P>
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<P>Notice that the above definition most emphatically does <I>not</I> say anything about making the software as fast as possible. It also does not say anything about using assembly language, or an optimizing compiler, or, for that matter, a compiler at all. It also doesn’t say anything about how the code was designed and written. What it does say is that high-performance code shouldn’t get in the user’s way—and that’s <I>all</I>.</P>
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</TABLE>
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<P>“What’s a fast slow program?” you ask. That’s a good question, and a brief (true) story is perhaps the best answer.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading4"></A><FONT COLOR="#000077">When Fast Isn’t Fast</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading4"></A>When Fast Isn’t Fast</H4>
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<P>In the early 1970s, as the first hand-held calculators were hitting the market, I knew a fellow named Irwin. He was a good student, and was planning to be an engineer. Being an engineer back then meant knowing how to use a slide rule, and Irwin could jockey a slipstick with the best of them. In fact, he was so good that he challenged a fellow with a calculator to a duel—and won, becoming a local legend in the process.
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</P>
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<P>When you get right down to it, though, Irwin was spitting into the wind. In a few short years his hard-earned slipstick skills would be worthless, and the entire discipline would be essentially wiped from the face of the earth. What’s more, anyone with half a brain could see that changeover coming. Irwin had basically wasted the considerable effort and time he had spent optimizing his soon-to-be-obsolete skills.</P>
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<hr width="90%" size="1" noshade>
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<div align="center">
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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</div>
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<P><BR></P>
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<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Rules for Building High-Performance Code</FONT></H3>
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<H3><A NAME="Heading5"></A>Rules for Building High-Performance Code</H3>
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<P>We’ve got the following rules for creating high-performance software:
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<P>Making rules is easy; the hard part is figuring out how to apply them in the real world. For my money, examining some actual working code is always a good way to get a handle on programming concepts, so let’s look at some of the performance rules in action.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">Know Where You’re Going</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading6"></A>Know Where You’re Going</H4>
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<P>If we’re going to create high-performance code, first we have to know what that code is going to do. As an example, let’s write a program that generates a 16-bit checksum of the bytes in a file. In other words, the program will add each byte in a specified file in turn into a 16-bit value. This checksum value might be used to make sure that a file hasn’t been corrupted, as might occur during transmission over a modem or if a Trojan horse virus rears its ugly head. We’re not going to do anything with the checksum value other than print it out, however; right now we’re only interested in generating that checksum value as rapidly as possible.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Make a Big Map</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Make a Big Map</H4>
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<P>How are we going to generate a checksum value for a specified file? The logical approach is to get the file name, open the file, read the bytes out of the file, add them together, and print the result. Most of those actions are straightforward; the only tricky part lies in reading the bytes and adding them together.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading8"></A><FONT COLOR="#000077">Make Lots of Little Maps</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading8"></A>Make Lots of Little Maps</H4>
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<P>Actually, we’re only going to make one little map, because we only have one program section that requires much thought—the section that reads the bytes and adds them up. What’s the best way to do this?
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<P>It would be convenient to load the entire file into memory and then sum the bytes in one loop. Unfortunately, there’s no guarantee that any particular file will fit in the available memory; in fact, it’s a sure thing that many files <I>won’t</I> fit into memory, so that approach is out.</P>
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<hr width="90%" size="1" noshade>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<P>The lesson is clear: Optimization makes code faster, but without proper design, optimization just creates fast slow code.
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</P>
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<P>Well, then, how are we going to improve our design? Before we can do that, we have to understand what’s wrong with the current design.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">Know the Territory</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading9"></A>Know the Territory</H4>
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<P>Just why is Listing 1.1 so slow? In a word: overhead. The C library implements the <B>read()</B> function by calling DOS to read the desired number of bytes. (I figured this out by watching the code execute with a debugger, but you can buy library source code from both Microsoft and Borland.) That means that Listing 1.1 (and Listing 1.3 as well) executes one DOS function per byte processed—and DOS functions, especially this one, come with a lot of overhead.</P>
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<P>For starters, DOS functions are invoked with interrupts, and interrupts are among the slowest instructions of the x86 family CPUs. Then, DOS has to set up internally and branch to the desired function, expending more cycles in the process. Finally, DOS has to search its own buffers to see if the desired byte has already been read, read it from the disk if not, store the byte in the specified location, and return. All of that takes a <I>long</I> time—far, far longer than the rest of the main loop in Listing 1.1. In short, Listing 1.1 spends virtually all of its time executing <B>read(),</B> and most of that time is spent somewhere down in DOS.</P>
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<P>You can verify this for yourself by watching the code with a debugger or using a code profiler, but take my word for it: There’s a great deal of overhead to DOS calls, and that’s what’s draining the life out of Listing 1.1.</P>
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<hr width="90%" size="1" noshade>
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<div align="center">
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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</PRE>
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<!-- END CODE //-->
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">Know When It Matters</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A>Know When It Matters</H4>
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<P>The last section contained a particularly interesting phrase: <I>the time-critical portions of your code</I>. Time-critical portions of your code are those portions in which the speed of the code makes a significant difference in the overall performance of your program—and by “significant,” I don’t mean that it makes the code 100 percent faster, or 200 percent, or any particular amount at all, but rather that it makes the program more responsive and/or usable <I>from the user’s perspective</I>.</P>
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<P>Don’t waste time optimizing non-time-critical code: set-up code, initialization code, and the like. Spend your time improving the performance of the code inside heavily-used loops and in the portions of your programs that directly affect response time. Notice, for example, that I haven’t bothered to implement a version of the checksum program entirely in assembly; Listings 1.2 and 1.6 call assembly subroutines that handle the time-critical operations, but C is still used for checking command-line parameters, operning files, printing, and the like.</P>
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<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP"><IMG SRC="images/i.jpg"><TD WIDTH="95%"><SMALL><I>If you were to implement any of the listings in this chapter entirely in hand-optimized assembly, I suppose you might get a performance improvement of a few percent—but I rather doubt you’d get even that much, and you’d sure as heck spend an awful lot of time for whatever meager improvement does result. Let C do what it does well, and use assembly only when it makes a perceptible difference.</I></SMALL>
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</TABLE>
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<P>Besides, we don’t want to optimize until the design is refined to our satisfaction, and that won’t be the case until we’ve thought about other approaches.
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading11"></A><FONT COLOR="#000077">Always Consider the Alternatives</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading11"></A>Always Consider the Alternatives</H4>
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<P>Listing 1.4 is good, but let’s see if there are other—perhaps less obvious—ways to get the same results faster. Let’s start by considering why Listing 1.4 is so much better than Listing 1.1. Like <B>read()</B>, <B>getc()</B> calls DOS to read from the file; the speed improvement of Listing 1.4 over Listing 1.1 occurs because <B>getc()</B> eads many bytes at once via DOS, then manages those bytes for us. That’s faster than reading them one at a time using <B>read()</B>—but there’s no reason to think that it’s faster than having our program read and manage blocks itself. Easier, yes, but not faster.</P>
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<P>Consider this: Every invocation of <B>getc()</B> involves pushing a parameter, executing a call to the C library function, getting the parameter (in the C library code), looking up information about the desired stream, unbuffering the next byte from the stream, and returning to the calling code. That takes a considerable amount of time, especially by contrast with simply maintaining a pointer to a buffer and whizzing through the data in the buffer inside a single loop.</P>
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<P>There are four reasons that many programmers would give for not trying to improve on Listing 1.4:</P>
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<hr width="90%" size="1" noshade>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<P>That brings us to the fourth reason: avoiding an internal-buffered implementation like Listing 1.5 because of the difficulty of coding such an approach. True, it is easier to let a C library function do the work, but it’s not all that hard to do the buffering internally. The key is the concept of handling data in <I>restartable blocks;</I> that is, reading a chunk of data, operating on the data until it runs out, suspending the operation while more data is read in, and then continuing as though nothing had happened.</P>
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<P>In Listing 1.5 the restartable block implementation is pretty simple because checksumming works with one byte at a time, forgetting about each byte immediately after adding it into the total. Listing 1.5 reads in a block of bytes from the file, checksums the bytes in the block, and gets another block, repeating the process until the entire file has been processed. In Chapter 5, we’ll see a more complex restartable block implementation, involving searching for text strings.</P>
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<P>At any rate, Listing 1.5 isn’t much more complicated than Listing 1.4—and it’s a <I>lot</I> faster. Always consider the alternatives; a bit of clever thinking and program redesign can go a long way.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading12"></A><FONT COLOR="#000077">Know How to Turn On the Juice</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading12"></A>Know How to Turn On the Juice</H4>
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<P>I have said time and again that optimization is pointless until the design is settled. When that time comes, however, optimization can indeed make a significant difference. Table 1.1 indicates that the optimized version of Listing 1.5 produced by Microsoft C outperforms an unoptimized version of the same code by more than 60 percent. What’s more, a mostly-assembly version of Listing 1.5, shown in Listings 1.6 and 1.7, outperforms even the best-optimized C version of List1.5 by 26 percent. These are considerable improvements, well worth pursuing—once the design has been maxed out.
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</P>
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<P><B>LISTING 1.6 L1-6.C</B></P>
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Graphics Programming Black Book © 2001 Michael Abrash
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<P>All this is basically a way of saying: Know where you’re going, know the territory, and know when it matters.
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</P>
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<H3><A NAME="Heading13"></A><FONT COLOR="#000077">Where We’ve Been, What We’ve Seen</FONT></H3>
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<H3><A NAME="Heading13"></A>Where We’ve Been, What We’ve Seen</H3>
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<P>What have we learned? Don’t let other people’s code—even DOS—do the work for you when speed matters, at least not without knowing what that code does and how well it performs.
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</P>
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<P>Optimization only matters after you’ve done your part on the program design end. Consider the ratios on the vertical axis of Table 1.1, which show that optimization is almost totally wasted in the checksumming application without an efficient design. Optimization is no panacea. Table 1.1 shows a two-times improvement from optimization—and a 50-times-plus improvement from redesign. The longstanding debate about which C compiler optimizes code best doesn’t matter quite so much in light of Table 1.1, does it? Your organic optimizer matters much more than your compiler’s optimizer, and there’s always assembly for those usually small sections of code where performance really matters.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading14"></A><FONT COLOR="#000077">Where We’re Going</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading14"></A>Where We’re Going</H4>
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<P>This chapter has presented a quick step-by-step overview of the design process. I’m not claiming that this is the only way to create high-performance code; it’s just an approach that works for me. Create code however you want, but never forget that design matters more than detailed optimization. Never stop looking for inventive ways to boost performance—and never waste time speeding up code that doesn’t need to be sped up.
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<P>I’m going to focus on specific ways to create high-performance code from now on. In Chapter 5, we’ll continue to look at restartable blocks and internal buffering, in the form of a program that searches files for text strings.</P><P><BR></P>
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Graphics Programming Black Book © 2001 Michael Abrash
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 2<BR>A World Apart
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<H3><A NAME="Heading2"></A><FONT COLOR="#000077">The Unique Nature of Assembly Language Optimization</FONT></H3>
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<H2><A NAME="Heading1"></A>Chapter 2<BR>A World Apart</H2>
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<H3><A NAME="Heading2"></A>The Unique Nature of Assembly Language Optimization</H3>
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<P>As I showed in the previous chapter, optimization is by no means always a matter of “dropping into assembly.” In fact, in performance tuning high-level language code, assembly should be used rarely, and then only after you’ve made sure a badly chosen or clumsily implemented algorithm isn’t eating you alive. Certainly if you use assembly at all, make absolutely sure you use it <I>right</I>. The potential of assembly code to run <I>slowly</I> is poorly understood by a lot of people, but that potential is great, especially in the hands of the ignorant.</P>
|
||||
<P>Truly great optimization, however, happens <I>only</I> at the assembly level, and it happens in response to a set of dynamics that is totally different from that governing C/C<SMALL>++</SMALL> or Pascal optimization. I’ll be speaking of assembly-level optimization time and again in this book, but when I do, I think it will be helpful if you have a grasp of those assembly specific dynamics.</P>
|
||||
<P>As usual, the best way to wade in is to present a real-world example.</P>
|
||||
<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Instructions: The Individual versus the Collective</FONT></H3>
|
||||
<H3><A NAME="Heading3"></A>Instructions: The Individual versus the Collective</H3>
|
||||
<P>Some time ago, I was asked to work over a critical assembly subroutine in order to make it run as fast as possible. The task of the subroutine was to construct a nibble out of four bits read from different bytes, rotating and combining the bits so that they ultimately ended up neatly aligned in bits 3-0 of a single byte. (In case you’re curious, the object was to construct a 16-color pixel from bits scattered over 4 bytes.) I examined the subroutine line by line, saving a cycle here and a cycle there, until the code truly seemed to be optimized. When I was done, the key part of the code looked something like this:
|
||||
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|
||||
<!-- CODE SNIP //-->
|
||||
|
|
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|
|||
<!-- END CODE //-->
|
||||
<P>This moved the costly multibit rotation out of the loop so that it was performed just once, rather than four times. While the code may not look much different from the original, and in fact still contains exactly the same number of instructions, the performance of the entire subroutine improved by about 10 percent from just this one change. (Incidentally, that wasn’t the end of the optimization; I eliminated the <B>DEC</B> and <B>JNJ</B> instructions by expanding the four iterations of the loop—but that’s a tale for another chapter.)</P>
|
||||
<P>The point is this: To write truly superior assembly programs, you need to know what the various instructions do and which instructions execute fastest...and more. You must also learn to look at your programming problems from a variety of perspectives so that you can put those fast instructions to work in the most effective ways.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">Assembly Is Fundamentally Different</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>Assembly Is Fundamentally Different</H3>
|
||||
<P>Is it really so hard as all that to write good assembly code for the PC? Yes! Thanks to the decidedly quirky nature of the x86 family CPUs, assembly language differs fundamentally from other languages, and is undeniably harder to work with. On the other hand, the potential of assembly code is much greater than that of other languages, as well.
|
||||
</P>
|
||||
<P>To understand why this is so, consider how a program gets written. A programmer examines the requirements of an application, designs a solution at some level of abstraction, and then makes that design come alive in a code implementation. If not handled properly, the transformation that takes place between conception and implementation can reduce performance tremendously; for example, a programmer who implements a routine to search a list of 100,000 sorted items with a linear rather than binary search will end up with a disappointingly slow program.</P><P><BR></P>
|
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<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">Transformation Inefficiencies</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>Transformation Inefficiencies</H4>
|
||||
<P>No matter how well an implementation is derived from the corresponding design, however, high-level languages like C/C<SMALL>++</SMALL> and Pascal inevitably introduce additional transformation inefficiencies, as shown in Figure 2.1.</P>
|
||||
<P>The process of turning a design into executable code by way of a high-level language involves two transformations: one performed by the programmer to generate source code, and another performed by the compiler to turn source code into machine language instructions. Consequently, the machine language code generated by compilers is usually less than optimal given the requirements of the original design.</P>
|
||||
<P>High-level languages provide artificial environments that lend themselves relatively well to human programming skills, in order to ease the transition from design to implementation. The price for this ease of implementation is a considerable loss of efficiency in transforming source code into machine language. This is particularly true given that the x86 family in real and 16-bit protected mode, with its specialized memory-addressing instructions and segmented memory architecture, does not lend itself particularly well to compiler design. Even the 32-bit mode of the 386 and its successors, with their more powerful addressing modes, offer fewer registers than compilers would like.</P>
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<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/02-01.jpg',417,202 )"> --><IMG SRC="images/02-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/02-01.jpg',417,202)"> --><FONT COLOR="#000077"><B>Figure 2.1</B></FONT></A> <I>The high-level language transformation inefficiencies.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/02-01.jpg',417,202)"> --><B>Figure 2.1</B></A> <I>The high-level language transformation inefficiencies.</I>
|
||||
</P>
|
||||
<P>Assembly, on the other hand, is simply a human-oriented representation of machine language. As a result, assembly provides a difficult programming environment—the bare hardware and systems software of the computer—<I>but properly constructed assembly programs suffer no transformation loss</I>, as shown in Figure 2.2.</P>
|
||||
<P>Only one transformation is required when creating an assembler program, and that single transformation is completely under the programmer’s control. Assemblers perform no transformation from source code to machine language; instead, they merely map assembler instructions to machine language instructions on a one-to-one basis. As a result, the programmer is able to produce machine language code that’s precisely tailored to the needs of each task a given application requires.</P>
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<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/02-02.jpg',414,201 )"> --><IMG SRC="images/02-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/02-02.jpg',414,201)"> --><FONT COLOR="#000077"><B>Figure 2.2</B></FONT></A> <I>Properly constructed assembly programs suffer no transformation loss.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/02-02.jpg',414,201)"> --><B>Figure 2.2</B></A> <I>Properly constructed assembly programs suffer no transformation loss.</I>
|
||||
</P>
|
||||
<P>The key, of course, is the programmer, since in assembly the programmer must essentially perform the transformation from the application specification to machine language entirely on his or her own. (The assembler merely handles the <I>direct</I> translation from assembly to machine language.)</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">Self-Reliance</FONT></H4>
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||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A>Self-Reliance</H4>
|
||||
<P>The first part of assembly language optimization, then, is self. An assembler is nothing more than a tool to let you design machine-language programs without having to think in hexadecimal codes. So assembly language programmers—unlike all other programmers—must take full responsibility for the quality of their code. Since assemblers provide little help at any level higher than the generation of machine language, the assembly programmer must be capable both of coding any programming construct directly and of controlling the PC at the lowest practical level—the operating system, the BIOS, even the hardware where necessary. High-level languages handle most of this transparently to the programmer, but in assembly everything is fair—and necessary—game, which brings us to another aspect of assembly optimization: knowledge.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Knowledge</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Knowledge</H4>
|
||||
<P>In the PC world, you can never have enough knowledge, and every item you add to your store will make your programs better. Thorough familiarity with both the operating system APIs and BIOS interfaces is important; since those interfaces are well-documented and reasonably straightforward, my advice is to get a good book or two and bring yourself up to speed. Similarly, familiarity with the PC hardware is required. While that topic covers a lot of ground—display adapters, keyboards, serial ports, printer ports, timer and DMA channels, memory organization, and more—most of the hardware is well-documented, and articles about programming major hardware components appear frequently in the literature, so this sort of knowledge can be acquired readily enough.
|
||||
</P>
|
||||
<P>The single most critical aspect of the hardware, and the one about which it is hardest to learn, is the CPU. The x86 family CPUs have a complex, irregular instruction set, and, unlike most processors, they are neither straightforward nor wellregarding true code performance. What’s more, assembly is so difficult to learn that most articles and books that present assembly code settle for code that just works, rather than code that pushes the CPU to its limits. In fact, since most articles and books are written for inexperienced assembly programmers, there is very little information of any sort available about how to generate high-quality assembly code for the x86 family CPUs. As a result, knowledge about programming them effectively is by far the hardest knowledge to gather. A good portion of this book is devoted to seeking out such knowledge.</P>
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||||
<H3><A NAME="Heading8"></A><FONT COLOR="#000077">The Flexible Mind</FONT></H3>
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||||
<H3><A NAME="Heading8"></A>The Flexible Mind</H3>
|
||||
<P>Is the never-ending collection of information all there is to the assembly optimization, then? Hardly. Knowledge is simply a necessary base on which to build. Let’s take a moment to examine the objectives of good assembly programming, and the remainder of the forces that act on assembly optimization will fall into place.
|
||||
</P>
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||||
<P>Basically, there are only two possible objectives to high-performance assembly programming: Given the requirements of the application, keep to a minimum either the number of processor cycles the program takes to run, or the number of bytes in the program, or some combination of both. We’ll look at ways to achieve both objectives, but we’ll more often be concerned with saving cycles than saving bytes, for the PC generally offers relatively more memory than it does processing horsepower. In fact, we’ll find that two-to-three times performance improvements <I>over already tight assembly code</I> are often possible if we’re willing to spend additional bytes in order to save cycles. It’s not always desirable to use such techniques to speed up code, due to the heavy memory requirements—but it is almost always <I>possible</I>.</P>
|
||||
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@ -50,7 +50,7 @@
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|||
<P>Simple logic dictates that no compiler can know as much about what a piece of code needs to do or adapt as well to those needs as the person who wrote the code. Given that superior information and adaptability, an assembly language programmer can generate better code than a compiler, all the more so given that compilers are constrained by the limitations of high-level languages and by the process of transformation from high-level to machine language. Consequently, carefully optimized assembly is not just the language of choice but the <I>only</I> choice for the 1percent to 10 percent of code—usually consisting of small, well-defined subroutines—that determines overall program performance, and it is the only choice for code that must be as compact as possible, as well. In the run-of-the-mill, non-time-critical portions of your programs, it makes no sense to waste time and effort on writing optimized assembly code—concentrate your efforts on loops and the like instead; but in those areas where you need the finest code quality, accept no substitutes.</P>
|
||||
<P>Note that I said that an assembly programmer <I>can</I> generate better code than a compiler, not <I>will</I> generate better code. While it is true that good assembly code is better than good compiled code, it is also true that bad assembly code is often much worse than bad compiled code; since the assembly programmer has so much control over the program, he or she has virtually unlimited opportunities to waste cycles and bytes. The sword cuts both ways, and good assembly code requires more, not less, forethought and planning than good code written in a high-level language.</P>
|
||||
<P>The gist of all this is simply that good assembly programming is done in the context of a solid overall framework unique to each program, and the flexible mind is the key to creating that framework and holding it together.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">Where to Begin?</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A>Where to Begin?</H4>
|
||||
<P>To summarize, the skill of assembly language optimization is a combination of knowledge, perspective, and a way of thought that makes possible the genesis of absolutely the fastest or the smallest code. With that in mind, what should the first step be? Development of the flexible mind is an obvious step. Still, the flexible mind is no better than the knowledge at its disposal. The first step in the journey toward mastering optimization at that exalted level, then, would seem to be learning how to learn.
|
||||
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||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 3<BR>Assume Nothing
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Understanding and Using the Zen Timer</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 3<BR>Assume Nothing</H2>
|
||||
<H3><A NAME="Heading2"></A>Understanding and Using the Zen Timer</H3>
|
||||
<P>When you’re pushing the envelope in writing optimized PC code, you’re likely to become more than a little compulsive about finding approaches that let you wring more speed from your computer. In the process, you’re bound to make mistakes, which is fine—as long as you watch for those mistakes and <I>learn</I> from them.</P>
|
||||
<P>A case in point: A few years back, I came across an article about 8088 assembly language called “Optimizing for Speed.” Now, “optimize” is not a word to be used lightly; <I>Webster’s Ninth New Collegiate Dictionary</I> defines optimize as “to make as perfect, effective, or functional as possible,” which certainly leaves little room for error. The author had, however, chosen a small, well-defined 8088 assembly language routine to refine, consisting of about 30 instructions that did nothing more than expand 8 bits to 16 bits by duplicating each bit.</P>
|
||||
<P>The author of “Optimizing” had clearly fine-tuned the code with care, examining alternative instruction sequences and adding up cycles until he arrived at an implementation he calculated to be nearly 50 percent faster than the original routine. In short, he had used all the information at his disposal to improve his code, and had, as a result, saved cycles by the bushel. There was, in fact, only one slight problem with the optimized version of the routine....</P>
|
||||
<P>It ran slower than the original version!</P>
|
||||
<H3><A NAME="Heading3"></A><FONT COLOR="#000077">The Costs of Ignorance</FONT></H3>
|
||||
<H3><A NAME="Heading3"></A>The Costs of Ignorance</H3>
|
||||
<P>As diligent as the author had been, he had nonetheless committed a cardinal sin of x86 assembly language programming: He had assumed that the information available to him was both correct and complete. While the execution times provided by Intel for its processors are indeed correct, they are incomplete; the other—and often more important—part of code performance is instruction <I>fetch</I> time, a topic to which I will return in later chapters.</P>
|
||||
<P>Had the author taken the time to measure the true performance of his code, he wouldn’t have put his reputation on the line with relatively low-performance code. What’s more, had he actually measured the performance of his code and found it to be unexpectedly slow, curiosity might well have led him to experiment further and thereby add to his store of reliable information about the CPU.</P>
|
||||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP"><IMG SRC="images/i.jpg"><TD WIDTH="95%" VALIGN="TOP"><I><SMALL>There you have an important tenet of assembly language optimization: After crafting the best code possible, check it in action to see if it’s really doing what you think it is. If it’s not behaving as expected, that’s all to the good, since solving mysteries is the path to knowledge. You’ll learn more in this way, I assure you, than from any manual or book on assembly language.</I></SMALL>
|
||||
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|
@ -51,7 +50,7 @@
|
|||
<P><I>Assume nothing</I>. I cannot emphasize this strongly enough—when you care about performance, do your best to improve the code and then <I>measure</I> the improvement. If you don’t measure performance, you’re just guessing, and if you’re guessing, you’re not very likely to write top-notch code.</P>
|
||||
<P>Ignorance about true performance can be costly. When I wrote video games for a living, I spent days at a time trying to wring more performance from my graphics drivers. I rewrote whole sections of code just to save a few cycles, juggled registers, and relied heavily on blurry-fast register-to-register shifts and adds. As I was writing my last game, I discovered that the program ran perceptibly faster if I used look-up tables instead of shifts and adds for my calculations. It <I>shouldn’t</I> have run faster, according to my cycle counting, but it did. In truth, instruction fetching was rearing its head again, as it often does, and the fetching of the shifts and adds was taking as much as four times the nominal execution time of those instructions.</P>
|
||||
<P>Ignorance can also be responsible for considerable wasted effort. I recall a debate in the letters column of one computer magazine about exactly how quickly text can be drawn on a Color/Graphics Adapter (CGA) screen without causing snow. The letter-writers counted every cycle in their timing loops, just as the author in the story that started this chapter had. Like that author, the letter-writers had failed to take the prefetch queue into account. In fact, they had neglected the effects of video wait states as well, so the code they discussed was actually <I>much</I> slower than their estimates. The proper test would, of course, have been to run the code to see if snow resulted, since the only true measure of code performance is observing it in action.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">The Zen Timer</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>The Zen Timer</H3>
|
||||
<P>Clearly, one key to mastering Zen-class optimization is a tool with which to measure code performance. The most accurate way to measure performance is with expensive hardware, but reasonable measurements at no cost can be made with the PC’s 8253 timer chip, which counts at a rate of slightly over 1,000,000 times per second. The 8253 can be started at the beginning of a block of code of interest and stopped at the end of that code, with the resulting count indicating how long the code took to execute with an accuracy of about 1 microsecond. (A microsecond is one millionth of a second, and is abbreviated µs). To be precise, the 8253 counts once every 838.1 nanoseconds. (A nanosecond is one billionth of a second, and is abbreviated ns.)
|
||||
</P>
|
||||
<P>Listing 3.1 shows 8253-based timer software, consisting of three subroutines: <B>ZTimerOn, ZTimerOff</B>, and <B>ZTimerReport</B>. For the remainder of this book, I’ll refer to these routines collectively as the “Zen timer.” C-callable versions of the two precision Zen timers are presented in Chapter K on the companion CD-ROM.</P><P><BR></P>
|
||||
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<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">The Zen Timer Is a Means, Not an End</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>The Zen Timer Is a Means, Not an End</H4>
|
||||
<P>We’re going to spend the rest of this chapter seeing what the Zen timer can do, examining how it works, and learning how to use it. I’ll be using the Zen timer again and again over the course of this book, so it’s essential that you learn what the Zen timer can do and how to use it. On the other hand, it is by no means essential that you understand exactly how the Zen timer works. (Interesting, yes; essential, no.)
|
||||
</P>
|
||||
<P>In other words, the Zen timer isn’t really part of the knowledge we seek; rather, it’s one tool with which we’ll acquire that knowledge. Consequently, you shouldn’t worry if you don’t fully grasp the inner workings of the Zen timer. Instead, focus on learning how to <I>use</I> it, and you’ll be on the right road.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">Starting the Zen Timer</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A>Starting the Zen Timer</H4>
|
||||
<P><B>ZTimerOn</B> is called at the start of a segment of code to be timed. <B>ZTimerOn</B> saves the context of the calling code, disables interrupts, sets timer 0 of the 8253 to mode 2 (divide-by-N mode), sets the initial timer count to 0, restores the context of the calling code, and returns. (I’d like to note that while Intel’s documentation for the 8253 seems to indicate that a timer won’t reset to 0 until it finishes counting down, in actual practice, timers seem to reset to 0 as soon as they’re loaded.)</P>
|
||||
<P>Two aspects of <B>ZTimerOn</B> are worth discussing further. One point of interest is that <B>ZTimerOn</B> disables interrupts. (<B>ZTimerOff</B> later restores interrupts to the state they were in when <B>ZTimerOn</B> was called.) Were interrupts not disabled by <B>ZTimerOn</B>, keyboard, mouse, timer, and other interrupts could occur during the timing interval, and the time required to service those interrupts would incorrectly and erratically appear to be part of the execution time of the code being measured. As a result, code timed with the Zen timer should not expect any hardware interrupts to occur during the interval between any call to <B>ZTimerOn</B> and the corresponding call to <B>ZTimerOff</B>, and should not enable interrupts during that time.</P>
|
||||
<H3><A NAME="Heading7"></A><FONT COLOR="#000077">Time and the PC</FONT></H3>
|
||||
<H3><A NAME="Heading7"></A>Time and the PC</H3>
|
||||
<P>A second interesting point about <B>ZTimerOn</B> is that it may introduce some small inaccuracy into the system clock time whenever it is called. To understand why this is so, we need to examine the way in which both the 8253 and the PC’s system clock (which keeps the current time) work.</P>
|
||||
<P>The 8253 actually contains three timers, as shown in Figure 3.1. All three timers are driven by the system board’s 14.31818 MHz crystal, divided by 12 to yield a 1.19318 MHz clock to the timers, so the timers count once every 838.1 ns. Each of the three timers counts down in a programmable way, generating a signal on its output pin when it counts down to 0. Each timer is capable of being halted at any time via a 0 level on its gate input; when a timer’s gate input is 1, that timer counts constantly. All in all, the 8253’s timers are inherently very flexible timing devices; unfortunately, much of that flexibility depends on how the timers are connected to external circuitry, and in the PC the timers are connected with specific purposes in mind.</P>
|
||||
<P>Timer 2 drives the speaker, although it can be used for other timing purposes when the speaker is not in use. As shown in Figure 3.1, timer 2 is the only timer with a programmable gate input in the PC; that is, timer 2 is the only timer that can be started and stopped under program control in the manner specified by Intel. On the other hand, the <I>output</I> of timer 2 is connected to nothing other than the speaker. In particular, timer 2 cannot generate an interrupt to get the 8088’s attention.</P>
|
||||
<P>Timer 1 is dedicated to providing dynamic RAM refresh, and should not be tampered with lest system crashes result.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/03-01.jpg',410,243 )"> --><IMG SRC="images/03-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/03-01.jpg',410,243)"> --><FONT COLOR="#000077"><B>Figure 3.1</B></FONT></A> <I>The configuration of the 8253 timer chip in the PC.</I>
|
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<BR><A HREF="javascript:displayWindow('images/03-01.jpg',410,243)"> --><B>Figure 3.1</B></A> <I>The configuration of the 8253 timer chip in the PC.</I>
|
||||
</P>
|
||||
<P>Finally, timer 0 is used to drive the system clock. As programmed by the BIOS at power-up, every 65,536 (64K) counts, or 54.925 milliseconds, timer 0 generates a rising edge on its output line. (A millisecond is one-thousandth of a second, and is abbreviated ms.) This line is connected to the hardware interrupt 0 (IRQ0) line on the system board, so every 54.925 ms, timer 0 causes hardware interrupt 0 to occur.
|
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<P>Potentially far greater inaccuracy can be incurred by timing code that takes longer than about 110 ms to execute. Recall that all interrupts, including the timer interrupt, are disabled while timing code with the Zen timer. The 8259 interrupt controller is capable of remembering at most one pending timer interrupt, so all timer interrupts after the first one during any given Zen timing interval are ignored. Consequently, if a timing interval exceeds 54.9 ms, the system clock effectively stops 54.9 ms after the timing interval starts and doesn’t restart until the timing interval ends, losing time all the while.</P>
|
||||
<P>The effects on the system time of the Zen timer aren’t a matter for great concern, as they are temporary, lasting only until the next warm or cold boot. System that have batteryclocks, (AT-style machines; that is, virtually all machines in common use) automatically reset the correct time whenever the computer is booted, and systems without battery-clocks prompt for the correct date and time when booted. Also,repeated use of the Zen timer usually makes the system clock slow by at most a total of a few seconds, unless code that takes much longer than 54 ms to run is timed (in which case the Zen timer will notify you that the code is too long to time).</P>
|
||||
<P>Nonetheless, it’s a good idea to reboot your computer at the end of each session with the Zen timer in order to make sure that the system clock is correct.</P>
|
||||
<H3><A NAME="Heading8"></A><FONT COLOR="#000077">Stopping the Zen Timer</FONT></H3>
|
||||
<H3><A NAME="Heading8"></A>Stopping the Zen Timer</H3>
|
||||
<P>At some point after <B>ZTimerOn</B> is called, <B>ZTimerOff</B> must always be called to mark the end of the timing interval. <B>ZTimerOff</B> saves the context of the calling program, latches and reads the timer 0 count, converts that count from the countdown value that the timer maintains to the number of counts elapsed since <B>ZTimerOn</B> was called, and stores the result. Immediately after latching the timer 0 count—and before enabling interrupts—<B>ZTimerOff</B> checks the 8259 interrupt controller to see if there is a pending timer interrupt, setting a flag to mark that the timer overflowed if there is indeed a pending timer interrupt.</P>
|
||||
<P>After that, <B>ZTimerOff</B> executes just the overhead code of <B>ZTimerOn</B> and <B>ZTimerOff</B> 16 times, and averages and saves the results in order to determine how many of the counts in the timing result just obtained were incurred by the overhead of the Zen timer rather than by the code being timed.</P>
|
||||
<P>Finally, <B>ZTimerOff</B> restores the context of the calling program, including the state of the interrupt flag that was in effect when <B>ZTimerOn</B> was called to start timing, and returns.</P>
|
||||
<P>One interesting aspect of <B>ZTimerOff</B> is the manner in which timer 0 is stopped in order to read the timer count. We don’t actually have to stop timer 0 to read the count; the 8253 provides a special latched read feature for the specific purpose of reading the count while a time is running. (That’s a good thing, too; we’ve no documented way to stop timer 0 if we wanted to, since its gate input isn’t connected. Later in this chapter, though, we’ll see that timer 0 can be stopped after all.) We simply tell the 8253 to latch the current count, and the 8253 does so without breaking stride.</P>
|
||||
<H3><A NAME="Heading9"></A><FONT COLOR="#000077">Reporting Timing Results</FONT></H3>
|
||||
<H3><A NAME="Heading9"></A>Reporting Timing Results</H3>
|
||||
<P><B>ZTimerReport</B> may be called to display timing results at any time after both <B>ZTimerOn</B> and <B>ZTimerOff</B> have been called. <B>ZTimerReport</B> first checks to see whether the timer overflowed (counted down to 0 and turned over) before <B>ZTimerOff</B> was called; if overflow did occur, <B>ZTimerOff</B> prints a message to that effect and returns. Otherwise, <B>ZTimerReport</B> subtracts the reference count (representing the overhead of the Zen timer) from the count measured between the calls to <B>ZTimerOn</B> and <B>ZTimerOff</B>, converts the result from timer counts to microseconds, and prints the resulting time in microseconds to the standard output.</P>
|
||||
<P>Note that <B>ZTimerReport</B> need not be called immediately after <B>ZTimerOff</B>. In fact, after a given call to <B>ZTimerOff, ZTimerReport</B> can be called at any time right up until the next call to <B>ZTimerOn</B>.</P>
|
||||
<P>You may want to use the Zen timer to measure several portions of a program while it executes normally, in which case it may not be desirable to have the text printed by <B>ZTimerReport</B> interfere with the program’s normal display. There are many ways to deal with this. One approach is removal of the invocations of the DOS print string function (INT 21H with AH equal to 9) from <B>ZTimerReport</B>, instead running the program under a debugger that supports screen flipping (such as Turbo Debugger or CodeView), placing a breakpoint at the start of <B>ZTimerReport</B>, and directly observing the count in microseconds as <B>ZTimerReport</B> calculates it.</P>
|
||||
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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<H3><A NAME="Heading10"></A><FONT COLOR="#000077">Notes on the Zen Timer</FONT></H3>
|
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<H3><A NAME="Heading10"></A>Notes on the Zen Timer</H3>
|
||||
<P>The Zen timer subroutines are designed to be near-called from assembly language code running in the public segment <B>Code</B>. The Zen timer subroutines can, however, be called from any assembly or high-level language code that generates OBJ files that are compatible with the Microsoft linker, simply by modifying the segment that the timer code runs in to match the segment used by the code being timed, or by changing the Zen timer routines to far procedures and making far calls to the Zen timer code from the code being timed, as discussed at the end of this chapter. All three subroutines preserve all registers and all flags except the interrupt flag, so calls to these routines are transparent to the calling code.</P>
|
||||
<P>If you do change the Zen timer routines to far procedures in order to call them from code running in another segment, be sure to make <I>all</I> the Zen timer routines far, including <B>ReferenceZTimerOn</B> and <B>ReferenceZTimerOff</B>. (You’ll have to put <B>FAR PTR</B> overrides on the calls from <B>ZTimerOff</B> to the latter two routines if you do make them far.) If the reference routines aren’t the same type—near or far—as the other routines, they won’t reflect the true overhead incurred by starting and stopping the Zen timer.</P>
|
||||
<P>Please be aware that the inaccuracy that the Zen timer can introduce into the system clock time does not affect the accuracy of the performance measurements reported by the Zen timer itself. The 8253 counts once every 838 ns, giving us a count resolution of about 1µs, although factors such as the prefetch queue (as discussed below), dynamic RAM refresh, and internal timing variations in the 8253 make it perhaps more accurate to describe the Zen timer as measuring code performance with an accuracy of better than 10µs. In fact, the Zen timer is actually most accurate in assessing code performance when timing intervals longer than about 100 µs. At any rate, we’re most interested in using the Zen timer to assess the relative performance of various code sequences—that is, using it to compare and tweak code—and the timer is more than accurate enough for that purpose.</P>
|
||||
<P>The Zen timer works on all PC-compatible computers I’ve tested it on, including XTs, ATs, PS/2 computers, and 386, 486, and Pentium-based machines. Of course, I haven’t been able to test it on <I>all</I> PC-compatibles, but I don’t expect any problems; computers on which the Zen timer doesn’t run can’t truly be called “PC-compatible.”</P>
|
||||
<P>On the other hand, there is certainly no guarantee that code performance as measured by the Zen timer will be the same on compatible computers as on genuine IBM machines, or that either absolute or relative code performance will be similar even on different IBM models; in fact, quite the opposite is true. For example, every PS/2 computer, even the relatively slow Model 30, executes code much faster than does a PC or XT. As another example, I set out to do the timings for my earlier book <I>Zen of Assembly Language</I> on an XTcomputer, only to find that the computer wasn’t quite IBM-compatible regarding code performance. The differences were minor, mind you, but my experience illustrates the risk of assuming that a specific make of computer will perform in a certain way without actually checking.</P>
|
||||
<P>Not that this variation between models makes the Zen timer one whit less useful—quite the contrary. The Zen timer is an excellent tool for evaluating code performance over the entire spectrum of PC-compatible computers.</P>
|
||||
<H3><A NAME="Heading11"></A><FONT COLOR="#000077">A Sample Use of the Zen Timer</FONT></H3>
|
||||
<H3><A NAME="Heading11"></A>A Sample Use of the Zen Timer</H3>
|
||||
<P>Listing 3.2 shows a test-bed program for measuring code performance with the Zen timer. This program sets DS equal to CS (for reasons we’ll discuss shortly), includes the code to be measured from the file TESTCODE, and calls <B>ZTimerReport</B> to display the timing results. Consequently, the code being measured should be in the file TESTCODE, and should contain calls to <B>ZTimerOn</B> and <B>ZTimerOff</B> .</P>
|
||||
<P><B>LISTING 3.2 PZTEST.ASM</B></P>
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|
|||
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<!-- END CODE SNIP //-->
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||||
<P>In fact, that’s exactly how I timed each of the listings in this book. Code fragments you write yourself can be timed in just the same way. If you wish to time code directly in place in your programs, rather than in the test-bed program of Listing 3.2, simply insert calls to <B>ZTimerOn, ZTimerOff</B>, and <B>ZTimerReport</B> in the appropriate places and link PZTIMER to your program.</P>
|
||||
<H3><A NAME="Heading12"></A><FONT COLOR="#000077">The Long-Period Zen Timer</FONT></H3>
|
||||
<H3><A NAME="Heading12"></A>The Long-Period Zen Timer</H3>
|
||||
<P>With a few exceptions, the Zen timer presented above will serve us well for the remainder of this book since we’ll be focusing on relatively short code sequences that generally take much less than 54 ms to execute. Occasionally, however, we will need to time longer intervals. What’s more, it is very likely that you will want to time code sequences longer than 54 ms at some point in your programming career. Accordingly, I’ve also developed a Zen timer for periods longer than 54 ms. The long-period Zen timer (so named by contrast with the precision Zen timer just presented) shown in Listing 3.5 can measure periods up to one hour in length.
|
||||
</P>
|
||||
<P>The key difference between the long-period Zen timer and the precision Zen timer is that the long-period timer leaves interrupts enabled during the timing period. As a result, timer interrupts are recognized by the PC, allowing the BIOS to maintain an accurate system clock time over the timing period. Theoretically, this enables measurement of arbitrarily long periods. Practically speaking, however, there is no need for a timer that can measure more than a few minutes, since the DOS time of day and date functions (or, indeed, the DATE and TIME commands in a batch file) serve perfectly well for longer intervals. Since very long timing intervals aren’t needed, the long-period Zen timer uses a simplified means of calculating elapsed time that is limited to measuring intervals of an hour or less. If a period longer than an hour is timed, the long-period Zen timer prints a message to the effect that it is unable to time an interval of that length.</P>
|
||||
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|||
<P>While permitting the timer interrupt to occur allows long intervals to be timed, that same interrupt makes the long-period Zen timer less accurate than the precision Zen timer, since the time the BIOS spends handling timer interrupts during the timing interval is included in the time measured by the long-period timer. Likewise, any other interrupts that occur during the timing interval, most notably keyboard and mouse interrupts, will increase the measured time.
|
||||
</P>
|
||||
<P>The long-period Zen timer has some of the same effects on the system time as does the precision Zen timer, so it’s a good idea to reboot the system after a session with the long-period Zen timer. The long-period Zen timer does not, however, have the same potential for introducing major inaccuracy into the system clock time during a single timing run since it leaves interrupts enabled and therefore allows the system clock to update normally.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading13"></A><FONT COLOR="#000077">Stopping the Clock</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading13"></A>Stopping the Clock</H4>
|
||||
<P>There’s a potential problem with the long-period Zen timer. The problem is this: In order to measure times longer than 54 ms, we must maintain not one but two timing components, the timer 0 count and the BIOS time-of-day count. The time-of-day count measures the passage of 54.9 ms intervals, while the timer 0 count measures time within those 54.9 ms intervals. We need to read the two time components simultaneously in order to get a clean reading. Otherwise, we may read the timer count just before it turns over and generates an interrupt, then read the BIOS time-of-day count just after the interrupt has occurred and caused the time-of-day count to turn over, with a resulting 54 ms measurement inaccuracy. (The opposite sequence—reading the time-of-day count and then the timer count—can result in a 54 ms inaccuracy in the other direction.)
|
||||
</P>
|
||||
<P>The only way to avoid this problem is to stop timer 0, read both the timer and time-of-day counts while the timer is stopped, and then restart the timer. Alas, the gate input to timer 0 isn’t program-controllable in the PC, so there’s no documented way to stop the timer. (The latched read feature we used in Listing 3.1 doesn’t stop the timer; it latches a count, but the timer keeps running.) What should we do?</P>
|
||||
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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|||
<P>While the the non-PS/2 version is more dangerous than the PS/2 version, it also produces more accurate results when it does work. If you have a non-PS/2 PC-compatible computer, the choice between the two timing approaches is yours.</P>
|
||||
<P>If you do leave the <B>PS2</B> equate at 1 in Listing 3.5, you should repeat each code-timing run several times before relying on the results to be accurate to more than 54 ms, since variations may result from the possible lack of synchronization between the timer 0 count and the BIOS time-of-day count. In fact, it’s a good idea to time code more than once no matter which version of the long-period Zen timer you’re using, since interrupts, which must be enabled in order for the long-period timer to work properly, may occur at any time and can alter execution time substantially.</P>
|
||||
<P>Finally, please note that the <I>precision</I> Zen timer works perfectly well on both PS/2 and non-PS/2 computers. The PS/2 and 8253 considerations we’ve just discussed apply <I>only</I> to the longZen timer.</P>
|
||||
<H3><A NAME="Heading14"></A><FONT COLOR="#000077">Example Use of the Long-Period Zen Timer</FONT></H3>
|
||||
<H3><A NAME="Heading14"></A>Example Use of the Long-Period Zen Timer</H3>
|
||||
<P>The long-period Zen timer has exactly the same calling interface as the precision Zen timer, and can be used in place of the precision Zen timer simply by linking it to the code to be timed in place of linking the precision timer code. Whenever the precision Zen timer informs you that the code being timed takes too long for the precision timer to handle, all you have to do is link in the long-period timer instead.
|
||||
</P>
|
||||
<P>Listing 3.6 shows a test-bed program for the long-period Zen timer. While this program is similar to Listing 3.2, it’s worth noting that Listing 3.6 waits for a few seconds before calling <B>ZTimerOn</B>, thereby allowing any pending keyboard interrupts to be processed. Since interrupts must be left on in order to time periods longer than 54 ms, the interrupts generated by keystrokes (including the upstroke of the Enter key press that starts the program)—or any other interrupts, for that matter—could incorrectly inflate the time recorded by the long-period Zen timer. In light of this, resist the temptation to type ahead, move the mouse, or the like while the long-period Zen timer is timing.</P>
|
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|
||||
<P>the result is 72,544 µs, or about 3.63 µs per load of AL from memory. This is just slightly longer than the time per load of AL measured by the precision Zen timer, as we would expect given that interrupts are left enabled by the long-period Zen timer. The extra fraction of a microsecond measured per <B>MOV</B> reflects the time required to execute the BIOS code that handles the 18.2 timer interrupts that occur each second.</P>
|
||||
<P>Note that the command can take as much as 10 minutes to finish on a slow PC if you are using MASM, with most of that time spent assembling Listing 3.8. Why? Because MASM is notoriously slow at assembling <B>REPT</B> blocks, and the block in Listing 3.8 is repeated 20,000 times.</P>
|
||||
<H3><A NAME="Heading15"></A><FONT COLOR="#000077">Using the Zen Timer from C</FONT></H3>
|
||||
<H3><A NAME="Heading15"></A>Using the Zen Timer from C</H3>
|
||||
<P>The Zen timer can be used to measure code performance when programming in C—but not right out of the box. As presented earlier, the timer is designed to be called from assembly language; some relatively minor modifications are required before the <B>ZTimerOn</B> (start timer), <B>ZTimerOff</B> (stop timer), and <B>ZTimerReport</B> (display timing results) routines can be called from C. There are two separate cases to be dealt with here: small code model and large; I’ll tackle the simpler one, the small code model, first.</P>
|
||||
<P>Altering the Zen timer for linking to a small code model C program involves the following steps: <B> C</B> hange <B>ZTimerOn</B> to <B>_ZTimerOn</B>, change <B>ZTimerOff</B> to <B>_ZTimerOff</B>, change <B>ZTimerReport</B> to <B>_ZTimerReport</B>, and change <B>Code</B> to <B>_TEXT</B> . Figure 3.2 shows the line numbers and new states of all lines from Listing 3.1 that must be changed. These changes convert the code to use C-style external label names and the small model C code segment. (In C<SMALL>++</SMALL>, use the “C” specifier, as in</P>
|
||||
<!-- CODE SNIP //-->
|
||||
|
|
@ -166,7 +166,7 @@ extern “C” ZTimerOn(void);
|
|||
|
||||
<hr width="90%" size="1" noshade>
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||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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@ -50,12 +50,12 @@ ZTimerReport();
|
|||
<P>(I’m talking about the precision timer here. The long-period timer—Listing 3.5—requires the same modifications, but to different lines.)
|
||||
</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/03-02.jpg',410,189 )"> --><IMG SRC="images/03-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/03-02.jpg',410,189)"> --><FONT COLOR="#000077"><B>Figure 3.2</B></FONT></A> <I>Changes for use with small code model C.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/03-02.jpg',410,189)"> --><B>Figure 3.2</B></A> <I>Changes for use with small code model C.</I>
|
||||
</P>
|
||||
<P>Altering the Zen timer for use in C’s large code model is a tad more complex, because in addition to the above changes, all functions, including the internal reference timing routines that are used to calculate overhead so it can be subtracted out, must be converted to far. Figure 3.3 shows the line numbers and new states of all lines from Listing 3.1 that must be changed in order to call the Zen timer from large code model C. Again, the line numbers are specific to the precision timer, but the long-period timer is very similar.
|
||||
</P>
|
||||
<P>The full listings for the C-callable Zen timers are presented in Chapter K on the companion CD-ROM.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading16"></A><FONT COLOR="#000077">Watch Out for Optimizing Assemblers!</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading16"></A>Watch Out for Optimizing Assemblers!</H4>
|
||||
<P>One important safety tip when modifying the Zen timer for use with large code model C code: Watch out for optimizing assemblers! TASM actually replaces
|
||||
</P>
|
||||
<!-- CODE SNIP //-->
|
||||
|
|
@ -73,16 +73,16 @@ call near ptr ReferenceZTimerOn
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>(and likewise for <B>ReferenceZTimerOff</B> ), which works because <B>ReferenceZTimerOn</B> is in the same segment as the calling code. This is normally a great optimization, being both smaller and faster than a far call. However, it’s not so great for the Zen</P>
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/03-03.jpg',413,221 )"> --><IMG SRC="images/03-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/03-03.jpg',413,221)"> --><FONT COLOR="#000077"><B>Figure 3.3</B></FONT></A> <I>Changes for use with large code model C.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/03-03.jpg',413,221)"> --><B>Figure 3.3</B></A> <I>Changes for use with large code model C.</I>
|
||||
</P>
|
||||
<P>timer, because our purpose in calling the reference timing code is to determine exactly how much time is taken by overhead code—including the far calls to <B>ZTimerOn</B> and <B>ZTimerOf</B>f! By converting the far calls to push/near call pairs within the Zen timer module, TASM makes it impossible to emulate exactly the overhead of the Zen timer, and makes timings slightly (about 16 cycles on a 386) less accurate.</P>
|
||||
<P>What’s the solution? Put the <B>NOSMART</B> directive at the start of the Zen timer code. This directive instructs TASM to turn off all optimizations, including converting far calls to push/near call pairs. By the way, there is, to the best of my knowledge, no such problem with MASM up through version 5.10A.</P>
|
||||
<P>In my mind, the whole business of optimizing assemblers is a mixed blessing. In general, it’s nice to have the assembler shortening jumps and selecting sign-extended forms of instructions for you. On the other hand, the benefits of tricks like substituting push/near call pairs for far calls are relatively small, and those tricks can get in the way when complete control is needed. Sure, complete control is needed very rarely, but when it is, optimizing assemblers can cause subtle problems; I discovered TASM’s alteration of far calls only because I happened to view the code in the debugger, and you might want to do the same if you’re using a recent version of MASM.</P>
|
||||
<P>I’ve tested the changes shown in Figures 3.2 and 3.3 with TASM and Borland C<SMALL>++</SMALL> 4.0, and also with the latest MASM and Microsoft C/C<SMALL>++</SMALL> compiler.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading17"></A><FONT COLOR="#000077">Further Reading</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading17"></A>Further Reading</H4>
|
||||
<P>For those of you who wish to pursue the mechanics of code measurement further, one good article about measuring code performance with the 8253 timer is “Programming Insight: High-Performance Software Analysis on the IBM PC,” by Byron Sheppard, which appeared in the January, 1987 issue of <I>Byte</I>. For complete if somewhat cryptic information on the 8253 timer itself, I refer you to Intel’s <I>Microsystem Components Handbook</I>, which is also a useful reference for a number of other PC components, including the 8259 Programmable Interrupt Controller and the 8237 DMA Controller. For details about the way the 8253 is used in the PC, as well as a great deal of additional information about the PC’s hardware and BIOS resources, I suggest you consult IBM’s series of technical reference manuals for the PC, XT, AT, Model 30, and microchannel computers, such as the Models 50, 60, and 80.</P>
|
||||
<P>For our purposes, however, it’s not critical that you understand exactly how the Zen timer works. All you really need to know is what the Zen timer can do and how to use it, and we’ve accomplished that in this chapter.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading18"></A><FONT COLOR="#000077">Armed with the Zen Timer, Onward and Upward</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading18"></A>Armed with the Zen Timer, Onward and Upward</H4>
|
||||
<P>The Zen timer is not perfect. For one thing, the finest resolution to which it can measure an interval is at best about 1µs, a period of time in which a 66 MHz Pentium computer can execute as many as 132 instructions (although an 8088-based PC would be hard-pressed to manage two instructions in a microsecond). Another problem is that the timing code itself interferes with the state of the prefetch queue and processor cache at the start of the code being timed, because the timing code is not necessarily fetched and does not necessarily access memory in exactly the same time sequence as the code immediately preceding the code under measurement normally does. This prefetch effect can introduce as much as 3 to 4 µ of inaccuracy. Similarly, the state of the prefetch queue at the end of the code being timed affects how long the code that stops the timer takes to execute. Consequently, the Zen timer tends to be more accurate for longer code sequences, since the relative magnitude of the inaccuracy introduced by the Zen timer becomes less over longer periods.
|
||||
</P>
|
||||
<P>Imperfections notwithstanding, the Zen timer is a good tool for exploring C code and x86 family assembly language, and it’s a tool we’ll use frequently for the remainder of this book.</P><P><BR></P>
|
||||
|
|
@ -98,7 +98,7 @@ call near ptr ReferenceZTimerOn
|
|||
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||||
<hr width="90%" size="1" noshade>
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<div align="center">
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 4<BR>In the Lair of the Cycle-Eaters
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">How the PC Hardware Devours Code Performance</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 4<BR>In the Lair of the Cycle-Eaters</H2>
|
||||
<H3><A NAME="Heading2"></A>How the PC Hardware Devours Code Performance</H3>
|
||||
<P>This chapter, adapted from my earlier book, <I>Zen of Assembly Language</I> located on the companion CD-ROM, goes right to the heart of my philosophy of optimization: Understand where the time really goes when your code runs. That may sound ridiculously simple, but, as this chapter makes clear, it turns out to be a challenging task indeed, one that at times verges on black magic. This chapter is a long-time favorite of mine because it was the first—and to a large extent only—work that I know of that discussed this material, thereby introducing a generation of PC programmers to pedal-to-the-metal optimization.</P>
|
||||
<P>This chapter focuses almost entirely on the first popular x86-family processor, the 8088. Some of the specific features and results that I cite in this chapter are no longer applicable to modern x86-family processors such as the 486 and Pentium, as I’ll point out later on when we discuss those processors. Nonetheless, the overall theme of this chapter—that understanding dimly-seen and poorly-documented code gremlins called cycle-eaters that lurk in your system is essential to performance programming—is every bit as valid today. Also, later chapters often refer back to the basic cycle-eaters described in this chapter, so this chapter is the foundation for the discussions of x86-family optimization to come. What’s more, the Zen timer remains an excellent tool with which to flush out and examine cycle-eaters, as we’ll see in later chapters, and this chapter is as good an illustration of how to use the Zen timer as you’re likely to find.</P>
|
||||
<P>So, don’t take either the absolute or the relative execution times presented in this chapter as gospel for newer processors, and read on to later chapters to see how the cycle-eaters and optimization rules have changed over time, but do take the time to at least skim through this chapter to give yourself a good start on the material in the rest of this book.</P>
|
||||
<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Cycle-Eaters</FONT></H3>
|
||||
<H3><A NAME="Heading3"></A>Cycle-Eaters</H3>
|
||||
<P>Programming has many levels, ranging from the familiar (high-level languages, DOS calls, and the like) down to the esoteric things that lie on the shadowy edge of hardware-land. I call these <I>cycle-eaters</I> because, like the monsters in a bad 50s horror movie, they lurk in those shadows, taking their share of your program’s performance without regard to the forces of goodness or the U.S. Army. In this chapter, we’re going to jump right in at the lowest level by examining the cycle-eaters that live beneath the programming interface; that is, beneath your application, DOS, and BIOS—in fact, beneath the instruction set itself.</P>
|
||||
<P>Why start at the lowest level? Simply because cycle-eaters affect the performance of all assembler code, and yet are almost unknown to most programmers. A full understanding of code optimization requires an understanding of cycle-eaters and their implications. That’s no simple task, and in fact it is in precisely that area that most books and articles about assembly programming fall short.</P>
|
||||
<P>Nearly all literature on assembly programming discusses only the programming interface: the instruction set, the registers, the flags, and the BIOS and DOS calls. Those topics cover the functionality of assembly programs most thoroughly—but it’s performance above all else that we’re after. No one ever tells you about the raw stuff of performance, which lies <I>beneath</I> the programming interface, in the dimly-seen realm—populated by instruction prefetching, dynamic RAM refresh, and wait states—where software meets hardware. This area is the domain of hardware engineers, and is almost never discussed as it relates to code performance. And yet it is only by understanding the mechanisms operating at this level that we can fully understand and properly improve the performance of our code.</P>
|
||||
<P>Which brings us to cycle-eaters.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">The Nature of Cycle-Eaters</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>The Nature of Cycle-Eaters</H3>
|
||||
<P>Cycle-eaters are gremlins that live on the bus or in peripherals (and sometimes within the CPU itself), slowing the performance of PC code so that it doesn’t execute at full speed. Most cycle-eaters (and all of those haunting the older Intel processors) live outside the CPU’s Execution Unit, where they can <I>only</I> affect the CPU when the CPU performs a bus access (a memory or I/O read or write). Once your code and data are already inside the CPU, those cycle-eaters can no longer be a problem. Only on the 486 and Pentium CPUs will you find cycle-eaters inside the chip, as we’ll see in later chapters.</P>
|
||||
<P>The nature and severity of the cycle-eaters vary enormously from processor to processor, and (especially) from memory architecture to memory architecture. In order to understand them all, we need first to understand the simplest among them, those that haunted the original 8088-based IBM PC. Later on in this book, I’ll be better able to explain the newer generation of cycle-eaters in terms of those ancestral cycle-eaters—but we have to get the groundwork down first.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">The 8088’s Ancestral Cycle-Eaters</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>The 8088’s Ancestral Cycle-Eaters</H4>
|
||||
<P>Internally, the 8088 is a 16-bit processor, capable of running at full speed at all times—unless external data is required. External data must traverse the 8088’s external data bus and the PC’s data bus one byte at a time to and from peripherals, with cycle-eaters lurking along every step of the way. What’s more, external data includes not only memory operands <I>but also instruction bytes,</I> so even instructions with no memory operands can suffer from cycle-eaters. Since some of the 8088’s fastest instructions are register-only instructions, that’s important indeed.</P>
|
||||
<P>The major cycle-eaters are:</P>
|
||||
<ul>
|
||||
|
|
@ -61,7 +60,7 @@
|
|||
</ul>
|
||||
<P>The locations of these cycle-eaters in the primordial 8088-based PC are shown in Figure 4.1. We’ll cover each of the cycle-eaters in turn in this chapter. The material won’t be easy since cycle-eaters are among the most subtle aspects of assembly programming. By the same token, however, this will be one of the most important and rewarding chapters in this book. Don’t worry if you don’t catch everything in this chapter, but do read it all even if the going gets a bit tough. Cycle-eaters play a key role in later chapters, so some familiarity with them is highly desirable.
|
||||
</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">The 8-Bit Bus Cycle-Eater</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>The 8-Bit Bus Cycle-Eater</H3>
|
||||
<P><I>Look! Down on the motherboard! It’s a 16-bit processor! It’s an 8-bit processor! It’s...</I></P>
|
||||
<P>...an 8088!</P>
|
||||
<P>Fans of the 8088 call it a 16-bit processor. Fans of other 16-bit processors call the 8088 an 8-bit processor. The truth of the matter is that the 8088 is a 16-bit processor that often performs like an 8-bit processor.</P>
|
||||
|
|
@ -78,7 +77,7 @@
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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|||
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|
||||
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@ -37,16 +37,16 @@
|
|||
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|
||||
<P><BR></P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/04-01.jpg',411,379 )"> --><IMG SRC="images/04-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/04-01.jpg',411,379)"> --><FONT COLOR="#000077"><B>Figure 4.1</B></FONT></A> <I>The location of the major cycle-eaters in the IBM PC.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/04-01.jpg',411,379)"> --><B>Figure 4.1</B></A> <I>The location of the major cycle-eaters in the IBM PC.</I>
|
||||
</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/04-02.jpg',418,236 )"> --><IMG SRC="images/04-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/04-02.jpg',418,236)"> --><FONT COLOR="#000077"><B>Figure 4.2</B></FONT></A> <I>Internal data bus widths of the 8088.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/04-02.jpg',418,236)"> --><B>Figure 4.2</B></A> <I>Internal data bus widths of the 8088.</I>
|
||||
</P>
|
||||
<P>As shown in Figure 4.1, the 8-bit bus cycle-eater lies squarely on the 8088’s external data bus. Technically, it might be more accurate to place this cycle-eater in the Bus Interface Unit, which breaks 16-bit memory accesses into paired 8-bit accesses, but it is really the limited width of the external data bus that constricts data flow into and out of the 8088. True, the original PC’s bus is also only 8 bits wide, but that’s just to match the 8088’s 8-bit bus; even if the PC’s bus were 16 bits wide, data could still pass into and out of the 8088 chip itself only 1 byte at a time.
|
||||
</P>
|
||||
<P>Each bus access by the 8088 takes 4 clock cycles, or 0.838 µs in the 4.77 MHz PC, and transfers 1 byte. That means that the maximum rate at which data can be transferred into and out of the 8088 is 1 byte every 0.838 µs. While 8086 bus accesses also take 4 clock cycles, each 8086 bus access can transfer either 1 byte or 1 word, for a maximum transfer rate of 1 word every 0.838 µs. Consequently, for word-sized memory accesses, the 8086 has an effective transfer rate of 1 byte every 0.419 µs. By contrast, every word-sized access on the 8088 requires two 4-cycle-long bus accesses, one for the high byte of the word and one for the low byte of the word. As a result, the 8088 has an effective transfer rate for word-sized memory accesses of just 1 word every 1.676 µs—and that, in a nutshell, is the 8-bit bus cycle-eater.</P>
|
||||
<P>A related cycle-eater lurks beneath the 386SX chip, which is a 32-bit processor internally with only a 16-bit path to system memory. The numbers are different, but the way the cycle-eater operates is exactly the same. AT-compatible systems have 16-bit data buses, which can access a full 16-bit word at a time. The 386SX can process 32 bits (a doubleword) at a time, however, and loses a lot of time fetching that doubleword from memory in two halves.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">The Impact of the 8-Bit Bus Cycle-Eater</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A>The Impact of the 8-Bit Bus Cycle-Eater</H4>
|
||||
<P>One obvious effect of the 8-bit bus cycle-eater is that word-sized accesses to memory operands on the 8088 take 4 cycles longer than byte-sized accesses. That’s why the official instruction timings indicate that for code running on an 8088 an additional 4 cycles are required for every word-sized access to a memory operand. For instance,
|
||||
</P>
|
||||
<!-- CODE SNIP //-->
|
||||
|
|
@ -76,7 +76,7 @@ add byte ptr [MemVar],al
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>String instructions can suffer from the 8-bit bus cycle-eater to a greater extent than other instructions. Believe it or not, a single <B>REP MOVSW</B> instruction can lose as much as 131,070 word-sized memory accesses x 4 cycles, or <I>524,280 cycles</I> to the 8-bit bus cycle-eater! In other words, one 8088 instruction (admittedly, an instruction that does a great deal) can take over one-tenth of a second longer on an 8088 than on an 8086, simply because of the 8-bit bus. <I>One-tenth of a second!</I> That’s a phenomenally long time in computer terms; in one-tenth of a second, the 8088 can perform more than 50,000 additions and subtractions.</P>
|
||||
<P>The upshot of all this is simply that the 8088 can transfer word-sized data to and from memory at only half the speed of the 8086, which inevitably causes performance problems when coupled with an Execution Unit that can process word-sized data every bit as quickly as an 8086. These problems show up with any code that uses word-sized memory operands. More ominously, as we will see shortly, the 8-bit bus cycle-eater can cause performance problems with other sorts of code as well.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A><FONT COLOR="#000077">What to Do about the 8-Bit Bus Cycle-Eater?</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A>What to Do about the 8-Bit Bus Cycle-Eater?</H4>
|
||||
<P>The obvious implication of the 8-bit bus cycle-eater is that byte-sized memory variables should be used whenever possible. After all, the 8088 performs <I>byte-sized</I> memory accesses just as quickly as the 8086. For instance, Listing 4.1, which uses a byte-sized memory variable as a loop counter, runs in 10.03 s per loop. That’s 20 percent faster than the 12.05 µs per loop execution time of Listing 4.2, which uses a word-sized counter. Why the difference in execution times? Simply because each word-sized <B>DEC</B> performs 4 byte-sized memory accesses (two to read the word-sized operand and two to write the result back to memory), while each byte-sized <B>DEC</B> performs only 2 byte-sized memory accesses in all.</P>
|
||||
<P><B>LISTING 4.1 LST4-1.ASM</B></P>
|
||||
<!-- CODE //-->
|
||||
|
|
@ -127,7 +127,7 @@ LoopTop:
|
|||
|
||||
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<P>There is yet another reason why register operands are preferable to memory operands, and it’s an unexpected effect of the 8-bit bus cycle-eater. Instructions with only register operands tend to be shorter (in terms of bytes) than instructions with memory operands, and when it comes to performance, shorter is usually better. In order to explain why that is true and how it relates to the 8-bit bus cycle-eater, I must diverge for a moment.</P>
|
||||
<P>For the last few pages, you may well have been thinking that the 8-bit bus cycle-eater, while a nuisance, doesn’t seem particularly subtle or difficult to quantify. After all, any instruction reference tells us exactly how many cycles each instruction loses to the 8-bit bus cycle-eater, doesn’t it?</P>
|
||||
<P>Yes and no. It’s true that in general we know approximately how much longer a given instruction will take to execute with a word-sized memory operand than with a byte-sized operand, although the dynamic RAM refresh and wait state cycle-eaters (which I’ll cover a little later) can raise the cost of the 8-bit bus cycle-eater considerably. However, <I>all</I> word-sized memory accesses lose 4 cycles to the 8-bit bus cycle-eater, and there’s one sort of word-sized memory access we haven’t discussed yet: instruction fetching. The ugliest manifestation of the 8-bit bus cycle-eater is in fact the prefetch queue cycle-eater.</P>
|
||||
<H3><A NAME="Heading9"></A><FONT COLOR="#000077">The Prefetch Queue Cycle-Eater</FONT></H3>
|
||||
<H3><A NAME="Heading9"></A>The Prefetch Queue Cycle-Eater</H3>
|
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<P>In an 8088 context, here’s the prefetch queue cycle-eater in a nutshell: The 8088’s 8-bit external data bus keeps the Bus Interface Unit from fetching instruction bytes as fast as the 16-bit Execution Unit can execute them, so the Execution Unit often lies idle while waiting for the next instruction byte to be fetched.
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</P>
|
||||
<P>Exactly why does this happen? Recall that the 8088 is an 8086 internally, but accesses word-sized memory data at only one-half the maximum rate of the 8086 due to the 8088’s 8-bit external data bus. Unfortunately, instructions are among the word-sized data the 8086 fetches, meaning that the 8088 can fetch instructions at only one-half the speed of the 8086. On the other hand, the 8086-equivalent Execution Unit of the 8088 can <I>execute</I> instructions every bit as fast as the 8086. The net result is that the Execution Unit burns up instruction bytes much faster than the Bus Interface Unit can fetch them, and ends up idling while waiting for instructions bytes to arrive.</P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">Official Execution Times Are Only Part of the Story</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A>Official Execution Times Are Only Part of the Story</H4>
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<P>The sequence of 5 <B>SHR</B> instructions in the last example is 10 bytes long. That means that it can never execute in less than 24 cycles even if the 4-byte prefetch queue is full when it starts, since 6 instruction bytes would still remain to be fetched, at 4 cycles per fetch. If the prefetch queue is empty at the start, the sequence <I>could</I> take 40 cycles. In short, thanks to instruction fetching, the code won’t run at its documented speed, and could take up to four times longer than it is supposed to.</P>
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<P>Why does Intel document Execution Unit execution time rather than overall instruction execution time, which includes both instruction fetch time and Execution Unit (EU) execution time? Well, instruction fetching isn’t performed as part of instruction execution by the Execution Unit, but instead is carried on in parallel by the Bus Interface Unit (BIU) whenever the external data bus isn’t in use or whenever the EU runs out of instruction bytes to execute. Sometimes the BIU is able to use spare bus cycles to prefetch instruction bytes before the EU needs them, so in those cases instruction fetching takes no time at all, practically speaking. At other times the EU executes instructions faster than the BIU can fetch them, and instruction fetching then becomes a significant part of overall execution time. As a result, <I>the effective fetch time for a given instruction varies greatly depending on the code mix preceding that instruction.</I> Similarly, the state in which a given instruction leaves the prefetch queue affects the overall execution time of the following instructions.</P>
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<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>In other words, while the execution time for a given instruction is constant, the fetch time for that instruction depends heavily on the context in which the instruction is executing—the amount of prefetching the preceding instructions allowed—and can vary from a full 4 cycles per instruction byte to no time at all.</I></SMALL>
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<P>As we’ll see later, other cycle-eaters, such as DRAM refresh and display memory wait states, can cause prefetching variations even during different executions of the same code sequence. Given that, it’s meaningless to talk about the prefetch time of a given instruction except in the context of a specific code sequence.
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</P>
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<P>So now you know why the official instruction execution times are often wrong, and why Intel can’t provide better specifications. You also know now why it is that you must time your code if you want to know how fast it really is.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading11"></A><FONT COLOR="#000077">There Is No Such Beast as a True Instruction Execution Time</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading11"></A>There Is No Such Beast as a True Instruction Execution Time</H4>
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<P>The effect of the code preceding an instruction on the execution time of that instruction makes the Zen timer trickier to use than you might expect, and complicates the interpretation of the results reported by the Zen timer. For one thing, the Zen timer is best used to time code sequences that are more than a few instructions long; below 10µs or so, prefetch queue effects and the limited resolution of the clock driving the timer can cause problems.
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</P>
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<P>Some slight prefetch queue-induced inaccuracy usually exists even when the Zen timer is used to time longer code sequences, since the calls to the Zen timer usually alter the code’s prefetch queue from its normal state. (Branches—jumps, calls, returns and the like—empty the prefetch queue.) Ideally, the Zen timer is used to measure the performance of an entire subroutine, so the prefetch queue effects of the branches at the start and end of the subroutine are similar to the effects of the calls to the Zen timer when you’re measuring the subroutine’s performance.</P>
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</PRE>
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<!-- END CODE //-->
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<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/04-03.jpg',414,337 )"> --><IMG SRC="images/04-03.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/04-03.jpg',414,337)"> --><FONT COLOR="#000077"><B>Figure 4.3</B></FONT></A> <I>Execution and instruction prefetching sequence for Listing 4.5.</I>
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<BR><A HREF="javascript:displayWindow('images/04-03.jpg',414,337)"> --><B>Figure 4.3</B></A> <I>Execution and instruction prefetching sequence for Listing 4.5.</I>
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</P>
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<P>Now let’s examine Listing 4.6. Here each <B>SHR</B> follows a <B>MUL</B> instruction. Since <B>MUL</B> instructions take so long to execute that the prefetch queue is always full when they finish, each <B>SHR</B> should be ready and waiting in the prefetch queue when the preceding <B>MUL</B> ends. As a result, we’d expect that each <B>SHR</B> would execute in 2 cycles; together with the 118-cycle execution time of multiplying 0 times 0, the total execution time should come to 120 cycles per <B>SHR/MUL</B> pair, as shown in Figure 4.4. And, by God, when we run Listing 4.6 we get an execution time of 25.14 µs per <B>SHR/MUL</B> pair, or <I>exactly</I> 120 cycles! According to these results, the “true” execution time of <B>SHR</B> would seem to be 2 cycles, quite a change from the conclusion we drew from Listing 4.5.</P>
|
||||
<P>The key point is this: We’ve seen one code sequence in which <B>SHR</B> took 8-plus cycles to execute, and another in which it took only 2 cycles. Are we talking about two different forms of <B>SHR</B> here? Of course not—the difference is purely a reflection of the differing states in which the preceding code left the prefetch queue. In Listing 4.5, each <B>SHR</B> after the first few follows a slew of other <B>SHR</B> instructions which have sucked the prefetch queue dry, so overall performance reflects instruction fetch time. By contrast, each <B>SHR</B> in Listing 4.6 follows a <B>MUL</B> instruction which leaves the prefetch queue full, so overall performance reflects Execution Unit execution time.</P><P><BR></P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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@ -39,7 +39,7 @@
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<P>Clearly, either instruction fetch time <I>or</I> Execution Unit execution time—or even a mix of the two, if an instruction is partially prefetched—can determine code performance. Some people operate under a rule of thumb by which they assume that the execution time of each instruction is 4 cycles times the number of bytes in the instruction. While that’s often true for register-only code, it frequently doesn’t hold for code that accesses memory. For one thing, the rule should be 4 cycles times the number of <I>memory accesses,</I> not instruction bytes, since all accesses take 4 cycles on the 8088-based PC. For another, memory-accessing instructions often have slower Execution Unit execution times than the 4 cycles per memory access rule would dictate, because the 8088 isn’t very fast at calculating memory addresses. Also, the 4 cycles per instruction byte rule isn’t true for register-only instructions that are already in the prefetch queue when the preceding instruction ends.</P>
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||||
<P>The truth is that it never hurts performance to reduce either the cycle count or the byte count of a given bit of code, but there’s no guarantee that one or the other will improve performance either. For example, consider Listing 4.7, which consists of a series of 4-cycle, 2-byte <B>MOV AL,0</B> instructions, and which executes at the rate of 1.81 µs per instruction. Now consider Listing 4.8, which replaces the 4-cycle <B>MOV AL,0</B> with the 3-cycle (but still 2-byte) <B>SUB AL,AL,</B> Despite its 1-cycle-per-instruction advantage, Listing 4.8 runs at exactly the same speed as Listing 4.7. The reason: Both instructions are 2 bytes long, and in both cases it is the 8-cycle instruction fetch time, not the 3 or 4-cycle Execution Unit execution time, that limits performance.</P>
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<P><A NAME="Fig4"><!-- </A><A HREF="javascript:displayWindow('images/04-04.jpg',410,449 )"> --><IMG SRC="images/04-04.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/04-04.jpg',410,449)"> --><FONT COLOR="#000077"><B>Figure 4.4</B></FONT></A> <I>Execution and instruction prefetching sequence for Listing 4.6.</I>
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<BR><A HREF="javascript:displayWindow('images/04-04.jpg',410,449)"> --><B>Figure 4.4</B></A> <I>Execution and instruction prefetching sequence for Listing 4.6.</I>
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<P><B>LISTING 4.7 LST4-7.ASM</B></P>
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<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>The only true execution time for an instruction is a time measured in a certain context, and that time is meaningful only in that context.</I></SMALL>
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<P>What we <I>really</I> want is to know how long useful working code takes to run, not how long a single instruction takes, and the Zen timer gives us the tool we need to gather that information. Granted, it would be easier if we could just add up neatly documented instruction execution times—but that’s not going to happen. Without actually measuring the performance of a given code sequence, you simply don’t know how fast it is. For crying out loud, even the people who <I>designed</I> the 8088 at Intel couldn’t tell you exactly how quickly a given 8088 code sequence executes on the PC just by looking at it! Get used to the idea that execution times are only meaningful in context, learn the rules of thumb in this book, and use the Zen timer to measure your code.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading12"></A><FONT COLOR="#000077">Approximating Overall Execution Times</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading12"></A>Approximating Overall Execution Times</H4>
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||||
<P>Don’t think that because overall instruction execution time is determined by both instruction fetch time and Execution Unit execution time, the two times should be added together when estimating performance. For example, practically speaking, each <B>SHR</B> in Listing 4.5 does not take 8 cycles of instruction fetch time plus 2 cycles of Execution Unit execution time to execute. Figure 4.3 shows that while a given <B>SHR</B> is executing, the fetch of the next <B>SHR</B> is starting, and since the two operations are overlapped for 2 cycles, there’s no sense in charging the time to both instructions. You could think of the extra instruction fetch time for <B>SHR</B> in Listing 4.5 as being 6 cycles, which yields an overall execution time of 8 cycles when added to the 2 cycles of Execution Unit execution time.</P>
|
||||
<P>Alternatively, you could think of each <B>SHR</B> in Listing 4.5 as taking 8 cycles to fetch, and then executing in effectively 0 cycles while the next <B>SHR</B> is being fetched. Whichever perspective you prefer is fine. The important point is that the time during which the execution of one instruction and the fetching of the next instruction overlap should only be counted toward the overall execution time of one of the instructions. For all intents and purposes, one of the two instructions runs at no performance cost whatsoever while the overlap exists.</P>
|
||||
<P>As a working definition, we’ll consider the execution time of a given instruction in a particular context to start when the first byte of the instruction is sent to the Execution Unit and end when the first byte of the next instruction is sent to the EU.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading13"></A><FONT COLOR="#000077">What to Do about the Prefetch Queue Cycle-Eater?</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading13"></A>What to Do about the Prefetch Queue Cycle-Eater?</H4>
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||||
<P>Reducing the impact of the prefetch queue cycle-eater is one of the overriding principles of high-performance assembly code. How can you do this? One effective technique is to minimize access to memory operands, since such accesses compete with instruction fetching for precious memory accesses. You can also greatly reduce instruction fetch time simply by your choice of instructions: <I>Keep your instructions short.</I> Less time is required to fetch instructions that are 1 or 2 bytes long than instructions that are 5 or 6 bytes long. Reduced instruction fetching lowers minimum execution time (minimum execution time is 4 cycles times the number of instruction bytes) and often leads to faster overall execution.</P>
|
||||
<P>While short instructions minimize overall prefetch time, ironically they actually often suffer more from the prefetch queue bottleneck than do long instructions. Short instructions generally have such fast execution times that they drain the prefetch queue despite their small size. For example, consider the <B>SHR</B> of Listing 4.5, which runs at only 25 percent of its Execution Unit execution time even though it’s only 2 bytes long, thanks to the prefetch queue bottleneck. Short instructions are nonetheless generally faster than long instructions, thanks to the combination of fewer instruction bytes and faster Execution Unit execution times, and should be used as much as possible—just don’t expect them to run at their “official” documented speeds.</P><P><BR></P>
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<P><BR></P>
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<P>More than anything, the above rules mean using the registers as heavily as possible, both because register-only instructions are short and because they don’t perform memory accesses to read or write operands. However, using the registers is a rule of thumb, not a commandment. In some circumstances, it may actually be <I>faster</I> to access memory. (The look-up table technique is one such case.) What’s more, the performance of the prefetch queue (and hence the performance of each instruction) differs from one code sequence to the next, and can even differ during different executions of the <I>same</I> code sequence.</P>
|
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<P>All in all, writing good assembler code is as much an art as a science. As a result, you should follow the rules of thumb described here—and then time your code to see how fast it really is. You should experiment freely, but always remember that actual, measured performance is the bottom line.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading14"></A><FONT COLOR="#000077">Holding Up the 8088</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading14"></A>Holding Up the 8088</H4>
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||||
<P>In this chapter I’ve taken you further and further into the depths of the PC, telling you again and again that you must understand the computer at the lowest possible level in order to write good code. At this point, you may well wonder, “Have we gotten low enough?”
|
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</P>
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<P>Not quite yet. The 8-bit bus and prefetch queue cycle-eaters are low-level indeed, but we’ve one level yet to go. Dynamic RAM refresh and wait states—our next topics—together form the lowest level at which the hardware of the PC affects code performance. Below this level, the PC is of interest only to hardware engineers.</P>
|
||||
<P>Before we begin our discussion of dynamic RAM refresh, let’s step back for a moment to take an overall look at this lowest level of cycle-eaters. In truth, the distinctions between wait states and dynamic RAM refresh don’t much matter to a programmer. What is important is that you understand this: <I>Under certain circumstances, devices on the PC bus can stop the CPU for 1 or more cycles, making your code run more slowly than it seemingly should.</I></P>
|
||||
<P>Unlike all the cycle-eaters we’ve encountered so far, wait states and dynamic RAM refresh are strictly external to the CPU, as was shown in Figure 4.1. Adapters on the PC’s bus, such as video and memory cards, can insert wait states on any bus access, the idea being that they won’t be able to complete the access properly unless the access is stretched out. Likewise, the channel of the DMA controller dedicated to dynamic RAM refresh can request control of the bus at any time, although the CPU must relinquish the bus before the DMA controller can take over. This means that your code can’t directly control wait states or dynamic RAM refresh. However, code <I>can</I> sometimes be designed to minimize the effects of these cycle-eaters, and even when the cycle-eaters slow your code without there being a thing in the world you can do about it, you’re still better off understanding that you’re losing performance and knowing why your code doesn’t run as fast as it’s supposed to than you were programming in ignorance.</P>
|
||||
<P>Let’s start with DRAM refresh, which affects the performance of every program that runs on the PC.</P>
|
||||
<H3><A NAME="Heading15"></A><FONT COLOR="#000077">Dynamic RAM Refresh: The Invisible Hand</FONT></H3>
|
||||
<H3><A NAME="Heading15"></A>Dynamic RAM Refresh: The Invisible Hand</H3>
|
||||
<P>Dynamic RAM (DRAM) refresh is sort of an act of God. By that I mean that DRAM refresh invisibly and inexorably steals a certain fraction of all available memory access time from your programs, when they are accessing memory for code and data. (When they are accessing cache on more recent processors, theoretically the DRAM refresh cycle-eater doesn’t come into play, but there are other cycle-eaters waiting to prey on cache-bound programs.) While you <I>could</I> stop DRAM refresh, you wouldn’t want to since that would be a sure prescription for crashing your computer. In the end, thanks to DRAM refresh, almost all code runs a bit slower on the PC than it otherwise would, and that’s that.</P>
|
||||
<P>A bit of background: A static RAM (SRAM) chip is a memory chip that retains its contents indefinitely so long as power is maintained. By contrast, each of several blocks of bits in a dynamic RAM (DRAM) chip retains its contents for only a short time after it’s accessed for a read or write. In order to get a DRAM chip to store data for an extended period, each of the blocks of bits in that chip must be accessed regularly, so that the chip’s stored data is kept refreshed and valid. So long as this is done often enough, a DRAM chip will retain its contents indefinitely.</P>
|
||||
<P>All of the PC’s system memory consists of DRAM chips. Each DRAM chip in the PC must be completely refreshed about once every four milliseconds in order to ensure the integrity of the data it stores. Obviously, it’s highly desirable that the memory in the PC retain the correct data indefinitely, so each DRAM chip in the PC <I>must</I> always be refreshed within 4 µs of the last refresh. Since there’s no guarantee that a given program will access each and every DRAM block once every 4 µs, the PC contains special circuitry and programming for providing DRAM refresh.</P>
|
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<H4 ALIGN="LEFT"><A NAME="Heading16"></A><FONT COLOR="#000077">How DRAM Refresh Works in the PC</FONT></H4>
|
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<H4 ALIGN="LEFT"><A NAME="Heading16"></A>How DRAM Refresh Works in the PC</H4>
|
||||
<P>On the original 8088-based IBM PC, timer 1 of the 8253 timer chip is programmed at power-up to generate a signal once every 72 cycles, or once every 15.08µs. That signal goes to channel 0 of the 8237 DMA controller, which requests the bus from the 8088 upon receiving the signal. (DMA stands for <I>direct memory access,</I> the ability of a device other than the 8088 to control the bus and access memory directly, without any help from the 8088.) As soon as the 8088 is between memory accesses, it gives control of the bus to the 8237, which in conjunction with special circuitry on the PC’s motherboard then performs a single 4-cycle read access to 1 of 256 possible addresses, advancing to the next address on each successive access. (The read access is only for the purpose of refreshing the DRAM; the data that is read isn’t used.)</P>
|
||||
<P>The 256 addresses accessed by the refresh DMA accesses are arranged so that taken together they properly refresh all the memory in the PC. By accessing one of the 256 addresses every 15.08 µs, all of the PC’s DRAM is refreshed in 256 x 15.08 µs, or 3.86 µs, which is just about the desired 4 µs time I mentioned earlier. (Only the first 640K of memory is refreshed in the PC; video adapters and other adapters above 640K containing memory that requires refreshing must provide their own DRAM refresh in pre-AT systems.)</P>
|
||||
<P>Don’t sweat the details here. The important point is this: For at least 4 out of every 72 cycles, the original PC’s bus is given over to DRAM refresh and is not available to the 8088, as shown in Figure 4.5. That means that as much as 5.56 percent of the PC’s already inadequate bus capacity is lost. However, DRAM refresh doesn’t necessarily stop the 8088 in its tracks for 4 cycles. The Execution Unit of the 8088 can keep processing while DRAM refresh is occurring, unless the EU needs to access memory. Consequently, DRAM refresh can slow code performance anywhere from 0 percent to 5.56 percent (and actually a bit more, as we'll see shortly), depending on the extent to which DRAM refresh occupies cycles during which the 8088 would otherwise be accessing memory.</P>
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<BR><A HREF="javascript:displayWindow('images/04-05.jpg',407,339)"> --><FONT COLOR="#000077"><B>Figure 4.5</B></FONT></A> <I>The PC bus dynamic RAM (DRAM) refresh.</I>
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<BR><A HREF="javascript:displayWindow('images/04-05.jpg',407,339)"> --><B>Figure 4.5</B></A> <I>The PC bus dynamic RAM (DRAM) refresh.</I>
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<H4 ALIGN="LEFT"><A NAME="Heading17"></A><FONT COLOR="#000077">The Impact of DRAM Refresh</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading17"></A>The Impact of DRAM Refresh</H4>
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<P>Let’s look at examples from opposite ends of the spectrum in terms of the impact of DRAM refresh on code performance. First, consider the series of <B>MUL</B> instructions in Listing 4.9. Since a 16-bit <B>MUL</B> on the 8088 executes in between 118 and 133 cycles and is only 2 bytes long, there should be plenty of time for the prefetch queue to fill after each instruction, even after DRAM refresh has taken its slice of memory access time. Consequently, the prefetch queue should be able to keep the Execution Unit well-supplied with instruction bytes at all times. Since Listing 4.9 uses no memory operands, the Execution Unit should never have to wait for data from memory, and DRAM refresh should have no impact on performance. (Remember that the Execution Unit can operate normally during DRAM refreshes so long as it doesn’t need to request a memory access from the Bus Interface Unit.)</P>
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<P><B>LISTING 4.9 LST4-9.ASM</B></P>
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<P>Since 4 cycles are required to read each instruction byte, we’d expect each <B>SHR</B> to execute in 8 cycles, or 1.676 µs, if there were no DRAM refresh. In fact, each <B>SHR</B> in Listing 4.10 executes in 1.81 µs, indicating that DRAM refresh is taking 7.4 percent of the program’s execution time. That’s nearly 2 percent more than our worst-case estimate of the loss to DRAM refresh overhead! In fact, the result indicates that DRAM refresh is stealing not 4, but 5.33 cycles out of every 72 cycles. How can this be?</P>
|
||||
<P>The answer is that a given DRAM refresh can actually hold up CPU memory accesses for as many as 6 cycles, depending on the timing of the DRAM refresh’s DMA request relative to the 8088’s internal instruction execution state. When the code in Listing 4.10 runs, each DRAM refresh holds up the CPU for either 5 or 6 cycles, depending on where the 8088 is in executing the current <B>SHR</B> instruction when the refresh request occurs. Now we see that things can get even worse than we thought: <I>DRAM refresh can steal as much as 8.33 percent of available memory access time—6 out of every 72 cycles—from the 8088.</I></P>
|
||||
<P>Which of the two cases we’ve examined reflects reality? While either case <I>can</I> happen, the latter case—significant performance reduction, ranging as high as 8.33 percent—is far more likely to occur. This is especially true for high-performance assembly code, which uses fast instructions that tend to cause non-stop instruction fetching.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading18"></A><FONT COLOR="#000077">What to Do About the DRAM Refresh Cycle-Eater?</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading18"></A>What to Do About the DRAM Refresh Cycle-Eater?</H4>
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<P><I>Hmmm.</I> When we discovered the prefetch queue cycle-eater, we learned to use short instructions. When we discovered the 8-bit bus cycle-eater, we learned to use byte-sized memory operands whenever possible, and to keep word-sized variables in registers. What can we do to work around the DRAM refresh cycle-eater?</P>
|
||||
<P>Nothing.</P>
|
||||
<P>As I’ve said before, DRAM refresh is an act of God. DRAM refresh is a fundamental, unchanging part of the PC’s operation, and there’s nothing you or I can do about it. If refresh were any less frequent, the reliability of the PC would be compromised, so tinkering with either timer 1 or DMA channel 0 to reduce DRAM refresh overhead is out. Nor is there any way to structure code to minimize the impact of DRAM refresh. Sure, some instructions are affected less by DRAM refresh than others, but how many multiplies and divides in a row can you really use? I suppose that code <I>could</I> conceivably be structured to leave a free memory access every 72 cycles, so DRAM refresh wouldn’t have any effect. In the old days when code size was measured in bytes, not K bytes, and processors were less powerful—and complex—programmers did in fact use similar tricks to eke every last bit of performance from their code. When programming the PC, however, the prefetch queue cycle-eater would make such careful code synchronization a difficult task indeed, and any modest performance improvement that did result could never justify the increase in programming complexity and the limits on creative programming that such an approach would entail. Besides, all that effort goes to waste on faster 8088s, 286s, and other computers with different execution speeds and refresh characteristics. There’s no way around it: Useful code accesses memory frequently and at irregular intervals, and over the long haul DRAM refresh always exacts its price.</P>
|
||||
<P>If you’re still harboring thoughts of reducing the overhead of DRAM refresh, consider this. Instructions that tend not to suffer very much from DRAM refresh are those that have a high ratio of execution time to instruction fetch time, and those aren’t the fastest instructions of the PC. It certainly wouldn’t make sense to use slower instructions just to reduce DRAM refresh overhead, for it’s <I>total</I> execution time—DRAM refresh, instruction fetching, and all—that matters.</P>
|
||||
<P>The important thing to understand about DRAM refresh is that it generally slows your code down, and that the extent of that performance reduction can vary considerably and unpredictably, depending on how the DRAM refreshes interact with your code’s pattern of memory accesses. When you use the Zen timer and get a fractional cycle count for the execution time of an instruction, that’s often the DRAM refresh cycle-eater at work. (The display adapter cycleis another possible culprit, and, on 386s and later processors, cache misses and pipeline execution hazards produce this sort of effect as well.) Whenever you get two timing results that differ less or more than they seemingly should, that’s usually DRAM refresh too. Thanks to DRAM refresh, variations of up to 8.33 percent in PC code performance are par for the course.</P>
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<H3><A NAME="Heading19"></A><FONT COLOR="#000077">Wait States</FONT></H3>
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<H3><A NAME="Heading19"></A>Wait States</H3>
|
||||
<P>Wait states are cycles during which a bus access by the CPU to a device on the PC’s bus is temporarily halted by that device while the device gets ready to complete the read or write. Wait states are well and truly the lowest level of code performance. Everything we have discussed (and will discuss)—even DMA accesses—can be affected by wait states.
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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<P>By understanding the circumstances in which wait states can occur, you can avoid them when possible. Even when it’s not possible to work around wait states, it’s still to your advantage to understand how they can cause your code to run more slowly.</P>
|
||||
<P>First, let’s learn a bit more about wait states by contrast with DRAM refresh. Unlike DRAM refresh, wait states do not occur on any regularly scheduled basis, and are of no particular duration. Wait states can only occur when an instruction performs a memory or I/O read or write. Both the presence of wait states and the number of wait states inserted on any given bus access are entirely controlled by the device being accessed. When it comes to wait states, the CPU is passive, merely accepting whatever wait states the accessed device chooses to insert during the course of the access. All of this makes perfect sense given that the whole point of the wait state mechanism is to allow a device to stretch out any access to itself for however much time it needs to perform the access.</P>
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<P><A NAME="Fig6"><!-- </A><A HREF="javascript:displayWindow('images/04-06.jpg',415,242 )"> --><IMG SRC="images/04-06.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/04-06.jpg',415,242)"> --><FONT COLOR="#000077"><B>Figure 4.6</B></FONT></A> <I>Video wait states inserted by the display adapter.</I>
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||||
<BR><A HREF="javascript:displayWindow('images/04-06.jpg',415,242)"> --><B>Figure 4.6</B></A> <I>Video wait states inserted by the display adapter.</I>
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</P>
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||||
<P>As with DRAM refresh, wait states don’t stop the 8088 completely. The Execution Unit can continue processing while wait states are inserted, so long as the EU doesn’t need to perform a bus access. However, in the PC, wait states most often occur when an instruction accesses a memory operand, so in fact the Execution Unit usually is stopped by wait states. (Instruction fetches rarely wait in an 8088-based PC because system memory is zero-wait-state. AT-class memory systems routinely insert 1 or more wait states, however.)
|
||||
</P>
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||||
<P>As it turns out, wait states pose a serious problem in just one area in the PC. While any adapter <I>can</I> insert wait states, in the PC only display adapters do so to the extent that performance is seriously affected.</P>
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||||
<H3><A NAME="Heading20"></A><FONT COLOR="#000077">The Display Adapter Cycle-Eater</FONT></H3>
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||||
<H3><A NAME="Heading20"></A>The Display Adapter Cycle-Eater</H3>
|
||||
<P>Display adapters must serve two masters, and that creates a fundamental performance problem. Master #1 is the circuitry that drives the display screen. This circuitry must constantly read display memory in order to obtain the information used to draw the characters or dots displayed on the screen. Since the screen must be redrawn between 50 and 70 times per second, and since each redraw of the screen can require as many as 36,000 reads of display memory (more in Super VGA modes), master #1 is a demanding master indeed. No matter how demanding master #1 gets, however, its needs must <I>always</I> be met—otherwise the quality of the picture on the screen would suffer.</P>
|
||||
<P>Master #2 is the CPU, which reads from and writes to display memory in order to manipulate the bytes that the video circuitry reads to form the picture on the screen. Master #2 is less important than master #1, since the CPU affects display quality only indirectly. In other words, if the video circuitry has to wait for display memory accesses, the picture will develop holes, snow, and the like, but if the CPU has to wait for display memory accesses, the program will just run a bit slower—no big deal.</P>
|
||||
<P>It matters a great deal which master is more important, for while both the CPU and the video circuitry must gain access to display memory, only one of the two masters can read or write display memory at any one time. Potential conflicts are resolved by flat-out guaranteeing the video circuitry however many accesses to display memory it needs, with the CPU waiting for whatever display memory accesses are left over.</P>
|
||||
<P>It turns out that the 8088 CPU has to do a lot of waiting, for three reasons. First, the video circuitry can take as much as about 90 percent of the available display memory access time, as shown in Figure 4.7, leaving as little as about 10 percent of all display memory accesses for the 8088. (These percentages vary considerably among the many EGA and VGA clones.)</P>
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<P><A NAME="Fig7"><!-- </A><A HREF="javascript:displayWindow('images/04-07.jpg',415,342 )"> --><IMG SRC="images/04-07.jpg"><BR><!-- </A>
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||||
<BR><A HREF="javascript:displayWindow('images/04-07.jpg',415,342)"> --><FONT COLOR="#000077"><B>Figure 4.7</B></FONT></A> <I>Allocation of display memory access.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/04-07.jpg',415,342)"> --><B>Figure 4.7</B></A> <I>Allocation of display memory access.</I>
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</P>
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||||
<P>Second, because the displayed dots (or <I>pixels,</I> short for “picture elements”) must be drawn on the screen at a constant speed, many display adapters provide memory accesses only at fixed intervals. As a result, time can be lost while the 8088 synchronizes with the start of the next display adapter memory access, even if the video circuitry isn’t accessing display memory at that time, as shown in Figure 4.8.</P>
|
||||
<P>Finally, the time it takes a display adapter to complete a memory access is related to the speed of the clock which generates pixels on the screen rather than to the memory access speed of the 8088. Consequently, the time taken for display memory to complete an 8088 read or write access is often longer than the time taken for system memory to complete an access, even if the 8088 lucks into hitting a free display memory access just as it becomes available, again as shown in Figure 4.8. Any or all of the three factors I’ve described can result in wait states, slowing the 8088 and creating the display adapter cycle.</P>
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<P><A NAME="Fig8"><!-- </A><A HREF="javascript:displayWindow('images/04-08.jpg',417,375 )"> --><IMG SRC="images/04-08.jpg"><BR><!-- </A>
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||||
<BR><A HREF="javascript:displayWindow('images/04-08.jpg',417,375)"> --><FONT COLOR="#000077"><B>Figure 4.8</B></FONT></A> <I>Display memory access slots.</I>
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||||
<BR><A HREF="javascript:displayWindow('images/04-08.jpg',417,375)"> --><B>Figure 4.8</B></A> <I>Display memory access slots.</I>
|
||||
</P>
|
||||
<P>If some of this is Greek to you, don’t worry. The important point is that display memory is not very fast compared to normal system memory. How slow is it? <I>Incredibly</I> slow. Remember how slow IBM’s ill-fated PC<I>jr</I>was? In case you’ve forgotten, I’ll refresh your memory: The PC<I>jr</I>was at best only half as fast as the PC. The PC<I>jr</I> had an 8088 running at 4.77 MHz, just like the PC—why do you suppose it was so much slower? I’ll tell you why: <I>All the memory in the PCjr was display memory.</I></P>
|
||||
<P>Enough said. All the memory in the PC is <I>not</I> display memory, however, and unless you’re thickheaded enough to put code in display memory, the PC isn’t going to run as slowly as a PC<I>jr.</I> (Putting code or other non-video data in unused areas of display memory sounds like a neat idea—until you consider the effect on instruction prefetching of cutting the 8088’s already-poor memory access performance in half. Running your code from display memory is sort of like running on a hypothetical 8084—an 8086 with a <I>4-bit</I> bus. Not recommended!) Given that your code and data reside in normal system memory below the 640K mark, how great an impact does the display adapter cycle-eater have on performance?</P><P><BR></P>
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<P><BR></P>
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<P>The answer varies considerably depending on what display adapter and what display mode we’re talking about. The display adapter cycle-eater is worst with the Enhanced Graphics Adapter (EGA) and the original Video Graphics Array (VGA). (Many VGAs, especially newer ones, insert many fewer wait states than IBM’s original VGA. On the other hand, Super VGAs have more bytes of display memory to be accessed in high-resolution mode.) While the Color/Graphics Adapter (CGA), Monochrome Display Adapter (MDA), and Hercules Graphics Card (HGC) all suffer from the display adapter cycle-eater as well, they suffer to a lesser degree. Since the VGA represents the base standard for PC graphics now and for the foreseeable future, and since it is the hardest graphics adapter to wring performance from, we’ll restrict our discussion to the VGA (and its close relative, the EGA) for the remainder of this chapter.
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||||
<H4 ALIGN="LEFT"><A NAME="Heading21"></A><FONT COLOR="#000077">The Impact of the Display Adapter Cycle-Eater</FONT></H4>
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||||
<H4 ALIGN="LEFT"><A NAME="Heading21"></A>The Impact of the Display Adapter Cycle-Eater</H4>
|
||||
<P>Even on the EGA and VGA, the effect of the display adapter cycle-eater depends on the display mode selected. In text mode, the display adapter cycle-eater is rarely a major factor. It’s not that the cycle-eater isn’t present; however, a mere 4,000 bytes control the entire text mode display, and even with the display adapter cycle-eater it just doesn’t take that long to manipulate 4,000 bytes. Even if the display adapter cycle-eater were to cause the 8088 to take as much as 5µs per display memory access—more than five times normal—it would still take only 4,000x 2x 5µs, or 40 µs, to read and write every byte of display memory. That’s a lot of time as measured in 8088 cycles, but it’s less than the blink of an eye in human time, and video performance only matters in human time. After all, the whole point of drawing graphics is to convey visual information, and if that information can be presented faster than the eye can see, that is by definition fast enough.
|
||||
</P>
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||||
<P>That’s not to say that the display adapter cycle-eater <I>can’t</I> matter in text mode. In Chapter 3, I recounted the story of a debate among letter-writers to a magazine about exactly how quickly characters could be written to display memory without causing snow. The writers carefully added up Intel’s instruction cycle times to see how many writes to display memory they could squeeze into a single horizontal retrace interval. (On a CGA, it’s only during the short horizontal retrace interval and the longer vertical retrace interval that display memory can be accessed in 80-column text mode without causing snow.) Of course, now we know that their cardinal sin was to ignore the prefetch queue; even if there were no wait states, their calculations would have been overly optimistic. There <I>are</I> display memory wait states as well, however, so the calculations were not just optimistic but wildly optimistic.</P>
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<P>In addition, code that accesses display memory infrequently tends to suffer only about half of the maximum display memory wait states, because on average such code will access display memory halfway between one available display memory access slot and the next. As a result, code that accesses display memory less intensively than the code in Listing 4.11 will on average lose 4 or 5 rather than 8-plus cycles to the display adapter cycle-eater on each memory access.
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||||
</P>
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||||
<P>Nonetheless, the display adapter cycle-eater always takes its toll on graphics code. Interestingly, that toll becomes much higher on ATs and 80386 machines because while those computers can execute many more instructions per microsecond than can the 8088-based PC, it takes just as long to access display memory on those computers as on the 8088-based PC. Remember, the limited speed of access to a graphics adapter is an inherent characteristic of the adapter, so the fastest computer around can’t access display memory one iota faster than the adapter will allow.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading22"></A><FONT COLOR="#000077">What to Do about the Display Adapter Cycle-Eater?</FONT></H4>
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||||
<H4 ALIGN="LEFT"><A NAME="Heading22"></A>What to Do about the Display Adapter Cycle-Eater?</H4>
|
||||
<P>What can we do about the display adapter cycle-eater? Well, we can minimize display memory accesses whenever possible. In particular, we can try to avoid read/modify/write display memory operations of the sort used to mask individual pixels and clip images. Why? Because read/modify/write operations require two display memory accesses (one read and one write) each time display memory is manipulated. Instead, we should try to use writes of the sort that set all the pixels in a given byte of display memory at once, since such writes don’t require accompanying read accesses. The key here is that only half as many display memory accesses are required to write a byte to display memory as are required to read a byte from display memory, mask part of it off and alter the rest, and write the byte back to display memory. Half as many display memory accesses means half as many display memory wait states.
|
||||
</P>
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||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Moreover, 486s and Pentiums, as well as recent Super VGAs, employ write-caching schemes that make display memory writes considerably faster than display memory reads.</I></SMALL>
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</P>
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||||
<P>Another principle for display adapter programming on the 8088 is to perform multiple accesses to display memory very rapidly, in order to make use of as many of the scarce accesses to display memory as possible. This is especially important when many large images need to be drawn quickly, since only by using virtually every available display memory access can many bytes be written to display memory in a short period of time. Repeated string instructions are ideal for making maximum use of display memory accesses; of course, repeated string instructions can only be used on whole bytes, so this is another point in favor of modifying display memory a byte at a time. (On faster processors, however, display memory is so slow that it often pays to do several instructions worth of work between display memory accesses, to take advantage of cycles that would otherwise be wasted on the wait states.)</P>
|
||||
<P>It would be handy to explore the display adapter cycle-eater issue in depth, with lots of example code and execution timings, but alas, I don’t have the space for that right now. For the time being, all you really need to know about the display adapter cycle-eater is that on the 8088 you can lose more than 8 cycles of execution time on each access to display memory. For intensive access to display memory, the loss really can be as high as 8cycles (and up to 50, 100, or even more on 486s and Pentiums paired with slow VGAs), while for average graphics code the loss is closer to 4 cycles; in either case, the impact on performance is significant. There is only one way to discover just how significant the impact of the display adapter cycle-eater is for any particular graphics code, and that is of course to measure the performance of that code.</P>
|
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<H4 ALIGN="LEFT"><A NAME="Heading23"></A><FONT COLOR="#000077">Cycle-Eaters: A Summary</FONT></H4>
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||||
<H4 ALIGN="LEFT"><A NAME="Heading23"></A>Cycle-Eaters: A Summary</H4>
|
||||
<P>We’ve covered a great deal of sophisticated material in this chapter, so don’t feel bad if you haven’t understood everything you’ve read; it will all become clear from further reading, especially once you study, time, and tune code that you have written yourself. What’s really important is that you come away from this chapter understanding that on the 8088:
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|
|||
</ul>
|
||||
<P>This basic knowledge about cycle-eaters puts you in a good position to understand the results reported by the Zen timer, and that means that you’re well on your way to writing high-performance assembler code.
|
||||
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|
||||
<H4 ALIGN="LEFT"><A NAME="Heading24"></A><FONT COLOR="#000077">What Does It All Mean?</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading24"></A>What Does It All Mean?</H4>
|
||||
<P>There you have it: life under the programming interface. It’s not a particularly pretty picture for the inhabitants of that strange realm where hardware and software meet are little-known cycle-eaters that sap the speed from your unsuspecting code. Still, some of those cycle-eaters can be minimized by keeping instructions short, using the registers, using byte-sized memory operands, and accessing display memory as little as possible. None of the cycle-eaters can be eliminated, and dynamic RAM refresh can scarcely be addressed at all; still, aren’t you better off knowing how fast your code <I>really</I> runs—and why—than you were reading the official execution times and guessing? And while specific cycle-eaters vary in importance on later x86-family processors, with some cycle-eaters vanishing altogether and new ones appearing, the concept that understanding these obscure gremlins is a key to performance remains unchanged, as we’ll see again and again in later chapters.</P><P><BR></P>
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|
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 5<BR>Crossing the Border
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Searching Files with Restartable Blocks</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 5<BR>Crossing the Border</H2>
|
||||
<H3><A NAME="Heading2"></A>Searching Files with Restartable Blocks</H3>
|
||||
<P><I>We just moved.</I> Those three little words should strike terror into the heart of anyone who owns more than a sleeping bag and a toothbrush. Our last move was the usual zoo—and then some. Because the distance from the old house to the new was only five miles, we used cars to move everything smaller than a washing machine. We have a sizable household—cats, dogs, kids, com, you name it—so the moving process took a number of car trips. A <I>large</I> number—33, to be exact. I personally spent about 15 hours just driving back and forth between the two houses. The move took days to complete.</P>
|
||||
<P><I>Never again</I>.</P>
|
||||
<P>You’re probably wondering two things: What does this have to do with high-performance programming, and why on earth didn’t I rent a truck and get the move over in one or two trips, saving hours of driving? As it happens, the second question answers the first. I didn’t rent a truck because it <I>seemed</I> easier and cheaper to use cars—no big truck to drive, no rentals, spread the work out more manageably, and so on.</P>
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|||
</TABLE>
|
||||
<P>And with that, let’s look at a fairly complex application of restartable blocks.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">Searching for Text</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>Searching for Text</H4>
|
||||
<P>The application we’re going to examine searches a file for a specified string. We’ll develop a program that will search the file specified on the command line for a string (also specified on the comline), then report whether the string was found or not. (Because the searched-for string is obtained via <B>argv</B>, it can’t contain any whitespace characters.)</P>
|
||||
<P>This is a <I>very</I> limited subset of what search utilities such as grep can do, and isn’t really intended to be a generally useful application; the purpose is to provide insight into restartable blocks in particular and optimization in general in the course of developing a search engine. That search engine will, however, be easy to plug into any program, and there’s nothing preventing you from using it in a more fruitful context, like searching through a user-selectable file set.</P>
|
||||
<P>The first point to address in designing our program involves the appropriate text-search approach to use. Literally dozens of workable ways exist to search a file. We can immediately discard all approaches that involve reading any byte of the file more than once, because disk access time is orders of magnitude slower than any data handling performed by our own code. Based on our experience in Chapter 1, we can also discard all approaches that get bytes either one at a time or in small sets from DOS. We want to read big “buffers-full” of bytes at a pop from the searched file, and the bigger the buffer the better—in order to minimize DOS’s overhead. A good rough cut is a buffer that will be between 16K and 64K, depending on the exact search approach, 64K being the maximum size because near pointers make for superior performance.</P>
|
||||
<P>So we know we want to work with a large buffer, filling it as infrequently as possible. Now we have to figure out how to search through a file by loading it into that large buffer in chunks. To accomplish this, we have to know how we want to do our searching, and that’s not immediately obvious. Where do we begin?</P>
|
||||
<P>Well, it might be instructive to consider how we would search if our search involved only one buffer, already resident in memory. In other words, suppose we don’t have to bother with file handling at all, and further suppose that we don’t have to deal with searching through multiple blocks. After all, that’s a good description of the all-important inner loop of our searching program, where the program will spend virtually all of its time (aside from the unavoidable disk access overhead).</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">Avoiding the String Trap</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>Avoiding the String Trap</H3>
|
||||
<P>The easiest approach would be to use a C/C<SMALL>++</SMALL> library function. The closest match to what we need is <B>strstr()</B>, which searches one string for the first occurrence of a second string. However, while <B>strstr()</B> would work, it isn’t ideal for our purposes. The problem is this: Where we want to search a fixed-length buffer for the first occurrence of a string, <B>strstr()</B> searches a <I>string</I> for the first occurrence of another string.</P><P><BR></P>
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|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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|||
<P>We could put a zero byte at the end of our buffer to allow <B>strstr()</B> to work, but why bother? The <B>strstr()</B> function must spend time either checking for the end of the string being searched or determining the length of that string—wasted effort given that we already know exactly how long our search buffer is. Even if a given <B>strstr()</B> implementation is well-written, its performance will suffer, at least for our application, from unnecessary overhead.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>This illustrates why you shouldn’t think of C/C<SMALL>++</SMALL> library functions as black boxes; understand what they do and try to figure out how they do it, and relate that to their performance in the context you’re interested in.</I></SMALL>
|
||||
</TABLE>
|
||||
<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Brute-Force Techniques</FONT></H3>
|
||||
<H3><A NAME="Heading5"></A>Brute-Force Techniques</H3>
|
||||
<P>Given that no C/C<SMALL>++</SMALL> library function meets our needs precisely, an obvious alternative approach is the brute-force technique that uses <B>memcmp()</B> to compare <I>every</I> potential matching location in the buffer to the string we’re searching for, as illustrated in Figure 5.1.</P>
|
||||
<P>By the way, we could, of course, use our own code, working with pointers in a loop, to perform the comparison in place of <B>memcmp()</B>. But <B>memcmp()</B> will almost certainly use the very fast <B>REPZ CMPS</B> instruction. However, <I>never assume!</I> It wouldn’t hurt to use a debugger to check out the actual machine-code implementation of <B>memcmp()</B> from your compiler. If necessary, you could always write your own assembly language implementation of <B>memcmp()</B>.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/05-01.jpg',415,211 )"> --><IMG SRC="images/05-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/05-01.jpg',415,211)"> --><FONT COLOR="#000077"><B>Figure 5.1</B></FONT></A> <I>The brute-force searching technique.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/05-01.jpg',415,211)"> --><B>Figure 5.1</B></A> <I>The brute-force searching technique.</I>
|
||||
</P>
|
||||
<P>Invoking <B>memcmp()</B> for each potential match location works, but entails considerable overhead. Each comparison requires that parameters be pushed and that a call to and return from <B>memcmp()</B> be performed, along with a pass through the comparison loop. Surely there’s a better way!</P>
|
||||
<P>Indeed there is. We can eliminate most calls to <B>memcmp()</B> by performing a simple test on each potential match location that will reject most such locations right off the bat. We’ll just check whether the first character of the potentially matching buffer location matches the first character of the string we’re searching for. We could make this check by using a pointer in a loop to scan the buffer for the next match for the first character, stopping to check for a match with the rest of the string <I>only</I> when the first character matches, as shown in Figure 5.2.</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Using memchr()</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Using memchr()</H3>
|
||||
<P>There’s yet a better way to implement this approach, however. Use the <B>memchr()</B> function, which does nothing more or less than find the next occurrence of a specified character in a fixed-length buffer (presumably by using the extremely efficient <B>REPNZ SCASB</B> instruction, although again it wouldn’t hurt to check). By using <B>memchr()</B> to scan for potential matches that can then be fully tested with <B>memcmp()</B>, we can build a highly efficient search engine that takes good advantage of the information we have about the buffer being searched and the string we’re searching for. Our engine also relies heavily on repeated string instructions, assuming that the <B>memchr()</B> and <B>memcmp()</B> library functions are properly coded.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/05-02.jpg',409,241 )"> --><IMG SRC="images/05-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/05-02.jpg',409,241)"> --><FONT COLOR="#000077"><B>Figure 5.2</B></FONT></A> <I>The faster string-searching technique.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/05-02.jpg',409,241)"> --><B>Figure 5.2</B></A> <I>The faster string-searching technique.</I>
|
||||
</P>
|
||||
<P>We’re going to go with the this approach in our file-searching program; the only trick lies in deciding how to integrate this approach with restartable blocks in order to search through files larger than our buffer. This certainly isn’t the fastest-possible searching algorithm; as one example, the Boyer-Moore algorithm, which cleverly eliminates many buffer locations as potential matches in the process of checking preceding locations, can be considerably faster. However, the Boyer-Moore algorithm is quite complex to understand and implement, and would distract us from our main focus, restartable blocks, so we’ll save it for a later chapter (Chapter 14, to be precise). Besides, I suspect you’ll find the approach we’ll use to be fast enough for most purposes.
|
||||
</P>
|
||||
<P>Now that we’ve selected a searching approach, let’s integrate it with file handling and searching through multiple blocks. In other words, let’s make it restartable.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Making a Search Restartable</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Making a Search Restartable</H4>
|
||||
<P>As it happens, there’s no great trick to putting the pieces of this search program together. Basically, we’ll read in a buffer of data (we’ll work with 16K at a time to avoid signed overflow problems with integers), search it for a match with the <B>memchr()/memcmp()</B> engine described, and exit with a “string found” response if the desired string is found.</P>
|
||||
<P>Otherwise, we’ll load in another buffer full of data from the file, search it, and so on. The only trick lies in handling potentially matching sequences in the file that start in one buffer and end in the next—that is, sequences that span buffers. We’ll handle this by copying the unchecked bytes at the end of one buffer to the start of the next and reading that many fewer bytes the next time we fill the buffer.</P>
|
||||
<P>The exact number of bytes to be copied from the end of one buffer to the start of the next is the length of the searched-for string minus 1, since that’s how many bytes at the end of the buffer can’t be checked as possible matches (because the check would run off the end of the buffer).</P>
|
||||
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<H3><A NAME="Heading8"></A><FONT COLOR="#000077">Interpreting Where the Cycles Go</FONT></H3>
|
||||
<H3><A NAME="Heading8"></A>Interpreting Where the Cycles Go</H3>
|
||||
<P>To boost the overall performance of Listing 5.1, I would normally convert <B>SearchForString()</B> to assembly language at this point. However, I’m not going to do that, and the reason is as important a lesson as any discussion of optimized assembly code is likely to be. Take a moment to examine some interesting performance aspects of the C implementation, and all should become much clearer.</P>
|
||||
<P>As you’ll recall from Chapter 1, one of the important rules for optimization involves knowing when optimization is worth bothering with at all. Another rule involves understanding where most of a program’s execution time is going. That’s more true for Listing 5.1 than you might think.</P>
|
||||
<P>When Listing 5.1 is run on a 1 MB assembly source file, it takes about three seconds to find the string “xxxend” (which is at the end of the file) on a 20 MHz 386 machine, with the entire file in a disk cache. If <B>BLOCK_SIZE</B> is trimmed from 16K to 4K, <I>execution time does not increase perceptibly!</I> At 2K, the program slows slightly; it’s not until the block size shrinks to 64 bytes that execution time becomes approximately double that of the 16K buffer.</P>
|
||||
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@ -44,7 +44,7 @@
|
|||
<P>When I replaced the <B>read()</B> function call in Listing 5.1 with code that simply fools the program into thinking that a 1 MB file is being read, the program ran almost instantaneously—in less than 1/2 second, even when the searched-for string wasn’t anywhere to be found. By contrast, Listing 5.1 requires three seconds to run even when searching for a single character that isn’t found anywhere in the file, the case in which a single call to <B>memchr()</B> (and thus a single <B>REPNZ SCASB</B>) can eliminate an entire block at a time.</P>
|
||||
<P>All in all, the time required for DOS disk access calls is taking up at least 80 percent of execution time, and search time is less than 20 percent of overall execution time. In fact, search time is probably a good deal less than 20 percent of the total, given that the overhead of loading the program, running through the C startup code, opening the file, executing <B>printf()</B>, and exiting the program and returning to the DOS shell are also included in my timings. Given which, it should be apparent why converting to assembly language isn’t worth the trouble—the best we could do by speeding up the search is a 10 percent or so improvement, and that would require more than doubling the performance of code that already uses repeated string instructions to do most of the work.</P>
|
||||
<P>Not likely.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">Knowing When Assembly Is Pointless</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A>Knowing When Assembly Is Pointless</H4>
|
||||
<P>So that’s why we’re not going to go to assembly language in this example—which is not to say it would never be worth converting the search engine in Listing 5.1 to assembly.
|
||||
</P>
|
||||
<P>If, for example, your application will typically search buffers in which the first character of the search string occurs frequently as might be the case when searching a text buffer for a string starting with the space character an assembly implementation might be several times faster. Why? Because assembly code can switch from <B>REPNZ SCASB</B> to match the first character to <B>REPZ CMPS</B> to check the remaining characters in just a few instructions.</P>
|
||||
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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<P>By the way, don’t think that just because very large block sizes don’t much improve performance, it wasn’t worth using restartable blocks in Listing 5.1. Listing 5.1 runs more than three times more slowly with a block size of 32 bytes than with a block size of 4K, and any byte-by-byte approach would surely be slower still, due to the overhead of repeated calls to DOS and/or the C stream I/O library.
|
||||
</P>
|
||||
<P>Restartable blocks do minimize the overhead of DOS file-access calls in Listing 5.1; it’s just that there’s no way to reduce that overhead to the point where it becomes worth attempting to further improve the performance of our relatively efficient search engine. Although the search engine is by no means fully optimized, it’s nonetheless as fast as there’s any reason for it to be, given the balance of performance among the components of this program.</P>
|
||||
<H3><A NAME="Heading10"></A><FONT COLOR="#000077">Always Look Where Execution Is Going</FONT></H3>
|
||||
<H3><A NAME="Heading10"></A>Always Look Where Execution Is Going</H3>
|
||||
<P>I’ve explained two important lessons: Know when it’s worth optimizing further, and use restartable blocks to process large data sets as a series of blocks, with each block handled at high speed. The first lesson is less obvious than it seems.
|
||||
</P>
|
||||
<P>When I set out to write this chapter, I fully intended to write an assembly language version of Listing 5.1, and I expected the assembly version to be much faster. When I actually looked at where execution time was going (which I did by modifying the program to remove the calls to the <B>read()</B> function, but a code profiler could be used to do the same thing much more easily), I found that the best code in the world wouldn’t make much difference.</P>
|
||||
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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<P><BR></P>
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 6<BR>Looking Past Face Value
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">How Machine Instructions May Do More Than You Think</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 6<BR>Looking Past Face Value</H2>
|
||||
<H3><A NAME="Heading2"></A>How Machine Instructions May Do More Than You Think</H3>
|
||||
<P>I first met Jeff Duntemann at an authors’ dinner hosted by <I>PC Tech Journal</I> at Fall Comdex, back in 1985. Jeff was already reasonably well-known as a computer editor and writer, although not as famous as <I>Complete Turbo Pascal</I>, editions 1 through 672 (or thereabouts), <I>TURBO TECHNIX</I>, and <I>PC TECHNIQUES</I> would soon make him. I was fortunate enough to be seated next to Jeff at the dinner table, and, not surprisingly, our often animated conversation revolved around computers, computer writing, and more computers (not necessarily in that order).</P>
|
||||
<P>Although I was making a living at computer work and enjoying it at the time, I nonetheless harbored vague ambitions of being a science-fiction writer when I grew up. (I have since realized that this hardly puts me in elite company, especially in the computer world, where it seems that every other person has told me they plan to write science fiction “someday.” Given that probably fewer than 500—I’m guessing here—original science fiction and fantasy short stories, and perhaps a few more novels than that, are published each year in this country, I see a few mid-life crises coming.)</P>
|
||||
<P>At any rate, I had accumulated a small collection of rejection slips, and fancied myself something of an old hand in the field. At the end of the dinner, as the other writers complained half-seriously about how little they were paid for writing for <I>Tech Journal</I>, I leaned over to Jeff and whispered, “You know, the pay isn’t so bad here. You should see what they pay for science fiction—even to the guys who win awards!”</P>
|
||||
|
|
@ -51,7 +50,7 @@
|
|||
<P>To produce the best code, you must decide precisely what you need to accomplish, then put together the sequence of instructions that accomplishes that end most efficiently, regardless of what the instructions are usually used for. That’s why optimization for the PC is an art, and it’s why the best assembly language for the x86 family will almost always handily outperform compiled code. With that in mind, let’s look past face value—and while we’re at it, I’ll toss in a few examples of not judging a book by its cover.</P>
|
||||
<P>The point to all this: You must come to regard the x86 family instructions for what they do, not what you’re used to thinking they do. Yes, <B>SHL</B> shifts a pattern left—but a look-up table can do the same thing, and can often do it faster. <B>ADD</B> can indeed add two operands, but it can’t put the result in a third register; <B>LEA</B> can. The instruction set is your raw material for writing high-performance code. By limiting yourself to thinking only in certain well-established ways about the various instructions, you’re putting yourself at a substantial disadvantage every time you sit down to program.</P>
|
||||
<P>In short, the x86 family can do much more than you think—if you’ll use everything it has to offer. Give it a shot!</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">Memory Addressing and Arithmetic</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>Memory Addressing and Arithmetic</H4>
|
||||
<P>Years ago, I saw a clip on the David Letterman show in which Letterman walked into a store by the name of “Just Lamps” and asked, “So what do you sell here?”
|
||||
</P>
|
||||
<P>“Lamps,” he was told. “Just lamps. Can’t you read?”</P>
|
||||
|
|
@ -87,7 +86,7 @@ mov al,[bx+si]
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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|
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||||
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|
||||
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|
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|
|
@ -49,7 +49,7 @@ LoopTop:
|
|||
<P>Here, <B>MOV AL,[BX]</B> is two cycles faster than <B>MOV AL,[BX+SI]</B>.</P>
|
||||
<P>On a 286 or 386, however, the balance shifts. <B>MOV AL,[BX+SI]</B> takes no longer than <B>MOV AL,[BX]</B> on these processors because effective address calculations generally take no extra time at all. (According to the MASM manual, one extra clock is required if three memory addressing components, as in <B>MOV AL,[BX+SI+1]</B>, are used. I have not been able to confirm this from Intel publications, but then I haven’t looked all that hard.) If you’re optimizing for the 286 or 386, then, you can take advantage of the processor’s ability to perform arithmetic as part of memory address calculations without taking a performance hit.</P>
|
||||
<P>The 486 is an odd case, in which the use of an index register or the use of a base register that’s the destination of the previous instruction may slow things down, so it is generally but not always better to perform the addition outside the loop on the 486. All memory addressing calculations are free on the Pentium, however. I’ll discuss 486 performance issues in Chapters 12 and 13, and the Pentium in Chapters 19 through 21.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">Math via Memory Addressing</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>Math via Memory Addressing</H3>
|
||||
<P>You’re probably not particularly wowed to hear that you can use addressing modes to perform memory addressing arithmetic that would otherwise have to be performed with separate arithmetic instructions. You may, however, be a tad more interested to hear that you can also use addressing modes to perform arithmetic that has nothing to do with memory addressing, and with a couple of advantages over arithmetic instructions, at that.
|
||||
</P>
|
||||
<P>How?</P>
|
||||
|
|
@ -87,13 +87,13 @@ lea di,[si+2]
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>Mind you, the only components <B>LEA</B> can add are BX or BP, SI or DI, and a constant displacement, so it’s not going to replace <B>ADD</B> most of the time. Also, <B>LEA</B> is considerably slower than <B>ADD</B> on an 8088, although it is just as fast as <B>ADD</B> on a 286 or 386 when fewer than three memory addressing components are used. <B>LEA</B> is 1 cycle slower than <B>ADD</B> on a 486 if the sum of two registers is used to point to memory, but no slower than <B>ADD</B> on a Pentium. On both a 486 and Pentium, <B>LEA</B> can also be slowed down by addressing interlocks.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/06-01.jpg',418,276 )"> --><IMG SRC="images/06-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/06-01.jpg',418,276)"> --><FONT COLOR="#000077"><B>Figure 6.1</B></FONT></A> <I>Operation of ADD Reg,Reg vs. LEA Reg,{Addr}.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/06-01.jpg',418,276)"> --><B>Figure 6.1</B></A> <I>Operation of ADD Reg,Reg vs. LEA Reg,{Addr}.</I>
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">The Wonders of LEA on the 386</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>The Wonders of LEA on the 386</H4>
|
||||
<P><B>LEA</B> really comes into its own as a “super-ADD” instruction on the 386, 486, and Pentium, where it can take advantage of the enhanced memory addressing modes of those processors. (The 486 and Pentium offer the same modes as the 386, so I’ll refer only to the 386 from now on.) The 386 can do two very interesting things: It can use <I>any</I> 32-bit register (EAX, EBX, and so on) as the memory addressing base register and/or the memory addressing index register, and it can multiply any 32-bit register used as an index by two, four, or eight in the process of calculating a memory address, as shown in Figure 6.2. Let’s see what that’s good for.</P>
|
||||
<P>Well, the obvious advantage is that any two 32-bit registers, or any 32-bit register and any constant, or any two 32-bit registers and any constant, can be added together, with the result stored in any register. This makes the 32-bit <B>LEA</B> much more generally useful than the standard 16-bit <B>LEA</B> in the role of an <B>ADD</B> with an independent destination.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/06-02.jpg',421,197 )"> --><IMG SRC="images/06-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/06-02.jpg',421,197)"> --><FONT COLOR="#000077"><B>Figure 6.2</B></FONT></A> <I>Operation of the 32-bit LEA reg,[Addr].</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/06-02.jpg',421,197)"> --><B>Figure 6.2</B></A> <I>Operation of the 32-bit LEA reg,[Addr].</I>
|
||||
</P>
|
||||
<P>But what else can <B>LEA</B> do on a 386, besides add?</P>
|
||||
<P>It can multiply any register used as an index. <B>LEA</B> can multiply only by the power-of-two values 2, 4, or 8, but that’s useful more often than you might imagine, especially when dealing with pointers into tables. Besides, multiplying by 2, 4, or 8 amounts to a left shift of 1, 2, or 3 bits, so we can now add up to two 32-bit registers and a constant, <I>and</I> shift (or multiply) one of the registers to some extent—all with a single instruction. For example,</P>
|
||||
|
|
@ -114,7 +114,7 @@ add edi,offset TableBase
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>when pointing to an entry in a doubly indexed table.
|
||||
</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Multiplication with LEA Using Non-Powers of Two</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Multiplication with LEA Using Non-Powers of Two</H3>
|
||||
<P>Are you impressed yet with all that <B>LEA</B> can do on the 386? Believe it or not, one more feature still awaits us. <B>LEA</B> can actually perform a fast multiply of a 32-bit register by some values <I>other</I> than powers of two. You see, the same 32-bit register can be both base and index on the 386, and can be scaled as the index while being used unchanged as the base. That means that you can, for example, multiply EBX by 5 with:</P>
|
||||
<!-- CODE SNIP //-->
|
||||
<PRE>
|
||||
|
|
@ -147,7 +147,7 @@ add ebx,edx
|
|||
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||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
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||||
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|
|||
</TABLE>
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||||
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||||
<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 7<BR>Local Optimization
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Optimizing Halfway between Algorithms and Cycle Counting</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 7<BR>Local Optimization</H2>
|
||||
<H3><A NAME="Heading2"></A>Optimizing Halfway between Algorithms and Cycle Counting</H3>
|
||||
<P>You might not think it, but there’s much to learn about performance programming from the Great Buffalo Sauna Fiasco. To wit:
|
||||
</P>
|
||||
<P>The scene is Buffalo, New York, in the dead of winter, with the snow piled several feet deep. Four college students, living in typical student housing, are frozen to the bone. The third floor of their house, uninsulated and so cold that it’s uninhabitable, has an ancient bathroom. One fabulously cold day, inspiration strikes:</P>
|
||||
|
|
@ -54,7 +53,7 @@
|
|||
</TABLE>
|
||||
<P>So, drawing fortitude from the knowledge that our quest is a pure and worthy one, let’s resume our exploration of assembly language instructions with hidden talents and instructions with well-known talents that are less than they appear to be. In the process, we’ll come to see that there is another, very important optimization level between the algorithm/design level and the cycle-counting/individual instruction level. I’ll call this middle level <I>local optimization;</I> it involves focusing on optimizing sequences of instructions rather than individual instructions, all with an eye to implementing designs as efficiently as possible given the capabilities of the x86 family instruction set.</P>
|
||||
<P>And yes, in case you’re wondering, the above story is indeed true. Was I there? Let me put it this way: If I were, I’d never admit it!</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">When LOOP Is a Bad Idea</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>When LOOP Is a Bad Idea</H4>
|
||||
<P>Let’s examine first an instruction that is less than it appears to be: <B>LOOP</B>. There’s no mystery about what <B>LOOP</B> does; it decrements CX and branches if CX doesn’t decrement to zero. It’s so beautifully suited to the task of counting down loops that any experienced x86 programmer instinctively stuffs the loop count in CX and reaches for <B>LOOP</B> when setting up a loop. That’s fine—<B>LOOP</B> does, of course, work as advertised—but there is one problem:</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>On half of the processors in the x86 family, <B>LOOP</B> is slower than <B>DEC CX</B> followed by <B>JNZ</B>. (Granted, <B>DEC CX/JNZ</B> isn’t precisely equivalent to <B>LOOP,</B> because <B>DEC</B> alters the flags and LOOP doesn’t, but in most situations they’re comparable.)</I></SMALL>
|
||||
</TABLE>
|
||||
|
|
@ -74,7 +73,7 @@
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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||||
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||||
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|||
10
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|
|||
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|
||||
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|
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@ -51,12 +51,12 @@ jz SkipLoop ;If field is 0, don’t bother
|
|||
</PRE>
|
||||
<!-- END CODE SNIP //-->
|
||||
<P>will do just fine and is faster on all processors. Use <B>JCXZ</B> only when the Zero flag isn’t already set to reflect the status of CX.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">The Lessons of LOOP and JCXZ</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>The Lessons of LOOP and JCXZ</H3>
|
||||
<P>What can we learn from <B>LOOP</B> and <B>JCXZ?</B> First, that a single instruction that is intended to do a complex task is not necessarily faster than several instructions that together do the same thing. Second, that the relative merits of instructions and optimization rules vary to a surprisingly large degree across the x86 family.</P>
|
||||
<P>In particular, if you’re going to write 386 protected mode code, which will run only on the 386, 486, and Pentium, you’d be well advised to rethink your use of the more esoteric members of the x86 instruction set. <B>LOOP, JCXZ,</B> the various accumulator-specific instructions, and even the string instructions in many circumstances no longer offer the advantages they did on the 8088. Sometimes they’re just not any faster than more general instructions, so they’re not worth going out of your way to use; sometimes, as with <B>LOOP,</B> they’re actually slower, and you’d do well to avoid them altogether in the 386/486 world. Reviewing the instruction cycle times in the MASM or TASM manuals, or looking over the cycle times in Intel’s literature, is a good place to start; published cycle times are closer to actual execution times on the 386 and 486 than on the 8088, and are reasonably reliable indicators of the relative performance levels of x86 instructions.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">Avoiding LOOPS of Any Stripe</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>Avoiding LOOPS of Any Stripe</H4>
|
||||
<P>Cycle counting and directly substituting instructions (<B>DEC CX/JNZ</B> for <B>LOOP,</B> for example) are techniques that belong at the lowest level of optimization. It’s an important level, but it’s fairly mechanical; once you’ve learned the capabilities and relative performance levels of the various instructions, you should be able to select the best instructions fairly easily. What’s more, this is a task at which compilers excel. What I’m saying is that you shouldn’t get too caught up in counting cycles because that’s a small (albeit important) part of the optimization picture, and not the area in which your greatest advantage lies.</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Local Optimization</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Local Optimization</H3>
|
||||
<P>One level at which assembly language programming pays off handsomely is that of <I>local optimization;</I> that is, selecting the best <I>sequence</I> of instructions for a task. The key to local optimization is viewing the 80x86 instruction set as a set of building blocks, each with unique characteristics. Your job is to sequence those blocks so that they perform well. It doesn’t matter what the instructions are intended to do or what their names are; all that matters is what they <I>do.</I></P>
|
||||
<P>Our discussion of <B>LOOP</B> versus <B>DEC/JNZ</B> is an excellent example of optimization by cycle counting. It’s worth knowing, but once you’ve learned it, you just routinely use <B>DEC/JNZ</B> at the bottom of loops in 386/486-specific code, and that’s that. Besides, you’ll save at most a few cycles each time, and while that helps a little, it’s not going to make all <I>that</I> much difference.</P>
|
||||
<P>Now let’s step back for a moment, and with no preconceptions consider what the x86 instruction set can do for us. The bulk of the time with both <B>LOOP</B> and <B>DEC/JNZ</B> is taken up by branching, which just happens to be one of the slowest aspects of every processor in the x86 family, and the rest is taken up by decrementing the count register and checking whether it’s zero. There may be ways to perform those tasks a little faster by selecting different instructions, but they can get only so fast, and branching can’t even get all that fast.</P>
|
||||
|
|
@ -76,7 +76,7 @@ jz SkipLoop ;If field is 0, don’t bother
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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@ -131,7 +131,7 @@ SearchMaxLengthendp
|
|||
end Start
|
||||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<H3><A NAME="Heading7"></A><FONT COLOR="#000077">Unrolling Loops</FONT></H3>
|
||||
<H3><A NAME="Heading7"></A>Unrolling Loops</H3>
|
||||
<P>Listing 7.2 takes a different tack, unrolling the loop so that four bytes are checked for each <B>LOOP</B> performed. The same instructions are used inside the loop in each listing, but Listing 7.2 is arranged so that three-quarters of the <B>LOOP</B>s are eliminated. Listings 7.1 and 7.2 perform exactly the same task, and they use the same instructions in the loop—the searching algorithm hasn’t changed in any way—but we have sequenced the instructions differently in Listing 7.2, and that makes all the difference.</P><P><BR></P>
|
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@ -145,7 +145,7 @@ SearchMaxLengthendp
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
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||||
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||||
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@ -185,7 +185,7 @@ SearchMaxLengthendp
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
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||||
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<P><BR></P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A><FONT COLOR="#000077">Rotating and Shifting with Tables</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A>Rotating and Shifting with Tables</H4>
|
||||
<P>As another example of local optimization, consider the matter of rotating or shifting a mask into position. First, let’s look at the simple task of setting bit N of AX to 1.
|
||||
</P>
|
||||
<P>The obvious way to do this is to place N in CL, rotate the bit into position, and OR it with AX, as follows:</P>
|
||||
|
|
@ -81,13 +81,13 @@ BIT_PATTERN=BIT_PATTERN SHL 1
|
|||
<TABLE WIDTH="100%">
|
||||
<TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Besides illustrating the advantages of local optimization, this example also shows that it generally pays to precalculate results; this is often done at or before assembly time, but precalculated tables can also be built at run time. This is merely one aspect of a fundamental optimization rule: Move as much work as possible out of your critical code by whatever means necessary.</I></SMALL>
|
||||
</TABLE>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">NOT Flips Bits—Not Flags</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A>NOT Flips Bits—Not Flags</H4>
|
||||
<P>The <B>NOT</B> instruction flips all the bits in the operand, from 0 to 1 or from 1 to 0. That’s as simple as could be, but <B>NOT</B> nonetheless has a minor but interesting talent: It doesn’t affect the flags. That can be irritating; I once spent a good hour tracking down a bug caused by my unconscious assumption that <B>NOT</B> does set the flags. After all, every other arithmetic and logical instruction sets the flags; why not <B>NOT</B>? Probably because <B>NOT</B> isn’t considered to be an arithmetic or logical instruction at all; rather, it’s a data manipulation instruction, like <B>MOV</B> and the various rotates. (These are <B>RCR, RCL, ROR,</B> and <B>ROL,</B> which affect only the Carry and Overflow flags.) NOT is often used for tasks, such as flipping masks, where there’s no reason to test the state of the result, and in that context it can be handy to keep the flags unmodified for later testing.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Besides, if you want to <B>NOT</B> an operand and set the flags in the process, you can just <B>XOR</B> it with -1. Put another way, the only functional difference between <B>NOT AX</B> and <B>XOR AX,0FFFFH</B> is that <B>XOR</B> modifies the flags and <B>NOT</B> doesn’t.</I></SMALL>
|
||||
</TABLE>
|
||||
<P>The x86 instruction set offers many ways to accomplish almost any task. Understanding the subtle distinctions between the instructions—whether and which flags are set, for example—can be critical when you’re trying to optimize a code sequence and you’re running out of registers, or when you’re trying to minimize branching.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">Incrementing with and without Carry</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading10"></A>Incrementing with and without Carry</H4>
|
||||
<P>Another case in which there are two slightly different ways to perform a task involves adding 1 to an operand. You can do this with <B>INC,</B> as in <B>INC AX,</B> or you can do it with <B>ADD,</B> as in <B>ADD AX,1.</B> What’s the difference? The obvious difference is that <B>INC</B> is usually a byte or two shorter (the exception being <B>ADD AL,1,</B> which at two bytes is the same length as <B>INC AL</B>), and is faster on some processors. Less obvious, but no less important, is that <B>ADD</B> sets the Carry flag while <B>INC</B> leaves the Carry flag untouched.</P>
|
||||
<P>Why is that important? Because it allows <B>INC</B> to function as a data pointer manipulation instruction for multi-word arithmetic. You can use <B>INC</B> to advance the pointers in code like that shown in Listing 7.5 without having to do any work to preserve the Carry status from one addition to the next.</P>
|
||||
<P><B>LISTING 7.5 L7-5.ASM</B></P>
|
||||
|
|
@ -153,7 +153,7 @@ ADC DX,0
|
|||
|
||||
<hr width="90%" size="1" noshade>
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|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
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||||
<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 8<BR>Speeding Up C with Assembly Language
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Jumping Languages When You Know It’ll Help</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 8<BR>Speeding Up C with Assembly Language</H2>
|
||||
<H3><A NAME="Heading2"></A>Jumping Languages When You Know It’ll Help</H3>
|
||||
<P>When I was a senior in high school, a pop song called “Seasons in the Sun,” sung by one Terry Jacks, soared up the pop charts and spent, as best I can recall, two straight weeks atop <I>Kasey Kasem’s American Top 40.</I> “Seasons in the Sun” wasn’t a particularly good song, primarily because the lyrics were silly. I’ve never understood why the song was a hit, but, as so often happens with undistinguished but popular music by forgotten one- or two-shot groups (“Don’t Pull Your Love Out on Me Baby,” “Billy Don’t Be a Hero,” <I>et al.</I>), I heard it everywhere for a month or so, then gave it not another thought for 15 years.</P>
|
||||
<P>Recently, though, I came across a review of a Rhino Records collection of obscure 1970s pop hits. Knowing that Jeff Duntemann is an aficionado of such esoterica (who do <I>you</I> know who owns an album by The Peppermint Trolley Company?), I sent the review to him. He was amused by it and, as we kicked the names of old songs around, “Seasons in the Sun” came up. I expressed my wonderment that a song that really wasn’t very good was such a big hit.</P>
|
||||
<P>“Well,” said Jeff, “I think it suffered in the translation from the French.”</P>
|
||||
|
|
@ -48,14 +47,14 @@
|
|||
</TABLE>
|
||||
<P>Apropos of which, when was the last time you heard of Terry Jacks?
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">Billy, Don’t Be a Compiler</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>Billy, Don’t Be a Compiler</H4>
|
||||
<P>The key to optimizing C programs with assembly language is, as always, writing good assembly language code, but with an added twist. Rule 1 when converting C code to assembly is this: <I>Don’t think like a compiler.</I> That’s more easily said than done, especially when the C code you’re converting is readily available as a model and the assembly code that the compiler generates is available as well. Nevertheless, the principle of not thinking like a compiler is essential, and is, in one form or another, the basis for all that I’ll discuss below.</P>
|
||||
<P>Before I discuss Rule 1 further, let me mention rule number 0: <I>Only optimize where it matters.</I> The bulk of execution time in any program is spent in a very small portion of the code, and most code beyond that small portion doesn’t have any perceptible impact on performance. Unless you’re supremely concerned with code size (an area in which assembly-only programs can excel), I’d suggest that you write most of your code in C and reserve assembly for the truly critical sections of your code; that’s the formula that I find gives the most bang for the buck.</P>
|
||||
<P>This is not to say that complete programs shouldn’t be <I>designed</I> with optimized assembly language in mind. As you’ll see shortly, orienting your data structures towards assembly language can be a salubrious endeavor indeed, even if most of your code is in C. When it comes to actually optimizing code and/or converting it to assembly, though, do it only where it matters. Get a profiler—and use it!</P>
|
||||
<P>Also make it a point to concentrate on refining your program design and algorithmic approach at the conceptual and/or C levels before doing any assembly language optimization.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Assembly language optimization is the final and far from the only step in the optimization chain, and as such should be performed last; converting to assembly too soon can lock in your code before the design is optimal. At the very least, conversion to assembly tends to make future changes and debugging more difficult, slowing you down and limiting your options.</I></SMALL>
|
||||
</TABLE>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">Don’t Call Your Functions on Me, Baby</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>Don’t Call Your Functions on Me, Baby</H3>
|
||||
<P>In order to think differently from a compiler, you must understand both what compilers and C programmers tend to do and how that differs from what assembly language does well. In this pursuit, it can be useful to examine the code your compiler generates, either by viewing the code in a debugger or by having the compiler generate an assembly language output file. (The latter is done with /Fa or /Fc in Microsoft C/C<SMALL>++</SMALL> and -S in Borland C<SMALL>++</SMALL>.)</P>
|
||||
<P>C programmers tend to modularize their code with lots of function calls. That’s good for readable, reliable, reusable code, and it allows the compiler to optimize better because it can deal with fewer variables and statements in each optimization arena—but it’s not so good when viewed from the assembly language level. Calls and returns are slow, especially in the large code model, and the pushes required to put parameters on the stack are expensive as well.</P>
|
||||
<P>What this means is that when you want to speed up a portion of a C program, you should identify the entire critical portion and move <I>all</I> of that critical portion into an assembly language function. You don’t want to move a part of the inner loop into assembly language and then call it from C every time through the loop; the function call and return overhead would be unacceptable. Carve out the critical code <I>en masse</I> and move it into assembly, and try to avoid calls and returns even in your assembly code. True, in assembly you can pass parameters in registers, but the calls and returns themselves are still slow; if the extra cycles they take don’t affect performance, then the code they’re in probably isn’t critical, and perhaps you’ve chosen to convert too much code to assembly, eh?</P><P><BR></P>
|
||||
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|
@ -71,7 +70,7 @@
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|||
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||||
<hr width="90%" size="1" noshade>
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<div align="center">
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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||||
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||||
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||||
<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Stack Frames Slow So Much</FONT></H3>
|
||||
<H3><A NAME="Heading5"></A>Stack Frames Slow So Much</H3>
|
||||
<P>C compilers work within the stack frame model, whereby variables reside in a block of stack memory and are accessed via offsets from BP. Compilers may store a couple of variables in registers and may briefly keep other variables in registers when they’re used repeatedly, but the stack frame is the underlying architecture. It’s a nice architecture; it’s flexible, convenient, easy to program, and makes for fairly compact code. However, stack frames have a few drawbacks. They must be constructed and destroyed, which takes both time and code. They are so easy to use that they tend to bias the assembly language programmer in favor of accessing memory variables more often than might be necessary. Finally, you cannot use BP as a general-purpose register if you intend to access a stack frame, and having that seventh register available is sometimes useful indeed.
|
||||
</P>
|
||||
<P>That doesn’t mean you shouldn’t use stack frames, which are useful and often necessary. Just don’t fall victim to their undeniable charms.</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Torn Between Two Segments</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Torn Between Two Segments</H3>
|
||||
<P>C compilers are not terrific at handling segments. Some compilers can efficiently handle a single far pointer used in a loop by leaving ES set for the duration of the loop. But two far pointers used in the same loop confuse every compiler I’ve seen, causing the full segment:offset address to be reloaded each time either pointer is used.
|
||||
</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>This particularly affects performance in 286 protected mode (under OS/2 1.X or the Rational DOS Extender, for example) because segment loads in protected mode take a minimum of 17 cycles, versus a mere 2 cycles in real mode. </I></SMALL>
|
||||
</TABLE>
|
||||
<P>In assembly language you have full control over segments. Use it, and, if necessary, reorganize your code to minimize segment loading.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Why Speeding Up Is Hard to Do</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Why Speeding Up Is Hard to Do</H4>
|
||||
<P>You might think that the most obvious advantage assembly language has over C is that it allows the use of all forms of instructions and all registers in all ways, whereas C compilers tend to use a subset of registers and instructions in a limited number of ways. Yes and no. It’s true that C compilers typically don’t generate instructions such as <B>XLAT,</B> rotates, or the string instructions. On the other hand, <B>XLAT</B> and rotates are useful in a limited set of circumstances, and string instructions <I>are</I> used in the C library functions. In fact, C library code is likely to be carefully optimized by experts, and may be much better than equivalent code you’d produce yourself.</P>
|
||||
<P>Am I saying that C compilers produce better code than you do? No, I’m saying that they <I>can,</I> unless you use assembly language properly. Writing code in assembly language rather than C guarantees nothing.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>You can write good assembly, bad assembly, or assembly that is virtually indistinguishable from compiled code; you are more likely than not to write the latter if you think that optimization consists of tweaking compiled C code. </I></SMALL>
|
||||
|
|
@ -56,7 +56,7 @@
|
|||
</P>
|
||||
<P>True optimization requires rethinking your code to take advantage of assembly language. A C loop that searches through an integer array for matches might compile</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/08-01.jpg',413,198 )"> --><IMG SRC="images/08-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/08-01.jpg',413,198)"> --><FONT COLOR="#000077"><B>Figure 8.1</B></FONT></A> <I>Tweaked compiler output for a loop.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/08-01.jpg',413,198)"> --><B>Figure 8.1</B></A> <I>Tweaked compiler output for a loop.</I>
|
||||
</P>
|
||||
<P>to something like Figure 8.1A. You might look at that and tweak it to the code shown in Figure 8.1B.
|
||||
</P>
|
||||
|
|
@ -69,7 +69,7 @@ jz Match
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>It’s a simple example—but, I hope, a convincing one. Stretch your brain when you optimize.
|
||||
</P>
|
||||
<H3><A NAME="Heading8"></A><FONT COLOR="#000077">Taking It to the Limit</FONT></H3>
|
||||
<H3><A NAME="Heading8"></A>Taking It to the Limit</H3>
|
||||
<P>The ultimate in assembly language optimization comes when you change the rules; that is, when you reorganize the entire program to allow the use of better assembly language code in the small section of code that most affects overall performance. For example, consider that the data searched in the last example is stored in an array of structures, with each structure in the array containing other information as well. In this situation, <B>REP SCASW</B> couldn’t be used because the data searched through wouldn’t be contiguous.</P>
|
||||
<P>However, if the need for performance in searching the array is urgent enough, there’s no reason why you can’t reorganize the data. This might mean removing the array elements from the structures and storing them in their own array so that <B>REP SCASW</B> <I>could</I> be used.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Organizing a program’s data so that the performance of the critical sections can be optimized is a key part of design, and one that’s easily shortchanged unless, during the design stage, you thoroughly understand and work to bring together your data needs, the critical sections of your program, and potential assembly language optimizations.</I></SMALL>
|
||||
|
|
@ -86,7 +86,7 @@ jz Match
|
|||
</ul>
|
||||
<P>That said, let me show some of these precepts in action.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">A C-to-Assembly Case Study</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A>A C-to-Assembly Case Study</H4>
|
||||
<P>Listing 8.1 is the sample C application I’m going to use to examine optimization in action. Listing 8.1 isn’t really complete—it doesn’t handle the “no-matches” case well, and it assumes that the sum of all matches will fit into an <B>int—</B>but it will do just fine as an optimization example.</P><P><BR></P>
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@ -100,7 +100,7 @@ jz Match
|
|||
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||||
<hr width="90%" size="1" noshade>
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
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||||
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@ -162,7 +162,7 @@ unsigned int FindIDAverage(unsigned int SearchedForID,
|
|||
<!-- END CODE //-->
|
||||
<P>The main body of Listing 8.1 constructs a linked list of memory blocks of various sizes and stores an array of structures across those blocks, as shown in Figure 8.2. The function <B>FindIDAverage</B> in Listing 8.1 searches through that array for all matches to a specified ID number and returns the average value of all such matches. <B>FindIDAverage</B> contains two nested loops, the outer one repeating once for each linked block and the inner one repeating once for each array element in each block. The inner loop—the critical one—is compact, containing only four statements, and should lend itself rather well to compiler optimization.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/08-02.jpg',413,265 )"> --><IMG SRC="images/08-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/08-02.jpg',413,265)"> --><FONT COLOR="#000077"><B>Figure 8.2</B></FONT></A> <I>Linked array storage format (version 1).</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/08-02.jpg',413,265)"> --><B>Figure 8.2</B></A> <I>Linked array storage format (version 1).</I>
|
||||
</P>
|
||||
<P>As it happens, Microsoft C/C<SMALL>++</SMALL> does optimize the inner loop of <B>FindIDAverage</B> nicely. Listing 8.2 shows the code Microsoft C/C<SMALL>++</SMALL> generates for the inner loop, consisting of a mere seven assembly language instructions inside the loop. The compiler is smart enough to convert the loop index variable, which counts up but is used for nothing but counting loops, into a count-down variable so that the <B>LOOP</B> instruction can be used.</P>
|
||||
<P><B>LISTING 8.2 L8-2.COD</B></P>
|
||||
|
|
@ -212,7 +212,7 @@ $FB264:
|
|||
|
||||
<hr width="90%" size="1" noshade>
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
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@ -258,7 +258,7 @@ _FindIDAverage ENDP
|
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|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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@ -61,7 +61,7 @@ extern unsigned int FindIDAverage2(unsigned int,
|
|||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/08-03.jpg',413,261 )"> --><IMG SRC="images/08-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/08-03.jpg',413,261)"> --><FONT COLOR="#000077"><B>Figure 8.3</B></FONT></A> <I>Linked array storage format (version 2).</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/08-03.jpg',413,261)"> --><B>Figure 8.3</B></A> <I>Linked array storage format (version 2).</I>
|
||||
</P>
|
||||
<!-- CODE //-->
|
||||
<PRE>
|
||||
|
|
@ -205,7 +205,7 @@ _FindIDAverage2 ENDP
|
|||
|
||||
<hr width="90%" size="1" noshade>
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||||
<div align="center">
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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||||
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13
09-01.html
13
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|||
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||||
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|||
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|
||||
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|
||||
<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 9<BR>Hints My Readers Gave Me
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Optimization Odds and Ends from the Field</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 9<BR>Hints My Readers Gave Me</H2>
|
||||
<H3><A NAME="Heading2"></A>Optimization Odds and Ends from the Field</H3>
|
||||
<P>Back in high school, I took a pre-calculus class from Mr. Bourgeis, whose most notable characteristics were incessant pacing and truly enormous feet. My friend Barry, who sat in the back row, right behind me, claimed that it was because of his large feet that Mr. Bourgeis was so restless. Those feet were <I>so</I> heavy, Barry hypothesized, that if Mr. Bourgeis remained in any one place for too long, the floor would give way under the strain, plunging the unfortunate teacher deep into the mantle of the Earth and possibly all the way through to China. Many amusing cartoons were drawn to this effect.</P>
|
||||
<P>Unfortunately, Barry was too busy drawing cartoons, or, alternatively, sleeping, to actually learn any math. In the long run, that didn’t turn out to be a handicap for Barry, who went on to become vice-president of sales for a ham-packing company, where presumably he was rarely called upon to derive the quadratic equation. Barry’s lack of scholarship caused some problems back then, though. On one memorable occasion, Barry was half-asleep, with his eyes open but unfocused and his chin balanced on his hand in the classic “if I fall asleep my head will fall off my hand and I’ll wake up” posture, when Mr. Bourgeis popped a killer problem:</P>
|
||||
<P>“Barry, solve this for X, please.” On the blackboard lay the equation:</P>
|
||||
|
|
@ -58,7 +57,7 @@ X - 1 = 0
|
|||
<P>“Well, I could hear the answer all the way up here. Surely you could hear it just one row away?”</P>
|
||||
<P>The class went wild. They might as well have sent us home early for all we accomplished the rest of the day.</P>
|
||||
<P>I like to think I know more about performance programming than Barry knew about math. Nonetheless, I always welcome good ideas and comments, and many readers have sent me a slew of those over the years. So in this chapter, I think I’ll return the favor by devoting a chapter to reader feedback.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">Another Look at LEA</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>Another Look at LEA</H4>
|
||||
<P>Several people have pointed out that while <B>LEA</B> is great for performing certain additions (see Chapter 6), it isn’t a perfect replacement for <B>ADD</B>. What’s the difference? <B>LEA</B>, an addressing instruction by trade, doesn’t affect the flags, while the arithmetic <B>ADD</B> instruction most certainly does. This is no problem when performing additions that involve only quantities that fit in one machine word (32 bits in 386 protected mode, 16 bits otherwise), but it renders <B>LEA</B> useless for multiword operations, which use the Carry flag to tie together partial results. For example, these instructions</P>
|
||||
<!-- CODE SNIP //-->
|
||||
<PRE>
|
||||
|
|
@ -92,7 +91,7 @@ ADDLOOP:
|
|||
<P>(Yes, I could use <B>LODSD</B> instead of <B>MOV/LEA</B>; I’m just illustrating a point here. Besides, <B>LODS</B> is only 1 cycle faster than <B>MOV/LEA</B> on the 386, and is actually more than twice as slow on the 486.) If we used <B>ADD</B> rather than <B>LEA</B> to advance the pointers, the carry from one <B>ADC</B> to the next would have to be preserved with either <B>PUSHF/POPF</B> or <B>LAHF/SAHF</B>. (Alternatively, we could use multiple <B>INC</B>s, since <B>INC</B> doesn’t affect the Carry flag.)</P>
|
||||
<P>In short, <B>LEA</B> is indeed different from <B>ADD</B>. Sometimes it’s better. Sometimes not; that’s the nature of the various instruction substitutions and optimizations that will occur to you over time. There’s no such thing as “best” instructions on the x86; it all depends on what you’re trying to do.</P>
|
||||
<P>But there sure are a lot of interesting options, aren’t there?</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading4"></A><FONT COLOR="#000077">The Kennedy Portfolio</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading4"></A>The Kennedy Portfolio</H4>
|
||||
<P>Reader John Kennedy regularly passes along intriguing assembly programming tricks, many of which I’ve never seen mentioned anywhere else. John likes to optimize for size, whereas I lean more toward speed, but many of his optimizations are good for both purposes. Here are a few of my favorites:
|
||||
</P>
|
||||
<P>John’s code for setting AX to its absolute value is:</P>
|
||||
|
|
@ -149,7 +148,7 @@ CopyDone:
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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|
||||
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||||
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10
09-02.html
10
09-02.html
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@ -24,7 +24,7 @@
|
|||
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||||
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||||
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@ -76,7 +76,7 @@ SHL AX,2 ;*64
|
|||
ADD AX,BX ;*80
|
||||
</PRE>
|
||||
<!-- END CODE SNIP //-->
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">Speeding Up Multiplication</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>Speeding Up Multiplication</H4>
|
||||
<P>That brings us to multiplication, one of the slowest of x86 operations and one that allows for considerable optimization. One way to speed up multiplication is to use shift and add, <B>LEA</B>, or a lookup table to hard-code a multiplication operation for a fixed multiplier, as shown above. Another is to take advantage of the early-out feature of the 386 (and the 486, but in the interests of brevity I’ll just say “386” from now on) by arranging your operands so that the multiplier (always the rightmost operand following <B>MUL</B> or <B>IMUL</B>) is no larger than the other operand.</P>
|
||||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP" ALIGN="LEFT"><IMG SRC="images/i.jpg"><TD WIDTH="95%" VALIGN="TOP" ALIGN="LEFT"><SMALL><I>Why? Because the 386 processes one multiplier bit per cycle and immediately ends a multiplication when all significant bits of the multiplier have been processed, so fewer cycles are required to multiply a large multiplicand times a small multiplier than a small multiplicand times a large multiplier, by a factor of about 1 cycle for each significant multiplier bit eliminated.</I></SMALL>
|
||||
</TABLE>
|
||||
|
|
@ -88,10 +88,10 @@ ADD AX,BX ;*80
|
|||
</TABLE>
|
||||
<P>All in all, <B>MUL</B> and <B>IMUL</B> are reasonable performers on the 386, no longer to be avoided in most cases—and you can help that along by arranging your code to make the smaller operand the multiplier whenever you know which operand is smaller.</P>
|
||||
<P>That doesn’t mean that your code should test and swap operands to make sure the smaller one is the multiplier; that rarely pays off. I’m speaking more of the case where you’re scaling an array up by a value that’s always in the range of, say, 2 to 10; because the scale value will always be small and the array elements may have any value, the scale value is the logical choice for the multiplier.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">Optimizing Optimized Searching</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A>Optimizing Optimized Searching</H4>
|
||||
<P>Rob Williams writes with a wonderful optimization to the <B>REPNZ SCASB-</B>based optimized searching routine I discussed in Chapter 5. As a quick refresher, I described searching a buffer for a text string as follows: Scan for the first byte of the text string with <B>REPNZ SCASB</B>, then use <B>REPZ CMPS</B> to check for a full match whenever <B>REPNZ SCASB</B> finds a match for the first character, as shown in Figure 9.1. The principle is that most buffer characters won’t match the first character of any given string, so <B>REPNZ SCASB</B>, by far the fastest way to search on the PC, can be used to eliminate most potential matches; each remaining potential match can then be checked in its entirety with <B>REPZ CMPS</B>.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/09-01.jpg',406,306 )"> --><IMG SRC="images/09-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-01.jpg',406,306)"> --><FONT COLOR="#000077"><B>Figure 9.1</B></FONT></A> <I>Simple searching method for locating a text string.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-01.jpg',406,306)"> --><B>Figure 9.1</B></A> <I>Simple searching method for locating a text string.</I>
|
||||
</P>
|
||||
<P>Rob’s revelation, which he credits without explanation to Edgar Allen Poe (search nevermore?), was that by far the slowest part of the whole deal is handling <B>REPNZ SCASB</B> matches, which require checking the remainder of the string with <B>REPZ CMPS</B> and restarting <B>REPNZ SCASB</B> if no match is found.</P>
|
||||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP" ALIGN="LEFT"><IMG SRC="images/i.jpg"><TD WIDTH="95%" VALIGN="TOP" ALIGN="LEFT"><SMALL><I>Rob points out that the number of <B>REPNZ SCASB</B> matches can easily be reduced simply by scanning for the character in the searched-for string that appears least often in the buffer being searched.</I></SMALL>
|
||||
|
|
@ -109,7 +109,7 @@ ADD AX,BX ;*80
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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|
||||
<!-- reference_subfoot = footer -->
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||||
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|||
|
|
@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=09//-->
|
||||
<!--PAGES=175-178//-->
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||||
<!--UNASSIGNED1//-->
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||||
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||||
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|
||||
|
||||
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|
||||
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||||
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|
@ -41,7 +41,7 @@
|
|||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP" ALIGN="LEFT"><IMG SRC="images/i.jpg"><TD WIDTH="95%" VALIGN="TOP" ALIGN="LEFT"><SMALL><I>The difference between Listings 9.1 and 9.2 (which gives you more than a doubling of performance) is due entirely to understanding the nature of the data being handled, and biasing the code to reflect that knowledge.</I></SMALL>
|
||||
</TABLE>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/09-02.jpg',409,306 )"> --><IMG SRC="images/09-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-02.jpg',409,306)"> --><FONT COLOR="#000077"><B>Figure 9.2</B></FONT></A> <I>Faster searching method for locating a text string.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-02.jpg',409,306)"> --><B>Figure 9.2</B></A> <I>Faster searching method for locating a text string.</I>
|
||||
</P>
|
||||
<P><B>LISTING 9.1 L9-1.ASM</B></P>
|
||||
<!-- CODE //-->
|
||||
|
|
@ -152,7 +152,7 @@ _FindStringendp
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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|
||||
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||||
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|||
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|
@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=09//-->
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||||
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||||
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||||
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|
||||
|
||||
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||||
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||||
|
|
@ -187,7 +187,7 @@ void main() {
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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|
||||
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||||
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|||
10
09-05.html
10
09-05.html
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@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=09//-->
|
||||
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||||
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||||
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||||
|
||||
<CENTER>
|
||||
<TABLE BORDER>
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||||
|
|
@ -39,7 +39,7 @@
|
|||
<P>You’ll notice that in Listing 9.2 I didn’t use a table of character frequencies in English text to determine the character for which to scan, but rather let the caller make that choice. Each buffer of bytes has unique characteristics, and English-letter frequency could well be inappropriate. What if the buffer is filled with French text? Cyrillic? What if it isn’t text that’s being searched? It might be worthwhile for an application to build a dynamic frequency table for each buffer so that the best scan character could be chosen for each search. Or perhaps not, if the search isn’t time-critical or the buffer is small.
|
||||
</P>
|
||||
<P>The point is that you can improve performance dramatically by understanding the nature of the data with which you work. (This is equally true for high-level language programming, by the way.) Listing 9.2 is very similar to and only slightly more complex than Listing 9.1; the difference lies not in elbow grease or cycle counting but in the organic integrating optimizer technology we all carry around in our heads.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Short Sorts</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Short Sorts</H4>
|
||||
<P>David Stafford (recently of Borland and Borland Japan) who happens to be one of the best assembly language programmers I’ve ever met, has written a C-callable routine that sorts an array of integers in ascending order. That wouldn’t be particularly noteworthy, except that David’s routine, shown in Listing 9.4, is exactly <I>25 bytes</I> long. Look at the code; you’ll keep saying to yourself, “But this doesn’t work...oh, yes, I guess it does.” As they say in the Prego spaghetti sauce ads, <I>it’s in there</I>—and what a job of packing. Anyway, David says that a 24-byte sort routine eludes him, and he’d like to know if anyone can come up with one.</P>
|
||||
<P><B>LISTING 9.4 L9-4.ASM</B></P>
|
||||
<!-- CODE //-->
|
||||
|
|
@ -78,12 +78,12 @@ _sort: pop dx ;get return address (entry point)
|
|||
end
|
||||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A><FONT COLOR="#000077">Full 32-Bit Division</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A>Full 32-Bit Division</H4>
|
||||
<P>One of the most annoying limitations of the x86 is that while the dividend operand to the <B>DIV</B> instruction can be 32 bits in size, both the divisor and the result must be 16 bits. That’s particularly annoying in regards to the result because sometimes you just don’t know whether the ratio of the dividend to the divisor is greater than 64K-1 or not—and if you guess wrong, you get that godawful Divide By Zero interrupt. So, what is one to do when the result might not fit in 16 bits, or when the dividend is larger than 32 bits? Fall back to a software division approach? That will work—but oh so slowly.</P>
|
||||
<P>There’s another technique that’s much faster than a pure software approach, albeit not so flexible. This technique allows arbitrarily large dividends and results, but the divisor is still limited to16 bits. That’s not perfect, but it does solve a number of problems, in particular eliminating the possibility of a Divide By Zero interrupt from a too-large result.</P>
|
||||
<P>This technique involves nothing more complicated than breaking up the division into word-sized chunks, starting with the most significant word of the dividend. The most significant word is divided by the divisor (with no chance of overflow because there are only 16 bits in each); then the remainder is prepended to the next 16 bits of dividend, and the process is repeated, as shown in Figure 9.3. This process is equivalent to dividing by hand, except that here we stop to carry the remainder manually only after each word of the dividend; the hardware divide takes care of the rest. Listing 9.5 shows a function to divide an arbitrarily large dividend by a 16-bit divisor, and Listing 9.6 shows a sample division of a large dividend. Note that the same principle can be applied to handling arbitrarily large dividends in 386 native mode code, but in that case the operation can proceed a dword, rather than a word, at a time.</P>
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/09-03.jpg',406,231 )"> --><IMG SRC="images/09-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-03.jpg',406,231)"> --><FONT COLOR="#000077"><B>Figure 9.3</B></FONT></A> <I>Fast multiword division on the 386.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-03.jpg',406,231)"> --><B>Figure 9.3</B></A> <I>Fast multiword division on the 386.</I>
|
||||
</P>
|
||||
<P>As for handling signed division with arbitrarily large dividends, that can be done easily enough by remembering the signs of the dividend and divisor, dividing the absolute value of the dividend by the absolute value of the divisor, and applying the stored signs to set the proper signs for the quotient and remainder. There may be more clever ways to produce the same result, by using <B>IDIV</B>, for example; if you know of one, drop me a line c/o Coriolis Group Books.</P><P><BR></P>
|
||||
<CENTER>
|
||||
|
|
@ -98,7 +98,7 @@ _sort: pop dx ;get return address (entry point)
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
<!-- all of the reference materials (books) have the footer and subfoot reveresed -->
|
||||
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||||
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|||
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@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=09//-->
|
||||
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|
||||
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|
||||
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||||
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|
||||
|
||||
<CENTER>
|
||||
<TABLE BORDER>
|
||||
|
|
@ -128,7 +128,7 @@ main() {
|
|||
}
|
||||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">Sweet Spot Revisited</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A>Sweet Spot Revisited</H4>
|
||||
<P>Way back in Volume 1, Number 1 of <I>PC TECHNIQUES</I>, (April/May 1990) I wrote the very first of that magazine’s HAX (#1), which extolled the virtues of placing your most commonly-used automatic (stack-based) variables within the stack’s “sweet spot,” the area between +127 to -128 bytes away from BP, the stack frame pointer. The reason was that the 8088 can store addressing displacements that fall within that range in a single byte; larger displacements require a full word of storage, increasing code size by a byte per instruction, and thereby slowing down performance due to increased instruction fetching time.</P>
|
||||
<P>This takes on new prominence in 386 native mode, where straying from the sweet spot costs not one, but two or three bytes. Where the 8088 had two possible displacement sizes, either byte or word, on the 386 there are three possible sizes: byte, word, or dword. In native mode (32-bit protected mode), however, a prefix byte is needed in order to use a word-sized displacement, so a variable located outside the sweet spot requires either two extra bytes (an extra displacement byte plus a prefix byte) or three extra bytes (a dword displacement rather than a byte displacement). Either way, instructions grow alarmingly.</P>
|
||||
<P>Performance may or may not suffer from missing the sweet spot, depending on the processor, the memory architecture, and the code mix. On a 486, prefix bytes often cost a cycle; on a 386SX, increased code size often slows performance because instructions must be fetched through the half-pint 16-bit bus; on a 386, the effect depends on the instruction mix and whether there’s a cache.</P>
|
||||
|
|
@ -148,7 +148,7 @@ main() {
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
<!-- all of the reference materials (books) have the footer and subfoot reveresed -->
|
||||
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||||
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|
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12
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@ -24,7 +24,7 @@
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|||
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||||
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|
|||
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|
||||
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|
||||
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|
||||
<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">Hard-Core Cycle Counting</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading10"></A>Hard-Core Cycle Counting</H4>
|
||||
<P>Next, we come to an item that cycle counters will love, especially since it involves apparently incorrect documentation on Intel’s part. According to Intel’s documents, all <B>RCR</B> and <B>RCL</B> instructions, which perform rotations through the Carry flag, as shown in Figure 9.4, take 9 cycles on the 386 when working with a register operand. My measurements indicate that the 9-cycle execution time almost holds true for <I>multibit</I> rotate-through-carries, which I’ve timed at 8 cycles apiece; for example, <B>RCR AX,CL</B> takes 8 cycles on <I>my</I> 386, as does <B>RCL DX,2</B>. Contrast that with <B>ROR</B> and <B>ROL</B>, which can rotate the contents of a register any number of bits in just 3 cycles.</P>
|
||||
<P>However, rotating by one bit through the Carry flag does <I>not</I> take 9 cycles, contrary to Intel’s <I>80386 Programmer’s Reference Manual</I>, or even 8 cycles. In fact, <B>RCR</B> <I>reg</I>,1 and <B>RCL</B> <I>reg</I>,1 take 3 cycles, just like <B>ROR, ROL, SHR,</B> and <B>SHL</B>. At least, that’s how fast they run on my 386, and I very much doubt that you’ll find different execution times on other 386s. (Please let me know if you do, though!)</P>
|
||||
<P><A NAME="Fig4"><!-- </A><A HREF="javascript:displayWindow('images/09-04.jpg',413,249 )"> --><IMG SRC="images/09-04.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-04.jpg',413,249)"> --><FONT COLOR="#000077"><B>Figure 9.4</B></FONT></A> <I>Performing rotate instructions using the Carry flag.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/09-04.jpg',413,249)"> --><B>Figure 9.4</B></A> <I>Performing rotate instructions using the Carry flag.</I>
|
||||
</P>
|
||||
<P>Interestingly, according to Intel’s <I>i486 Microprocessor Programmer’s Reference Manual</I>, the 486 can <B>RCR</B> or <B>RCL</B> a register by one bit in 3 cycles, but takes between 8 and 30 cycles to perform a multibit register <B>RCR</B> or <B>RCL</B>!</P>
|
||||
<P>No great lesson here, just a caution to be leery of multibit <B>RCR</B> and <B>RCL</B> when performance matters—and to take cycle-time documentation with a grain of salt.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading11"></A><FONT COLOR="#000077">Hardwired Far Jumps</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading11"></A>Hardwired Far Jumps</H4>
|
||||
<P>Did you ever wonder how to code a far jump to an absolute address in assembly language? Probably not, but if you ever do, you’re going to be glad for this next item, because the obvious solution doesn’t work. You might think all it would take to jump to, say, 1000:5 would be <B>JMP FAR PTR 1000:5</B>, but you’d be wrong. That won’t even assemble. You might then think to construct in memory a far pointer containing 1000:5, as in the following:</P>
|
||||
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|
||||
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|
||||
|
|
@ -82,7 +82,7 @@ start:
|
|||
<P>By the way, if you’re wondering how I figured this out, I merely applied my good friend Dan Illowsky’s long-standing rule for dealing with MASM:
|
||||
</P>
|
||||
<P>If the obvious doesn’t work (and it usually doesn’t), just try everything you can think of, no matter how ridiculous, until you find something that does—a rule with plenty of history on its side.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading12"></A><FONT COLOR="#000077">Setting 32-Bit Registers: Time versus Space</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading12"></A>Setting 32-Bit Registers: Time versus Space</H4>
|
||||
<P>To finish up this chapter, consider these two items. First, in 32-bit protected mode,
|
||||
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|
||||
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||||
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|
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|
|||
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||||
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 10<BR>Patient Coding, Faster Code
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">How Working Quickly Can Bring Execution to a Crawl</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 10<BR>Patient Coding, Faster Code</H2>
|
||||
<H3><A NAME="Heading2"></A>How Working Quickly Can Bring Execution to a Crawl</H3>
|
||||
<P>My grandfather does <I>The New York Times</I> crossword puzzle every Sunday. In ink. With nary a blemish.</P>
|
||||
<P>The relevance of which will become apparent in a trice.</P>
|
||||
<P>What my grandfather is, is a pattern matcher <I>par excellence</I>. You’re a pattern matcher, too. So am I. We can’t help it; it comes with the territory. Try focusing on text and not reading it. Can’t do it. Can you hear the voice of someone you know and not recognize it? I can’t. And how in the Nine Billion Names of God is it that we’re capable of instantly recognizing one face out of the thousands we’ve seen in our lifetimes—even years later, from a different angle and in different light? Although we take them for granted, our pattern-matching capabilities are surely a miracle on the order of loaves and fishes.</P>
|
||||
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@ -50,11 +49,11 @@
|
|||
</TABLE>
|
||||
<P>In this chapter, I’m going to walk you through a simple but illustrative case history that nicely points up the wisdom of delaying gratification when faced with programming problems, so that your mind has time to chew on the problems from other angles. The alternative solutions you find by doing this may seem obvious, once you’ve come up with them. They may not even differ greatly from your initial solutions. Often, however, they will be much better—and you’ll never even have the chance to decide whether they’re better or not if you take the first thing that comes into your head and run with it.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">The Case for Delayed Gratification</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>The Case for Delayed Gratification</H4>
|
||||
<P>Once upon a time, I set out to read <I>Algorithms</I>, by Robert Sedgewick (Addison-Wesley), which turned out to be a wonderful, stimulating, and most useful book, one that I recommend highly. My story, however, involves only what happened in the first 12 pages, for it was in those pages that Sedgewick discussed Euclid’s algorithm.</P>
|
||||
<P>Euclid’s algorithm (discovered by Euclid, of Euclidean geometry fame, a very long time ago, way back when computers still used core memory) is a straightforward algorithm that solves one of the simplest problems imaginable: finding the greatest common integer divisor (GCD) of two positive integers. Sedgewick points out that this is useful for reducing a fraction to its lowest terms. I’m sure it’s useful for other things, as well, although none spring to mind. (A long time ago, I wrote an article about optimizing a bit of code that wasn’t even vaguely time-critical, and got swamped with letters telling me so. I knew it wasn’t time-critical; it was just a good example. So for now, close your eyes and <I>imagine</I> that finding the GCD is not only necessary but must also be done as quickly as possible, because it’s perfect for the point I want to make here and now. Okay?)</P>
|
||||
<P>The problem at hand, then, is simply this: Find the largest integer value that evenly divides two arbitrary positive integers. That’s all there is to it. So warm up your pattern matchers...and go!</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">The Brute-Force Syndrome</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>The Brute-Force Syndrome</H3>
|
||||
<P>I have a funny feeling that you’d already figured out how to find the GCD before I even said “go.” That’s what I did when reading <I>Algorithms;</I> before I read another word, I had to figure it out for myself. Programmers are like that; give them a problem and their eyes immediately glaze over as they try to solve it before you’ve even shut your mouth. That sort of instant response can certainly be impressive, but it can backfire, too, as it did in my case.</P>
|
||||
<P>You see, I fell victim to a common programming pitfall, the “brute-force” syndrome. The basis of this syndrome is that there are many problems that have obvious, brute-force solutions—with one small drawback. The drawback is that if you were to try to apply a brute-force solution by hand—that is, work a single problem out with pencil and paper or a calculator—it would generally require that you have the patience and discipline to work on the problem for approximately seven hundred years, not counting eating and sleeping, in order to get an answer. Finding all the prime numbers less than 1,000,000 is a good example; just divide each number up to 1,000,000 by every lesser number, and see what’s left standing. For most of the history of humankind, people were forced to think of cleverer solutions, such as the Sieve of Eratosthenes (we’d have been in big trouble if the ancient Greeks had had computers), mainly because after about five minutes of brute force-type work, people’s attention gets diverted to other important matters, such as how far a paper airplane will fly from a second-story window.</P><P><BR></P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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||||
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@ -41,7 +41,7 @@
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|||
<P>The solution that I instantly came up with to finding the GCD is about as brute- force as you can get: Divide both the larger integer (iL) and the smaller integer (iS) by every integer equal to or less than the smaller integer, until a number is found that divides both evenly, as shown in Figure 10.1. This works, but it’s a lousy solution, requiring as many as iS*2 divisions; <I>very</I> expensive, especially for large values of iS. For example, finding the GCD of 30,001 and 30,002 would require 60,002 divisions, which alone, disregarding tests and branches, would take about 2 seconds on an 8088, and more than 50 milliseconds even on a 25 MHz 486—a <I>very</I> long time in computer years, and not insignificant in human years either.</P>
|
||||
<P>Listing 10.1 is an implementation of the brute-force approach to GCD calculation. Table 10.1 shows how long it takes this approach to find the GCD for several integer pairs. As expected, performance is extremely poor when iS is large.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/10-01.jpg',411,233 )"> --><IMG SRC="images/10-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/10-01.jpg',411,233)"> --><FONT COLOR="#000077"><B>Figure 10.1</B></FONT></A> <I>Using a brute-force algorithm to find a GCD.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/10-01.jpg',411,233)"> --><B>Figure 10.1</B></A> <I>Using a brute-force algorithm to find a GCD.</I>
|
||||
</P>
|
||||
<TABLE WIDTH="100%">
|
||||
<TR>
|
||||
|
|
@ -136,7 +136,7 @@ unsigned int gcd(unsigned int int1, unsigned int int2) {
|
|||
}
|
||||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">Wasted Breakthroughs</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>Wasted Breakthroughs</H4>
|
||||
<P>Sedgewick’s first solution to the GCD problem was pretty much the one I came up with. He then pointed out that the GCD of iL and iS is the same as the GCD of iL-iS and iS. This was obvious (once Sedgewick pointed it out); by the very nature of division, any number that divides iL evenly nL times and iS evenly nS times must divide iL-iS evenly nL-nS times. Given that insight, I immediately designed a new, faster approach, shown in Listing 10.2.
|
||||
</P>
|
||||
<P><B>LISTING 10.2 L10-2.C</B></P>
|
||||
|
|
@ -186,7 +186,7 @@ unsigned int gcd(unsigned int int1, unsigned int int2) {
|
|||
|
||||
<hr width="90%" size="1" noshade>
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<div align="center">
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
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||||
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||||
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12
10-03.html
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|||
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||||
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@ -38,7 +38,7 @@
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|||
<P><BR></P>
|
||||
<P>Listing 10.2 repeatedly subtracts iS from iL until iL becomes less than or equal to iS. If iL becomes equal to iS, then that’s the GCD; alternatively, if iL becomes <I>less</I> than iS, iL and iS switch values, and the process is repeated, as shown in Figure 10.2. The number of iterations this approach requires relative to Listing 10.1 depends heavily on the values of iL and iS, so it’s not always faster, but, as Table 10.1 indicates, Listing 10.2 is generally much better code.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/10-02.jpg',415,306 )"> --><IMG SRC="images/10-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/10-02.jpg',415,306)"> --><FONT COLOR="#000077"><B>Figure 10.2</B></FONT></A> <I>Using repeated subtraction algorithm to find a GCD.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/10-02.jpg',415,306)"> --><B>Figure 10.2</B></A> <I>Using repeated subtraction algorithm to find a GCD.</I>
|
||||
</P>
|
||||
<P>Listing 10.2 is a far graver misstep than Listing 10.1, for all that it’s faster. Listing 10.1 is obviously a hacked-up, brute-force approach; no one could mistake it for anything else. It could be speeded up in any of a number of ways with a little thought. (Simply skipping testing all the divisors between iS and iS/2, not inclusive, would cut the worst-case time in half, for example; that’s not a particularly <I>good</I> optimization, but it illustrates how easily Listing 10.1 can be improved.) Listing 10.1 is a hack job, crying out for inspiration.</P>
|
||||
<P>Listing 10.2, on the other hand, has gotten the inspiration—and largely wasted it through haste. Had Sedgewick not told me otherwise, I might well have assumed that Listing 10.2 was optimized, a mistake I would never have made with Listing 10.1. I experienced a conceptual breakthrough when I understood Sedgewick’s point: A smaller number can be subtracted from a larger number without affecting their GCD, thereby inexpensively reducing the scale of the problem. And, in my hurry to make this breakthrough reality, I missed its full scope. As Sedgewick says on the very next page, the number that one gets by subtracting iS from iL until iL is less than iS is precisely the same as the remainder that one gets by dividing iL by iS—again, this is inherent in the nature of division—and <I>that</I> is the basis for Euclid’s algorithm, shown in Figure 10.3. Listing 10.3 is an implementation of Euclid’s algorithm.</P>
|
||||
|
|
@ -94,11 +94,11 @@ static unsigned int gcd_recurs(unsigned int larger_int,
|
|||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP"><IMG SRC="images/i.jpg"><TD WIDTH="95%"><SMALL><I>Had I been implementing GCD determination without Sedgewick’s help, I would surely not have settled for Listing 10.1—but I might well have ended up with Listing 10.2 in my enthusiasm over the “brilliant” discovery of subtracting the lesser Using Euclid’s algorithm to find a GCD number from the greater. In a commercial product, my lack of patience and discipline could have been costly indeed.</I></SMALL>
|
||||
</TABLE>
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/10-03.jpg',411,279 )"> --><IMG SRC="images/10-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/10-03.jpg',411,279)"> --><FONT COLOR="#000077"><B>Figure 10.3</B></FONT></A> <I>Using Euclid’s algorithm to find a GCD.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/10-03.jpg',411,279)"> --><B>Figure 10.3</B></A> <I>Using Euclid’s algorithm to find a GCD.</I>
|
||||
</P>
|
||||
<P>Give your mind time and space to wander around the edges of important programming problems before you settle on any one approach. I titled this book’s first chapter “The Best Optimizer Is between Your Ears,” and that’s still true; what’s even more true is that the optimizer between your ears does its best work not at the implementation stage, but at the very beginning, when you try to imagine how what you want to do and what a computer is capable of doing can best be brought together.
|
||||
</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Recursion</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Recursion</H3>
|
||||
<P>Euclid’s algorithm lends itself to recursion beautifully, so much so that an implementation like Listing 10.3 comes almost without thought. Again, though, take a moment to stop and consider what’s really going on, at the assembly language level, in Listing 10.3. There’s recursion and then there’s recursion; code recursion and data recursion, to be exact. Listing 10.3 is code recursion—recursion through calls—the sort most often used because it is conceptually simplest. However, code recursion tends to be slow because it pushes parameters and calls a subroutine for every iteration. Listing 10.4, which uses data recursion, is much faster and no more complicated than Listing 10.3. Actually, you could just say that Listing 10.4 uses a loop and ignore any mention of recursion; conceptually, though, Listing 10.4 performs the same recursive operations that Listing 10.3 does.
|
||||
</P>
|
||||
<P><B>LISTING 10.4 L10-4.C</B></P>
|
||||
|
|
@ -138,7 +138,7 @@ unsigned int gcd(unsigned int int1, unsigned int int2) {
|
|||
}
|
||||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Patient Optimization</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Patient Optimization</H4>
|
||||
<P>At long last, we’re ready to optimize GCD determination in the classic sense. Table 10.1 shows the performance of Listing 10.4 with and without Microsoft C/C<SMALL>++</SMALL>’s maximum optimization, and also shows the performance of Listing 10.5, an assembly language version of Listing 10.4. Sure, the optimized versions are faster than the unoptimized version of Listing 10.4—but the gains are small compared to those realized from the higher-level optimizations in Listings 10.2 through 10.4.</P><P><BR></P>
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||||
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@ -152,7 +152,7 @@ unsigned int gcd(unsigned int int1, unsigned int int2) {
|
|||
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||||
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||||
<div align="center">
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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Graphics Programming Black Book © 2001 Michael Abrash
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 11<BR>Pushing the 286 and 386
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">New Registers, New Instructions, New Timings, New Complications</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 11<BR>Pushing the 286 and 386</H2>
|
||||
<H3><A NAME="Heading2"></A>New Registers, New Instructions, New Timings, New Complications</H3>
|
||||
<P>This chapter, adapted from my earlier book <I>Zen of Assembly Language</I> (1989; now out of print), provides an overview of the 286 and 386, often contrasting those processors with the 8088. At the time I originally wrote this, the 8088 was the king of processors, and the 286 and 386 were the new kids on the block. Today, of course, all three processors are past their primes, but many millions of each are still in use, and the 386 in particular is still well worth considering when optimizing software.</P>
|
||||
<P>This chapter provides an interesting look at the evolution of the x86 architecture, to a greater degree than you might expect, for the x86 family came into full maturity with the 386; the 486 and the Pentium are really nothing more than faster 386s, with very little in the way of new functionality. In contrast, the 286 added a number of instructions, respectable performance, and protected mode to the 8088’s capabilities, and the 386 added more instructions and a whole new set of addressing modes, and brought the x86 family into the 32-bit world that represents the future (and, increasingly, the present) of personal computing. This chapter also provides insight into the effects on optimization of the variations in processors and memory architectures that are common in the PC world. So, although the 286 and 386 no longer represent the mainstream of computing, this chapter is a useful mix of history lesson, x86 overview, and details on two workhorse processors that are still in wide use.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">Family Matters</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>Family Matters</H4>
|
||||
<P>While the x86 family is a large one, only a few members of the family—which includes the 8088, 8086, 80188, 80186, 286, 386SX, 386DX, numerous permutations of the 486, and now the Pentium—really matter.
|
||||
</P>
|
||||
<P>The 8088 is now all but extinct in the PC arena. The 8086 was used fairly widely for a while, but has now all but disappeared. The 80186 and 80188 never really caught on for use in PC and don’t require further discussion.</P>
|
||||
|
|
@ -49,7 +48,7 @@
|
|||
<P>I’m not going to discuss the 386SX in detail. If you do find yourself programming for the 386SX, follow the same general rules you should follow for the 8088: use short instructions, use the registers as heavily as possible, and don’t branch. In other words, avoid memory, since the 386SX is by definition better at processing data internally than it is at accessing memory.</P>
|
||||
<P>The 486 is a world unto itself for the purposes of optimization, and the Pentium is a <I>universe</I> unto itself. We’ll treat them separately in later chapters.</P>
|
||||
<P>This leaves us with just two processors: the 286 and the 386. Each was <I>the</I> PC standard in its day. The 286 is no longer used in new systems, but there are millions of 286-based systems still in daily use. The 386 is still being used in new systems, although it’s on the downhill leg of its lifespan, and it is in even wider use than the 286. The future clearly belongs to the 486 and Pentium, but the 286 and 386 are still very much a part of the present-day landscape.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading4"></A><FONT COLOR="#000077">Crossing the Gulf to the 286 and the 386</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading4"></A>Crossing the Gulf to the 286 and the 386</H4>
|
||||
<P>Apart from vastly improved performance, the biggest difference between the 8088 and the 286 and 386 (as well as the later Intel CPUs) is that the 286 introduced protected mode, and the 386 greatly expanded the capabilities of protected mode. We’re only going to talk about real-mode operation of the 286 and 386 in this book, however. Protected mode offers a whole new memory management scheme, one that isn’t supported by the 8088. Only code specifically written for protected mode can run in that mode; it’s an alien and hostile environment for MS-DOS programs.
|
||||
</P>
|
||||
<P>In particular, segments are different creatures in protected mode. They’re <I>selectors</I>—indexes into a table of segment descriptors—rather than plain old registers, and can’t be set to arbitrary values. That means that segments can’t be used for temporary storage or as part of a fast indivisible 32-bit load from memory, as in</P>
|
||||
|
|
@ -69,7 +68,7 @@ mov dx,word ptr [LongVar+2]
|
|||
<P>Protected mode uses those altered segment registers to offer access to a great deal more memory than real mode: The 286 supports 16 megabytes of memory, while the 386 supports 4 gigabytes (4K megabytes) of physical memory and 64 <I>terabytes</I> (64K gigabytes!) of virtual memory.</P>
|
||||
<P>In protected mode, your programs generally run under an operating system (OS/2, Unix, Windows NT or the like) that exerts much more control over the computer than does MS-DOS. Protected mode operating systems can generally run multiple programs simultaneously, and the performance of any one program may depend far less on code quality than on how efficiently the program uses operating system services and how often and under what circumstances the operating system preempts the program. Protected mode programs are often mostly collections of operating system calls, and the performance of whatever code <I>isn’t</I> operating-system oriented may depend primarily on how large a time slice the operating system gives that code to run in.</P>
|
||||
<P>In short, taken as a whole, protected mode programming is a different kettle of fish altogether from what I’ve been describing in this book. There’s certainly a knack to optimizing specifically for protected mode under a given operating system...but it’s not what we’ve been learning, and now is not the time to pursue it further. In general, though, the optimization strategies discussed in this book still hold true in protected mode; it’s just issues specific to protected mode or a particular operating system that we won’t discuss.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">In the Lair of the Cycle-Eaters, Part II</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>In the Lair of the Cycle-Eaters, Part II</H4>
|
||||
<P>Under the programming interface, the 286 and 386 differ considerably from the 8088. Nonetheless, with one exception and one addition, the cycle-eaters remain much the same on computers built around the 286 and 386. Next, we’ll review each of the familiar cycle-eaters I covered in Chapter 4 as they apply to the 286 and 386, and we’ll look at the new member of the gang, the data alignment cycle-eater.
|
||||
</P>
|
||||
<P>The one cycle-eater that vanishes on the 286 and 386 is the 8-bit bus cycle-eater. The 286 is a 16-bit processor both internally and externally, and the 386 is a 32-bit processor both internally and externally, so the Execution Unit/Bus Interface Unit size mismatch that plagues the 8088 is eliminated. Consequently, there’s no longer any need to use byte-sized memory variables in preference to word-sized variables, at least so long as word-sized variables start at even addresses, as we’ll see shortly. On the other hand, access to byte-sized variables still isn’t any <I>slower</I> than access to word-sized variables, so you can use whichever size suits a given task best.</P><P><BR></P>
|
||||
|
|
@ -85,7 +84,7 @@ mov dx,word ptr [LongVar+2]
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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@ -42,7 +42,7 @@
|
|||
<P>After a branch it <I>does</I> matter how fast the queue can refill, and there we come to the second reason the prefetch queue cycle-eater lives on: The 286 and 386 are so fast that sometimes the Execution Unit can execute instructions faster than they can be fetched, even though instruction fetching is <I>much</I> faster on the 286 and 386 than on the 8088.</P>
|
||||
<P>(All other things being equal, too-slow instruction fetching is more of a problem on the 286 than on the 386, since the 386 fetches 4 instruction bytes at a time versus the 2 instruction bytes fetched per memory access by the 286. However, the 386 also typically runs at least twice as fast as the 286, meaning that the 386 can easily execute instructions faster than they can be fetched unless very high-speed memory is used.)</P>
|
||||
<P>The most significant reason that the prefetch queue cycle-eater not only survives but prospers on the 286 and 386, however, lies in the various memory architectures used in computers built around the 286 and 386. Due to the memory architectures, the 8-bit bus cycle-eater is replaced by a new form of the wait state cycle-eater: wait states on accesses to normal system memory.</P>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading6"></A><FONT COLOR="#000077">System Wait States</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading6"></A>System Wait States</H4>
|
||||
<P>The 286 and 386 were designed to lose relatively little performance to the prefetch queue cycle-eater...<I>when used with zero-wait-state memory:</I> memory that can complete memory accesses so rapidly that no wait states are needed. However, true zero-wait-state memory is almost never used with those processors. Why? Because memory that can keep up with a 286 is fairly expensive, and memory that can keep up with a 386 is <I>very</I> expensive. Instead, computer designers use alternative memory architectures that offer more performance for the dollar—but less performance overall—than zero-wait-state memory. (It <I>is</I> possible to build zero-wait-state systems for the 286 and 386; it’s just so expensive that it’s rarely done.)</P>
|
||||
<P>The IBM AT and true compatibles use one-wait-state memory (some AT clones use zero-wait-state memory, but such clones are less common than one-wait-state AT clones). The 386 systems use a wide variety of memory systems—including high-speed caches, interleaved memory, and static-column RAM—that insert anywhere from 0 to about 5 wait states (and many more if 8 or 16-bit memory expansion cards are used); the exact number of wait states inserted at any given time depends on the interaction between the code being executed and the memory system it’s running on.</P>
|
||||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP" ALIGN="LEFT"><IMG SRC="images/i.jpg"><TD WIDTH="95%" ALIGN="LEFT" VALIGN="TOP"><SMALL><I>The performance of most 386 memory systems can vary greatly from one memory access to another, depending on factors such as what data happens to be in the cache and which interleaved bank and/or RAM column was accessed last.</I></SMALL>
|
||||
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|
@ -90,7 +90,7 @@ Skip:
|
|||
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||||
<hr width="90%" size="1" noshade>
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
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Graphics Programming Black Book © 2001 Michael Abrash
|
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10
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@ -55,7 +55,7 @@
|
|||
</ul>
|
||||
<P>Of course, those are exactly the rules that apply to 8088 optimization as well. Isn’t it convenient that the same general rules apply across the board?
|
||||
</P>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading7"></A><FONT COLOR="#000077">Data Alignment</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading7"></A>Data Alignment</H4>
|
||||
<P>Thanks to its 16-bit bus, the 286 can access word-sized memory variables just as fast as byte-sized variables. There’s a catch, however: That’s only true for word-sized variables that start at even addresses. When the 286 is asked to perform a word-sized access starting at an odd address, it actually performs two separate accesses, each of which fetches 1 byte, just as the 8088 does for all word-sized accesses.
|
||||
</P>
|
||||
<P>Figure 11.1 illustrates this phenomenon. The conversion of word-sized accesses to odd addresses into double byte-sized accesses is transparent to memory-accessing instructions; all any instruction knows is that the requested word has been accessed, no matter whether 1 word-sized access or 2 byte-sized accesses were required to accomplish it.</P>
|
||||
|
|
@ -65,7 +65,7 @@
|
|||
<P>That, in a nutshell, is the data alignment cycle-eater, the one new cycle-eater of the 286 and 386. (The data alignment cycle-eater is a close relative of the 8088’s 8-bit bus cycle-eater, but since it behaves differently—occurring only at odd addresses—and is avoided with a different workaround, we’ll consider it to be a new cycle-eater.)
|
||||
</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/11-01.jpg',409,328 )"> --><IMG SRC="images/11-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-01.jpg',409,328)"> --><FONT COLOR="#000077"><B>Figure 11.1</B></FONT></A> <I>The data alignment cycle-eater.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-01.jpg',409,328)"> --><B>Figure 11.1</B></A> <I>The data alignment cycle-eater.</I>
|
||||
</P>
|
||||
<P>The way to deal with the data alignment cycle-eater is straightforward: <I>Don’t perform word-sized accesses to odd addresses on the 286 if you can help it</I>. The easiest way to avoid the data alignment cycle-eater is to place the directive <B>EVEN</B> before each of your word-sized variables. <B>EVEN</B> forces the offset of the next byte assembled to be even by inserting a <B>NOP</B> if the current offset is odd; consequently, you can ensure that any word-sized variable can be accessed efficiently by the 286 simply by preceding it with <B>EVEN</B>.</P>
|
||||
<P>Listing 11.2, which accesses memory a word at a time with each word starting at an odd address, runs on a 10 MHz AT clone in 1.27 ms per repetition of <B>MOVSW</B>, or 0.64 ms per word-sized memory access. That’s 6-plus cycles per word-sized access, which breaks down to two separate memory accesses—3 cycles to access the high byte of each word and 3 cycles to access the low byte of each word, the inevitable result of non-word-aligned word-sized memory accesses—plus a bit extra for DRAM refresh.</P>
|
||||
|
|
@ -115,7 +115,7 @@ Skip:
|
|||
<!-- END CODE //-->
|
||||
<P>The data alignment cycle-eater has intriguing implications for speeding up 286/386 code. The expenditure of a little care and a few bytes to make sure that word-sized variables and memory blocks are word-aligned can literally double the performance of certain code running on the 286. Even if it doesn’t double performance, word alignment usually helps and never hurts.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A><FONT COLOR="#000077">Code Alignment</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A>Code Alignment</H4>
|
||||
<P>Lack of word alignment can also interfere with instruction fetching on the 286, although not to the extent that it interferes with access to word-sized memory variables. The 286 prefetches instructions a word at a time; even if a given instruction doesn’t begin at an even address, the 286 simply fetches the first byte of that instruction at the same time that it fetches the last byte of the previous instruction, as shown in Figure 11.2, then separates the bytes internally. That means that in most cases, instructions run just as fast whether they’re word-aligned or not.
|
||||
</P>
|
||||
<P>There is, however, a non-word-alignment penalty on <I>branches</I> to odd addresses. On a branch to an odd address, the 286 is only able to fetch 1 useful byte with the first instruction fetch following the branch, as shown in Figure 11.3. In other words, lack of word alignment of the target instruction for any branch effectively cuts the instruction-fetching power of the 286 in half for the first instruction fetch after that branch. While that may not sound like much, you’d be surprised at what it can do to tight loops; in fact, a brief story is in order.</P><P><BR></P>
|
||||
|
|
@ -131,7 +131,7 @@ Skip:
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|||
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||||
<hr width="90%" size="1" noshade>
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||||
<div align="center">
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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16
11-04.html
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|
|
@ -49,10 +49,10 @@ LoopTop:
|
|||
</PRE>
|
||||
<!-- END CODE SNIP //-->
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/11-02.jpg',406,204 )"> --><IMG SRC="images/11-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-02.jpg',406,204)"> --><FONT COLOR="#000077"><B>Figure 11.2</B></FONT></A> <I>Word-aligned prefetching on the 286. </I>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-02.jpg',406,204)"> --><B>Figure 11.2</B></A> <I>Word-aligned prefetching on the 286. </I>
|
||||
</P>
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/11-03.jpg',408,240 )"> --><IMG SRC="images/11-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-03.jpg',408,240)"> --><FONT COLOR="#000077"><B>Figure 11.3</B></FONT></A> <I>How instruction bytes are fetched after a branch.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-03.jpg',408,240)"> --><B>Figure 11.3</B></A> <I>How instruction bytes are fetched after a branch.</I>
|
||||
</P>
|
||||
<P>Now, this code <I>should</I> run in, say, about 12 cycles per loop at most. Instead, it took over 14 cycles per loop, an execution time that I could not explain in any way. After rolling it around in my head for a while, I took a look at the code under a debugger...and the answer leaped out at me. <I>The loop began at an odd address!</I> That meant that two instruction fetches were required each time through the loop; one to get the opcode byte of the <B>LOOP</B> instruction, which resided at the end of one word-aligned word, and another to get the displacement byte, which resided at the start of the next word-aligned word.</P>
|
||||
<P>One simple change brought the execution time down to a reasonable 12.5 cycles per loop:</P>
|
||||
|
|
@ -80,22 +80,22 @@ FindChar proc near
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>In my experience, this simple practice is the one form of code alignment that consistently provides a reasonable return for bytes and effort expended, although sometimes it also pays to word-align tight time-critical loops.
|
||||
</P>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading9"></A><FONT COLOR="#000077">Alignment and the 386</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading9"></A>Alignment and the 386</H4>
|
||||
<P>So far we’ve only discussed alignment as it pertains to the 286. What, you may well ask, of the 386?
|
||||
</P>
|
||||
<P>The 386 adds the issue of <I>doubleword</I> alignment (that is, alignment to addresses that are multiples of four.) The rule for the 386 is: Word-sized memory accesses should be word-aligned (it’s impossible for word-aligned word-sized accesses to cross doubleword boundaries), and doubleword-sized memory accesses should be doubleword-aligned. However, in real (as opposed to 32-bit protected) mode, doubleword-sized memory accesses are rare, so the simple word-alignment rule we’ve developed for the 286 serves for the 386 in real mode as well.</P>
|
||||
<P>As for code alignment...the subroutine-start word-alignment rule of the 286 serves reasonably well there too since it avoids the worst case, where just 1 byte is fetched on entry to a subroutine. While optimum performance would dictate doubleword alignment of subroutines, that takes 3 bytes, a high price to pay for an optimization that improves performance <I>only</I> on the post 286 processors.</P>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading10"></A><FONT COLOR="#000077">Alignment and the Stack</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading10"></A>Alignment and the Stack</H4>
|
||||
<P>One side-effect of the data alignment cycle-eater of the 286 and 386 is that you should <I>never</I> allow the stack pointer to become odd. (You can make the stack pointer odd by adding an odd value to it or subtracting an odd value from it, or by loading it with an odd value.) An odd stack pointer on the 286 or 386 (or a non-doubleword-aligned stack in 32-bit protected mode on the 386, 486, or Pentium) will significantly reduce the performance of <B>PUSH,</B> <B>POP,</B> <B>CALL</B>, and <B>RET</B>, as well as <B>INT</B> and <B>IRET</B>, which are executed to invoke DOS and BIOS functions, handle keystrokes and incoming serial characters, and manage the mouse. I know of a Forth programmer who vastly improved the performance of a complex application on the AT simply by forcing the Forth interpreter to maintain an even stack pointer at all times.</P>
|
||||
<P>An interesting corollary to this rule is that you shouldn’t <B>INC SP</B> twice to add 2, even though that takes fewer bytes than <B>ADD SP,2</B>. The stack pointer is odd between the first and second <B>INC</B>, so any interrupt occurring between the two instructions will be serviced more slowly than it normally would. The same goes for decrementing twice; use <B>SUB SP,2</B> instead.</P>
|
||||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP" ALIGN="LEFT"><IMG SRC="images/i.jpg"><TD WIDTH="95%" ALIGN="LEFT" VALIGN="TOP"><SMALL><I>Keep the stack pointer aligned at all times.</I></SMALL>
|
||||
</TABLE>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading11"></A><FONT COLOR="#000077">The DRAM Refresh Cycle-Eater: Still an Act of God</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading11"></A>The DRAM Refresh Cycle-Eater: Still an Act of God</H4>
|
||||
<P>The DRAM refresh cycle-eater is the cycle-eater that’s least changed from its 8088 form on the 286 and 386. In the AT, DRAM refresh uses a little over five percent of all available memory accesses, slightly less than it uses in the PC, but in the same ballpark. While the DRAM refresh penalty varies somewhat on various AT clones and 386 computers (in fact, a few computers are built around static RAM, which requires no refresh at all; likewise, caches are made of static RAM so cached systems generally suffer less from DRAM refresh), the 5 percent figure is a good rule of thumb.
|
||||
</P>
|
||||
<P>Basically, the effect of the DRAM refresh cycle-eater is pretty much the same throughout the PC-compatible world: fairly small, so it doesn’t greatly affect performance; unavoidable, so there’s no point in worrying about it anyway; and a nuisance since it results in fractional cycle counts when using the Zen timer. Just as with the PC, a given code sequence on the AT can execute at varying speeds at different times as a result of the interaction between the code and DRAM refresh.</P>
|
||||
<P>There’s nothing much new with DRAM refresh on 286/386 computers, then. Be aware of it, but don’t overly concern yourself—DRAM refresh is still an act of God, and there’s not a blessed thing you can do about it. Happily, the internal caches of the 486 and Pentium make DRAM refresh largely a performance non-issue on those processors.</P>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading12"></A><FONT COLOR="#000077">The Display Adapter Cycle-Eater</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading12"></A>The Display Adapter Cycle-Eater</H4>
|
||||
<P>Finally we come to the last of the cycle-eaters, the display adapter cycle-eater. There are two ways of looking at this cycle-eater on 286/386 computers: (1) It’s much worse than it was on the PC, or (2) it’s just about the same as it was on the PC.
|
||||
</P>
|
||||
<P>Either way, the display adapter cycle-eater is extremely bad news on 286/386 computers and on 486s and Pentiums as well. In fact, this cycle-eater on those systems is largely responsible for the popularity of VESA local bus (VLB).</P>
|
||||
|
|
@ -112,7 +112,7 @@ FindChar proc near
|
|||
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<hr width="90%" size="1" noshade>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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<P>I know that’s hard to believe, but the display adapter cycle-eater gives out just so many display memory accesses in a given time, and no more, no matter how fast the processor is. In fact, the faster the processor, the more the display adapter cycle-eater hurts the performance of instructions that access display memory. The display adapter cycle-eater is not only still present in 286/386 computers, it’s worse than ever.
|
||||
</P>
|
||||
<P>What can we do about this new, more virulent form of the display adapter cycle-eater? The workaround is the same as it was on the PC: Access display memory as little as you possibly can.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading13"></A><FONT COLOR="#000077">New Instructions and Features: The 286</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading13"></A>New Instructions and Features: The 286</H4>
|
||||
<P>The 286 and 386 offer a number of new instructions. The 286 has a relatively small number of instructions that the 8088 lacks, while the 386 has those instructions and quite a few more, along with new addressing modes and data sizes. We’ll discuss the 286 and the 386 separately in this regard.
|
||||
</P>
|
||||
<P>The 286 has a number of instructions designed for protected-mode operations. As I’ve said, we’re not going to discuss protected mode in this book; in any case, protected-mode instructions are generally used only by operating systems. (I should mention that the 286’s protected mode brings with it the ability to address 16 MB of memory, a considerable improvement over the 8088’s 1 MB. In real mode, however, programs are still limited to 1 MB of addressable memory on the 286. In either mode, each segment is still limited to 64K.)</P>
|
||||
<P>There are also a handful of 286-specific real-mode instructions, and they can be quite useful. <B>BOUND</B> checks array bounds. <B>ENTER</B> and <B>LEAVE</B> support compact and speedy stack frame construction and removal, ideal for interfacing to high-level languages such as C and Pascal (although these instructions are actually relatively slow on the 386 and its successors, and should be used with caution when performance matters). <B>INS</B> and <B>OUTS</B> are new string instructions that support efficient data transfer between memory and I/O ports. Finally, <B>PUSHA</B> and <B>POPA</B> push and pop all eight general-purpose registers.</P>
|
||||
<P>A couple of old instructions gain new features on the 286. For one, the 286 version of <B>PUSH</B> is capable of pushing a constant on the stack. For another, the 286 allows all shifts and rotates to be performed for not just 1 bit or the number of bits specified by CL, but for <I>any</I> constant number of bits.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading14"></A><FONT COLOR="#000077">New Instructions and Features: The 386</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading14"></A>New Instructions and Features: The 386</H4>
|
||||
<P>The 386 is somewhat more complex than the 286 regarding new features. Once again, we won’t discuss protected mode, which on the 386 comes with the ability to address up to 4 gigabytes per segment and 64 terabytes in all. In real mode (and in virtual-86 mode, which allows the 386 to multitask MS-DOS applications, and which is identical to real mode so far as MS-DOS programs are concerned), programs running on the 386 are still limited to 1 MB of addressable memory and 64K per segment.
|
||||
</P>
|
||||
<P>The 386 has many new instructions, as well as new registers, addressing modes and data sizes that have trickled down from protected mode. Let’s take a quick look at these new real-mode features.</P>
|
||||
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|
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|||
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<hr width="90%" size="1" noshade>
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<div align="center">
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
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Graphics Programming Black Book © 2001 Michael Abrash
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|||
<P>Finally, it’s possible in real mode to use the 386’s new addressing modes, in which <I>any</I> 32-bit general-purpose register or pair of registers can be used to address memory. What’s more, multiplication of memory-addressing registers by 2, 4, or 8 for look-ups in word, doubleword, or quadword tables can be built right into the memory addressing mode. (The 32-bit addressing modes are discussed further in later chapters.) In protected mode, these new addressing modes allow you to address a full 4 gigabytes per segment, but in real mode you’re still limited to 64K, even with 32-bit registers and the new addressing modes, unless you play some unorthodox tricks with the segment registers.</P>
|
||||
<TABLE WIDTH="100%"><TD WIDTH="5%" VALIGN="TOP" ALIGN="LEFT"><IMG SRC="images/i.jpg"><TD WIDTH="95%" ALIGN="LEFT" VALIGN="TOP"><SMALL><I>Note well: Those tricks don’t necessarily work with system software such as Windows, so I’d recommend against using them. If you want 4-gigabyte segments, use a 32-bit environment such as Win32.</I></SMALL>
|
||||
</TABLE>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading15"></A><FONT COLOR="#000077">Optimization Rules: The More Things Change...</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading15"></A>Optimization Rules: The More Things Change...</H4>
|
||||
<P>Let’s see what we’ve learned about 286/386 optimization. Mostly what we’ve learned is that our familiar PC cycle-eaters still apply, although in somewhat different forms, and that the major optimization rules for the PC hold true on ATs and 386-based computers. You won’t go wrong on any of these computers if you keep your instructions short, use the registers heavily and avoid memory, don’t branch, and avoid accessing display memory like the plague.
|
||||
</P>
|
||||
<P>Although we haven’t touched on them, repeated string instructions are still desirable on the 286 and 386 since they provide a great deal of functionality per instruction byte and eliminate both the prefetch queue cycle-eater and branching. However, string instructions are not quite so spectacularly superior on the 286 and 386 as they are on the 8088 since non-string memory-accessing instructions have been speeded up considerably on the newer processors.</P>
|
||||
<P>There’s one cycle-eater with new implications on the 286 and 386, and that’s the data alignment cycle-eater. From the data alignment cycle-eater we get a new rule: Word-align your word-sized variables, and start your subroutines at even addresses.</P>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading16"></A><FONT COLOR="#000077">Detailed Optimization</FONT></H4>
|
||||
<H4 ALIGN="CENTER"><A NAME="Heading16"></A>Detailed Optimization</H4>
|
||||
<P>While the major 8088 optimization rules hold true on computers built around the 286 and 386, many of the instruction-specific optimizations no longer hold, for the execution times of most instructions are quite different on the 286 and 386 than on the 8088. We have already seen one such example of the sometimes vast difference between 8088 and 286/386 instruction execution times: <B>MOV [WordVar],0</B>, which has an Execution Unit execution time of 20 cycles on the 8088, has an EU execution time of just 3 cycles on the 286 and 2 cycles on the 386.</P>
|
||||
<P>In fact, the performance of virtually all memory-accessing instructions has been improved enormously on the 286 and 386. The key to this improvement is the near elimination of effective address (EA) calculation time. Where an 8088 takes from 5 to 12 cycles to calculate an EA, a 286 or 386 usually takes no time whatsoever to perform the calculation. If a base+index+displacement addressing mode, such as <B>MOV AX,[WordArray+bx+si]</B>, is used on a 286 or 386, 1 cycle is taken to perform the EA calculation, but that’s both the worst case and the only case in which there’s any EA overhead at all.</P>
|
||||
<P>The elimination of EA calculation time means that the EU execution time of memory-addressing instructions is much closer to the EU execution time of register-only instructions. For instance, on the 8088 <B>ADD [WordVar],100H</B> is a 31-cycle instruction, while <B>ADD DX,100H</B> is a 4-cycle instruction—a ratio of nearly 8 to 1. By contrast, on the 286 <B>ADD [WordVar],100H</B> is a 7-cycle instruction, while <B>ADD DX,100H</B> is a 3-cycle instruction—a ratio of just 2.3 to 1.</P>
|
||||
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|||
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||||
<hr width="90%" size="1" noshade>
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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|
|||
<P>Is this always the case? No. When the prefetch queue is full, memory-accessing instructions on the 286 and 386 are much faster (relative to register-only instructions) than they are on the 8088. Given the system wait states prevalent on 286 and 386 computers, however, the prefetch queue is likely to be empty quite a bit, especially when code consisting of instructions with short EU execution times is executed. Of course, that’s just the sort of code we’re likely to write when we’re optimizing, so the performance of high-speed code is more likely to be controlled by instruction size than by EU execution time on most 286 and 386 computers, just as it is on the PC.</P>
|
||||
<P>All of which is just a way of saying that faster memory access and EA calculation notwithstanding, it’s just as desirable to keep instructions short and memory accesses to a minimum on the 286 and 386 as it is on the 8088. And the way to do that is to use the registers as heavily as possible, use string instructions, use short forms of instructions, and the like.</P>
|
||||
<P>The more things change, the more they remain the same....</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading17"></A><FONT COLOR="#000077">POPF and the 286</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading17"></A>POPF and the 286</H4>
|
||||
<P>We’ve one final 286-related item to discuss: the hardware malfunction of <B>POPF</B> under certain circumstances on the 286.</P>
|
||||
<P>The problem is this: Sometimes <B>POPF</B> permits interrupts to occur when interrupts are initially off and the setting popped into the Interrupt flag from the stack keeps interrupts off. In other words, an interrupt can happen even though the Interrupt flag is never set to 1. Now, I don’t want to blow this particular bug out of proportion. It only causes problems in code that cannot tolerate interrupts under any circumstances, and that’s a rare sort of code, especially in user programs. However, some code really does need to have interrupts absolutely disabled, with no chance of an interrupt sneaking through. For example, a critical portion of a disk BIOS might need to retrieve data from the disk controller the instant it becomes available; even a few hundred microseconds of delay could result in a sector’s worth of data misread. In this case, one misplaced interrupt during a <B>POPF</B> could result in a trashed hard disk if that interrupt occurs while the disk BIOS is reading a sector of the File Allocation Table.</P>
|
||||
<P>There is a workaround for the <B>POPF</B> bug. While the workaround is easy to use, it’s considerably slower than <B>POPF</B>, and costs a few bytes as well, so you won’t want to use it in code that can tolerate interrupts. On the other hand, in code that truly cannot be interrupted, you should view those extra cycles and bytes as cheap insurance against mysterious and erratic program crashes.</P>
|
||||
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@ -82,7 +82,7 @@ Skip:
|
|||
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||||
<hr width="90%" size="1" noshade>
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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10
11-08.html
10
11-08.html
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@ -39,7 +39,7 @@
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|||
<P>Well, there’s only one instruction other than <B>POPF</B> that loads the FLAGS register directly from the stack, and that’s <B>IRET</B>, which loads the FLAGS register from the stack as it branches, as shown in Figure 11.5. iret has no known bugs of the sort that plague <B>POPF</B>, so it’s certainly a candidate to replace popf in non-interruptible applications. Unfortunately, <B>IRET</B> loads the FLAGS register with the <I>third</I> word down on the stack, not the word on top of the stack, as is the case with <B>POPF</B>; the far return address that <B>IRET</B> pops into CS:IP lies between the top of the stack and the word popped into the FLAGS register.</P>
|
||||
<P>Obviously, the segment:offset that <B>IRET</B> expects to find on the stack above the pushed flags isn’t present when the stack is set up for <B>POPF</B>, so we’ll have to adjust the stack a bit before we can substitute <B>IRET</B> for <B>POPF</B>. What we’ll have to do is push the segment:offset of the instruction after our workaround code onto the stack right above the pushed flags. <B>IRET</B> will then branch to that address and pop the flags, ending up at the instruction after the workaround code with the flags popped. That’s just the result that would have occurred had we executed <B>POPF</B>—WITH the bonus that no interrupts can accidentally occur when the Interrupt flag is 0 both before and after the pop.</P>
|
||||
<P><A NAME="Fig4"><!-- </A><A HREF="javascript:displayWindow('images/11-04.jpg',412,383 )"> --><IMG SRC="images/11-04.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-04.jpg',412,383)"> --><FONT COLOR="#000077"><B>Figure 11.4</B></FONT></A> <I>The operation of POPF.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-04.jpg',412,383)"> --><B>Figure 11.4</B></A> <I>The operation of POPF.</I>
|
||||
</P>
|
||||
<P>How can we push the segment:offset of the next instruction? Well, finding the offset of the next instruction by performing a near call to that instruction is a tried-and-true trick. We can do something similar here, but in this case we need a far call, since <B>IRET</B> requires both a segment and an offset. We’ll also branch backward so that the address pushed on the stack will point to the instruction we want to continue with. The code works out like this:</P>
|
||||
<!-- CODE //-->
|
||||
|
|
@ -63,7 +63,7 @@ popfskip:
|
|||
</PRE>
|
||||
<!-- END CODE //-->
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<P><A NAME="Fig5"><!-- </A><A HREF="javascript:displayWindow('images/11-05.jpg',410,520 )"> --><IMG SRC="images/11-05.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-05.jpg',410,520)"> --><FONT COLOR="#000077"><B>Figure 11.5</B></FONT></A> <I>The operation of IRET.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-05.jpg',410,520)"> --><B>Figure 11.5</B></A> <I>The operation of IRET.</I>
|
||||
</P>
|
||||
<P>The operation of this code is illustrated in Figure 11.6.
|
||||
</P>
|
||||
|
|
@ -105,7 +105,7 @@ EMULATE_POPFmacro
|
|||
</PRE>
|
||||
<!-- END CODE SNIP //-->
|
||||
<P><A NAME="Fig6"><!-- </A><A HREF="javascript:displayWindow('images/11-06.jpg',409,447 )"> --><IMG SRC="images/11-06.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-06.jpg',409,447)"> --><FONT COLOR="#000077"><B>Figure 11.6</B></FONT></A> <I>Workaround code for the POPF bug.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/11-06.jpg',409,447)"> --><B>Figure 11.6</B></A> <I>Workaround code for the POPF bug.</I>
|
||||
</P>
|
||||
<P>The standard version of <B>EMULATE_POPF</B> is 6 bytes longer than <B>POPF</B> and much slower, as you’d expect given that it involves three branches. Anyone in his/her right mind would prefer <B>POPF</B> to a larger, slower, three-branch macro—given a choice. In noncode, however, there’s no choice here; the safer—if slower—approach is the best. (Having people associate your programs with crashed computers is <I>not</I> a desirable situation, no matter how unfair the circumstances under which it occurs.)</P>
|
||||
<P>And now you know the nature of and the workaround for the <B>POPF</B> bug. Whether you ever need the workaround or not, it’s a neatly packaged example of the tremendous flexibility of the x86 instruction set.</P><P><BR></P>
|
||||
|
|
@ -121,7 +121,7 @@ EMULATE_POPFmacro
|
|||
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<hr width="90%" size="1" noshade>
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<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 12<BR>Pushing the 486
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">It’s Not Just a Bigger 386</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 12<BR>Pushing the 486</H2>
|
||||
<H3><A NAME="Heading2"></A>It’s Not Just a Bigger 386</H3>
|
||||
<P>So this traveling salesman is walking down a road, and he sees a group of men digging a ditch with their bare hands. “Whoa, there!” he says. “What you guys need is a Model 8088 ditch digger!” And he whips out a trowel and sells it to them.
|
||||
</P>
|
||||
<P>A few days later, he stops back around. They’re happy with the trowel, but he sells them the latest ditch-digging technology, the Model 80286 spade. That keeps them content until he stops by again with a Model 80386 shovel (a full 32 inches wide, with a narrow point to emulate the trowel), and <I>that</I> holds them until he comes back around with what they really need: a Model 80486 bulldozer.</P>
|
||||
<P>Having reached the top of the line, the salesman doesn’t pay them a call for a while. When he does, not only are they none too friendly, but they’re digging with the 80386 shovel; the bulldozer is sitting off to one side. “Why on earth are you using that shovel?” the salesman asks. “Why aren’t you digging with the bulldozer?”</P>
|
||||
<P>“Well, Lord knows we tried,” says the foreman, “but it was all we could do just to lift the damn thing!”</P>
|
||||
<P>Substitute “processor” for the various digging implements, and you get an idea of just how different the optimization rules for the 486 are from what you’re used to. Okay, it’s not quite <I>that</I> bad—but upon encountering a processor where string instructions are often to be avoided and memory-to-register <B>MOV</B>s are frequently as fast as register-to-register <B>MOV</B>s, Dorothy was heard to exclaim (before she sank out of sight in a swirl of hopelessly mixed metaphors), “I don’t think we’re in Kansas anymore, Toto.”</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">Enter the 486</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>Enter the 486</H4>
|
||||
<P>No chip that is a direct, fully compatible descendant of the 8088, 286, and 386 could ever be called a RISC chip, but the 486 certainly contains RISC elements, and it’s those elements that are most responsible for making 486 optimization unique. Simple, common instructions are executed in a single cycle by a RISC-like core processor, but other instructions are executed pretty much as they were on the 386, where every instruction takes at least 2 cycles. For example, <B>MOV AL, [TestChar]</B> takes only 1 cycle on the 486, assuming both instruction and data are in the cache—3 cycles faster than the 386—but <B>STOSB</B> takes 5 cycles, 1 cycle <I>slower</I> than on the 386. The floating-point execution unit inside the 486 is also much faster than the 387 math coprocessor, largely because, being in the same silicon as the CPU (the 486 has a math coprocessor built in), it is more tightly coupled. The results are sometimes startling: <B>FMUL</B> (floating point multiply) is usually faster on the 486 than <B>IMUL</B> (integer multiply)!</P>
|
||||
<P>An encyclopedic approach to 486 optimization would take a book all by itself, so in this chapter I’m only going to hit the highlights of 486 optimization, touching on several optimization rules, some documented, some not. You might also want to check out the following sources of 486 information: <I>i486 Microprocessor Programmer’s Reference Manual,</I> from Intel; “8086 Optimization: Aim Down the Middle and Pray,” in the March, 1991 <I>Dr. Dobb’s Journal</I>; and “Peak Performance: On to the 486,” in the November, 1990 <I>Programmer’s Journal.</I></P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">Rules to Optimize By</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>Rules to Optimize By</H3>
|
||||
<P>In Appendix G of the <I>i486 Microprocessor Programmer</I>’<I>s</I> <I>Reference Manual</I>, Intel lists a number of optimization techniques for the 486. While neither exhaustive (we’ll look at two undocumented optimizations shortly) nor entirely accurate (we’ll correct two of the rules here), Intel’s list is certainly a good starting point. In particular, the list conveys the extent to which 486 optimization differs from optimization for earlier x86 processors. Generally, I’ll be discussing optimization for real mode (it being the most widely used mode at the moment), although many of the rules should apply to protected mode as well.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>486 optimization is generally more precise and less frustrating than optimization for other x86 processors because every 486 has an identical internal cache. Whenever both the instructions being executed and the data the instructions access are in the cache, those instructions will run in a consistent and calculatable number of cycles on all 486s, with little chance of interference from the prefetch queue and without regard to the speed of external memory.</I></SMALL>
|
||||
</TABLE>
|
||||
<P>In other words, for cached code (which time-critical code almost always is), performance is predictable and can be calculated with good precision, and those calculations will apply on any 486. However, “predictable” doesn’t mean “trivial”; the cycle times printed for the various instructions are not the whole story. You must be aware of all the rules, documented and undocumented, that go into calculating actual execution times—and uncovering some of those rules is exactly what this chapter is about.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A><FONT COLOR="#000077">The Hazards of Indexed Addressing</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading5"></A>The Hazards of Indexed Addressing</H4>
|
||||
<P>Rule #1: Avoid indexed addressing (that is, try not to use either two registers or scaled addressing to point to memory).
|
||||
</P>
|
||||
<P>Intel cautions against using indexing to address memory because there’s a one-cycle penalty for indexed addressing. True enough—but “indexed addressing” might not mean what you expect.</P>
|
||||
|
|
@ -98,7 +97,7 @@ LoopTop:
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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||||
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|||
12
12-02.html
12
12-02.html
|
|
@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=12//-->
|
||||
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||||
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||||
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|
||||
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||||
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|
@ -42,7 +42,7 @@
|
|||
<P>All this fuss over one cycle! You might well wonder how much difference one cycle could make. After all, on the 8088, effective address calculations take a <I>minimum</I> of 5 cycles. On the 486, however, 1 cycle is a big deal because many instructions, including most register-only instructions (<B>MOV</B>, <B>ADD</B>, <B>CMP</B>, and so on) execute in just 1 cycle. In particular, <B>MOV</B>s to and from memory execute in 1 cycle—if they’re not hampered by something like indexed addressing, in which case they slow to half speed (or worse, as we will see shortly).</P>
|
||||
<P>For example, consider the summing example shown earlier. The version that uses base+index ([BX+SI]) addressing executes in eight cycles per loop. As expected, the version that uses base ([SI]) addressing runs one cycle faster, at seven cycles per loop. However, the loop code executes so fast on the 486 that the single cycle saved by using base addressing makes the <I>whole loop</I> more than 14 percent faster.</P>
|
||||
<P>In a key loop on the 486, 1 cycle can indeed matter.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">Calculate Memory Pointers Ahead of Time</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading6"></A>Calculate Memory Pointers Ahead of Time</H4>
|
||||
<P>Rule #2: Don’t use a register as a memory pointer during the next two cycles after loading it.
|
||||
</P>
|
||||
<P>Intel states that if the destination of one instruction is used as the base addressing component of the next instruction, then a one-cycle penalty is imposed. This rule, unlike anything ever before seen in the x86 family, reflects the heavily pipelined nature of the 486. Apparently, the 486 starts each effective address calculation before the start of the instruction that will need it, as shown in Figure 12.1; this effectively makes the address calculation time vanish, because it happens while the preceding instruction executes.</P>
|
||||
|
|
@ -82,7 +82,7 @@ LoopTop:
|
|||
</P>
|
||||
<P>Considering that <B>MOV</B> normally takes only one cycle total, that’s quite a loss. For example, the postdecrement loop shown above is 2 full cycles faster than the preincrement loop, resulting in a 29 percent improvement in the performance of the entire loop. But wait, there’s more. If a register is loaded 2 cycles (which generally means 2 instructions, but, because some 486 instructions take more than 1 cycle,</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/12-01.jpg',407,155 )"> --><IMG SRC="images/12-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/12-01.jpg',407,155)"> --><FONT COLOR="#000077"><B>Figure 12.1</B></FONT></A> <I>One-cycle-ahead address pipelining.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/12-01.jpg',407,155)"> --><B>Figure 12.1</B></A> <I>One-cycle-ahead address pipelining.</I>
|
||||
</P>
|
||||
<P>the 2 are not always equivalent) before it’s used to point to memory, 1 cycle is lost. Therefore, whereas this code
|
||||
</P>
|
||||
|
|
@ -121,9 +121,9 @@ jnz LoopTop
|
|||
</P>
|
||||
<P>Clearly, there’s considerable optimization potential in careful rearrangement of 486 code.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/12-02.jpg',411,158 )"> --><IMG SRC="images/12-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/12-02.jpg',411,158)"> --><FONT COLOR="#000077"><B>Figure 12.2</B></FONT></A> <I>Two-cycle-ahead address pipelining.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/12-02.jpg',411,158)"> --><B>Figure 12.2</B></A> <I>Two-cycle-ahead address pipelining.</I>
|
||||
</P>
|
||||
<H3><A NAME="Heading7"></A><FONT COLOR="#000077">Caveat Programmor</FONT></H3>
|
||||
<H3><A NAME="Heading7"></A>Caveat Programmor</H3>
|
||||
<P>A caution: I’m quite certain that the 2-cycle-ahead addressing pipeline interruption penalty I’ve described exists in the two 486s I’ve tested. However, there’s no guarantee that Intel won’t change this aspect of the 486 in the future, especially given that the documentation indicates otherwise. Perhaps the 2-cycle penalty is the result of a bug in the initial steps of the 486, and will revert to the documented 1-cycle penalty someday; likewise for the undocumented optimizations I’ll describe below. Nonetheless, none of the optimizations I suggest would hurt performance even if the undocumented performance characteristics of the 486 were to vanish, and they certainly will help performance on at least some 486s right now, so I feel they’re well worth using.
|
||||
</P><P><BR></P>
|
||||
<CENTER>
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||||
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|
@ -138,7 +138,7 @@ jnz LoopTop
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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||||
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|
||||
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|||
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@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=12//-->
|
||||
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||||
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||||
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||||
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@ -38,7 +38,7 @@
|
|||
<P><BR></P>
|
||||
<P>There is, of course, no guarantee that I’m entirely correct about the optimizations discussed in this chapter. Without knowing the internals of the 486, all I can do is time code and make inferences from the results; I invite you to deduce your own rules and cross-check them against mine. Also, most likely there are other optimizations that I’m unaware of. If you have further information on these or any other undocumented optimizations, please write and let me know. And, of course, if anyone from Intel is reading this and wants to give us the gospel truth, please do!
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A><FONT COLOR="#000077">Stack Addressing and Address Pipelining</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading8"></A>Stack Addressing and Address Pipelining</H4>
|
||||
<P>Rule #2A: Rule #2 sometimes, but not always, applies to the stack pointer when it is implicitly used to point to memory.
|
||||
</P>
|
||||
<P>Intel states that the stack pointer is an implied destination register for <B>CALL</B>, <B>ENTER</B>, <B>LEAVE</B>, <B>RET</B>, <B>PUSH</B>, and <B>POP</B> (which alter (E)SP), and that it is the implied base addressing register for <B>PUSH</B>, <B>POP</B>, and <B>RET</B> (which use (E)SP to address memory). Intel then implies that the aforementioned addressing pipeline penalty is incurred whenever the stack pointer is used as a destination by one of the first set of instructions and is then immediately used to address memory by one of the second set. This raises the specter of unpleasant programming contortions such as intermixing <B>PUSH</B>es and <B>POP</B>s with other instructions to avoid interrupting the addressing pipeline. Fortunately, matters are actually not so grim as Intel’s documentation would indicate; my tests indicate that the addressing pipeline penalty pops up only spottily when the stack pointer is involved.</P>
|
||||
|
|
@ -82,7 +82,7 @@ pop ax
|
|||
<P>loses two cycles for the same reason.
|
||||
</P>
|
||||
<P>I certainly haven’t tried all possible combinations, but the results so far indicate that the stack pointer incurs the addressing pipeline penalty only if (E)SP is the <I>explicit</I> destination of one instruction and is then used by one of the two following instructions to address memory. So, for instance, SP isn’t the explicit operand of <B>POP AX—</B>AX is—and no cycles are lost if <B>POP AX</B> is followed by <B>POP</B> or <B>RET</B>. Happily, then, we need not worry about the sequence in which we use <B>PUSH</B> and <B>POP</B>. However, adding to, moving to, or subtracting from the stack pointer should ideally be done at least two cycles before <B>PUSH</B>, <B>POP</B>, <B>RET</B>, or any other instruction that uses the stack pointer to address memory.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">Problems with Byte Registers</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading9"></A>Problems with Byte Registers</H4>
|
||||
<P>There are two ways to lose cycles by using byte registers, and neither of them is documented by Intel, so far as I know. Let’s start with the lesser and simpler of the two.
|
||||
</P>
|
||||
<P>Rule #3: Do not load a byte portion of a register during one instruction, then use that register in its entirety as a source register during the next instruction.</P>
|
||||
|
|
@ -133,7 +133,7 @@ xlat
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
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||||
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||||
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|||
10
12-04.html
10
12-04.html
|
|
@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=12//-->
|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
|
|
@ -38,7 +38,7 @@
|
|||
<P><BR></P>
|
||||
<P>You don’t need to understand every corner of the 486 universe unless you’re a diehard ASMhead who does this stuff for fun. Just learn enough to be able to speed up the key portions of your programs, and spend the rest of your time on a fast design and overall implementation.
|
||||
</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">More Fun with Byte Registers</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading10"></A>More Fun with Byte Registers</H4>
|
||||
<P>Rule #4: Don’t load <I>any</I> byte register exactly 2 cycles before using <I>any</I> register to address memory.</P>
|
||||
<P>This, the last of this chapter’s rules, is the strangest of the lot. If any byte register is loaded, and then two cycles later any register is used to point to memory, one cycle is lost. So, for example, this code</P>
|
||||
<!-- CODE SNIP //-->
|
||||
|
|
@ -78,7 +78,7 @@ mov ax,[bx]
|
|||
<P>A more sophisticated programmer would expect to lose one cycle, because BX is loaded two cycles before being used to address memory. In fact, though, this code takes 5 cycles—2 cycles, or 67 percent, longer than normal. Why? Well, under normal conditions, loading a byte register—CL in this case—one cycle before using a register to address memory produces no penalty; loading 2 cycles ahead is the only case that normally incurs a penalty. However, think of Rule #4 as meaning that loading a byte register disrupts the memory addressing pipeline as it starts up. Viewed that way, we can see that <B>MOV BX,OFFSET MemVar</B> interrupts the addressing pipeline, forcing it to start again, and then, presumably, <B>MOV CL,AL</B> interrupts the pipeline again because the pipeline is now on its first cycle: the one that loading a byte register can affect.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>I know—it seems awfully complicated. It isn’t, really. Generally, try not to use byte destinations exactly two cycles before using a register to address memory, and try not to load a register either one or two cycles before using it to address memory, and you’ll be fine.</I></SMALL>
|
||||
</TABLE>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading11"></A><FONT COLOR="#000077">Timing Your Own 486 Code</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading11"></A>Timing Your Own 486 Code</H4>
|
||||
<P>In case you want to do some 486 performance analysis of your own, let me show you how I arrived at one of the above conclusions; at the same time, I can warn you of the timing hazards of the cache. Listings 12.1 and 12.2 show the code I ran through the Zen timer in order to establish the effects of loading a byte register before using a register to address memory. Listing 12.1 ran in 120 µs on a 33 MHz 486, or 4 cycles per repetition (120 µs/1000 repetitions = 120 ns per repetition; 120 ns per repetition/30 ns per cycle = 4 cycles per repetition); Listing 12.2 ran in 90 µs, or 3 cycles, establishing that loading a byte register costs a cycle only when it’s performed exactly 2 cycles before addressing memory.
|
||||
</P>
|
||||
<P><B>LISTING 12.1 LST12-1.ASM</B></P>
|
||||
|
|
@ -128,7 +128,7 @@ Done:
|
|||
<P>Note that Listings 12.1 and 12.2 each repeat the timing of the code under test a second time, to make sure that the instructions are in the cache on the second pass, the one for which results are displayed. Also note that the code is less than 8K in size, so that it can all fit in the 486’s 8K internal cache. If I double the <B>REPT</B> value in Listing 12.2 to 2,000, making the test code larger than 8K, the execution time more than doubles to 224 µs, or 3.7 cycles per repetition; the extra seven-tenths of a cycle comes from fetching non-cached instruction bytes.</P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Whenever you see non-integral timing results of this sort, it’s a good bet that the test code or data isn’t cached.</I></SMALL>
|
||||
</TABLE>
|
||||
<H3><A NAME="Heading12"></A><FONT COLOR="#000077">The Story Continues</FONT></H3>
|
||||
<H3><A NAME="Heading12"></A>The Story Continues</H3>
|
||||
<P>There’s certainly plenty more 486 lore to explore, including the 486’s unique prefetch queue, more optimization rules, branching optimizations, performance implications of the cache, the cost of cache misses for reads, and the implications of cache write-through for writes. Nonetheless, we’ve covered quite a bit of ground in this chapter, and I trust you’ve gotten a feel for the considerable extent to which 486 optimization differs from what you’re used to. Odd as 486 optimization is, though, it’s well worth mastering, for the 486 is, at its best, so staggeringly fast that carefully crafted 486 code can do more than twice as much per cycle as the best 386 code—which makes it perhaps 50 times as fast as optimized code for the original PC.
|
||||
</P>
|
||||
<P>Sometimes it <I>is</I> hard to believe we’re still in Kansas!</P><P><BR></P>
|
||||
|
|
@ -144,7 +144,7 @@ Done:
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
<!-- all of the reference materials (books) have the footer and subfoot reveresed -->
|
||||
<!-- reference_subfoot = footer -->
|
||||
|
|
|
|||
13
13-01.html
13
13-01.html
|
|
@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=13//-->
|
||||
<!--PAGES=248-251//-->
|
||||
<!--UNASSIGNED1//-->
|
||||
<!--UNASSIGNED2//--></HEAD><BODY LINK=#0000FF ALINK=#000099 VLINK=#0000FF BGCOLOR=#FFFFFF>
|
||||
<!--UNASSIGNED2//--></HEAD><body>
|
||||
|
||||
<CENTER>
|
||||
<TABLE BORDER>
|
||||
|
|
@ -36,14 +36,13 @@
|
|||
</TABLE>
|
||||
</CENTER>
|
||||
<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 13<BR>Aiming the 486
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Pipelines and Other Hazards of the High End</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 13<BR>Aiming the 486</H2>
|
||||
<H3><A NAME="Heading2"></A>Pipelines and Other Hazards of the High End</H3>
|
||||
<P>It’s a sad but true fact that 84 percent of American schoolchildren are ignorant of 92 percent of American history. Not my daughter, though. We recently visited historical Revolutionary-War-vintage Fort Ticonderoga, and she’s now 97 percent aware of a key element of our national heritage: that the basic uniform for soldiers in those days was what appears to be underwear, plus a hat so that no one could complain that they were undermining family values. Ha! Just kidding! Actually, what she learned was that in those days, it was pure coincidence if a cannonball actually hit anything it was aimed at, which isn’t surprising considering the lack of rifling, precision parts, and ballistics. The guides at the fort shot off three cannons; the closest they came to the target was about 50 feet, and that was only because the wind helped. I think the idea in early wars was just to put so much lead in the air that some of it was bound to hit <I>something;</I> preferably, but not necessarily, the enemy.</P>
|
||||
<P>Nowadays, of course, we have automatic weapons that allow a teenager to singlehandedly defeat the entire U.S. Army, not to mention so-called “smart” bombs, which are smart in the sense that they can seek out and empty a taxpayer’s wallet without being detected by radar. There’s an obvious lesson here about progress, which I leave you to deduce for yourselves.</P>
|
||||
<P>Here’s the same lesson, in another form. Ten years ago, we had a slow processor, the 8088, for which it was devilishly hard to optimize, and for which there was no good optimization documentation available. Now we have a processor, the 486, that’s 50 to 100 times faster than the 8088—and for which there is no good optimization documentation available. Sure, Intel provides a few tidbits on optimization in the back of the <I>i486 Microprocessor Programmer’s Reference Manual,</I> but, as I discussed in Chapter 12, that information is both incomplete and not entirely correct. Besides, most assembly language programmers don’t bother to read Intel’s manuals (which are extremely informative and well done, but only slightly more fun to read than the phone book), and go right on programming the 486 using outdated 8088 optimization techniques, blissfully unaware of a new and heavily mutated generation of cycle-eaters that interact with their code in ways undreamt of even on the 386.</P>
|
||||
<P>For example, consider how Terje Mathisen doubled the speed of his word-counting program on a 486 simply by shuffling a couple of instructions.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A><FONT COLOR="#000077">486 Pipeline Optimization</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading3"></A>486 Pipeline Optimization</H4>
|
||||
<P>I’ve mentioned Terje Mathisen in my writings before. Terje is an assembly language programmer extraordinaire, and author of the incredibly fast public-domain word-counting program WC (which comes complete with source code; well worth a look, if you want to see what <I>really</I> fast code looks like). Terje’s a regular participant in the ibm.pc/fast.code topic on Bix. In a thread titled “486 Pipeline Optimization, or TANSTATFC (There Ain’t No Such Thing As The Fastest Code),” he detailed the following optimization to WC, perhaps the best example of 486 pipeline optimization I’ve yet seen.</P>
|
||||
<P>Terje’s inner loop originally looked something like the code in Listing 13.1. (I’ve taken a few liberties for illustrative purposes.) Of course, Terje unrolls this loop a few times (128 times, to be exact). By the way, in Listing 13.1 you’ll notice that Terje counts not only words but also lines, at a rate of three instructions for every two characters!</P>
|
||||
<P><B>LISTING 13.1 L13-1.ASM</B></P>
|
||||
|
|
@ -58,7 +57,7 @@ add dx,[bx+8000h] ;increment word and line count
|
|||
<P>Listing 13.1 looks as tight as it could be, with just two one-cycle instructions, one two-cycle instruction, and no branches. It <I>is</I> tight, but those three instructions actually take a minimum of 8 cycles to execute, as shown in Figure 13.1. The problem is that DI is loaded just before being used to address memory, and that costs 2 cycles because it interrupts the 486’s internal instruction pipeline. Likewise, BX is loaded just before being used to address memory, costing another two cycles. Thus, this loop takes twice as long as cycle counts would seem to indicate, simply because two registers are loaded immediately before being used, disrupting the 486’s pipeline.</P>
|
||||
<P>Listing 13.2 shows Terje’s immediate response to these pipelining problems; he simply swapped the instructions that load DI and BL. This one change cut execution time per character pair from eight cycles to five cycles! The load of BL is now separated by one instruction from the use of BX to address memory, so the pipeline penalty is reduced from two cycles to one cycle. The load of DI is also separated by one instruction from the use of DI to address memory (remember, the loop is unrolled, so the last instruction is followed by the first instruction), but because the intervening instruction takes two cycles, there’s no penalty at all.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/13-01.jpg',100,65 )"> --><IMG SRC="images/13-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/13-01.jpg',100,65)"> --><FONT COLOR="#000077"><B>Figure 13.1</B></FONT></A> <I>Cycle-eaters in the original WC.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/13-01.jpg',100,65)"> --><B>Figure 13.1</B></A> <I>Cycle-eaters in the original WC.</I>
|
||||
</P>
|
||||
<TABLE WIDTH="100%">
|
||||
<TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Remember, pipeline penalties diminish with increasing number of cycles, not instructions, between the pipeline disrupter and the potentially affected instruction.</I></SMALL>
|
||||
|
|
@ -86,7 +85,7 @@ add dx,[bx+8000h] ;increment word and line count
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
<!-- all of the reference materials (books) have the footer and subfoot reveresed -->
|
||||
<!-- reference_subfoot = footer -->
|
||||
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|
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|
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@ -24,7 +24,7 @@
|
|||
<!--CHAPTER=13//-->
|
||||
<!--PAGES=252-254//-->
|
||||
<!--UNASSIGNED1//-->
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||||
<!--UNASSIGNED2//--></HEAD><BODY LINK=#0000FF ALINK=#000099 VLINK=#0000FF BGCOLOR=#FFFFFF>
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|
||||
|
||||
<CENTER>
|
||||
<TABLE BORDER>
|
||||
|
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@ -58,7 +58,7 @@ mov ax,[bx+8000h] ;get increments for next time
|
|||
<!-- END CODE SNIP //-->
|
||||
<P>I’d like to point out two fairly remarkable things. First, the single cycle that Terje saved in Listing 13.4 sped up his entire word-counting engine by 25 percent or more; Listing 13.4 is fully twice as fast as Listing 13.1—all the result of nothing more than shifting an instruction and splitting another into two operations. Second, Terje’s word-counting engine can process more than 16 million characters <I>per second</I> on a 486/33.</P>
|
||||
<P>Clever 486 optimization can pay off big. QED.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">BSWAP: More Useful Than You Might Think</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>BSWAP: More Useful Than You Might Think</H3>
|
||||
<P>There are only 3 non-system instructions unique to the 486. None is earthshaking, but they have their uses. Consider <B>BSWAP. BSWAP</B> does just what its name implies, swapping the bytes (not bits) of a 32-bit register from one end of the register to the other, as shown in Figure 13.2. (<B>BSWAP</B> can only work with 32-bit registers; memory locations and 16-bit registers are not valid operands.) The obvious use of <B>BSWAP</B> is to convert data from Intel format (least significant byte first in memory, also called <I>little endian</I>) to Motorola format (most significant byte first in memory, or <I>big endian</I>), like so:</P>
|
||||
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|
||||
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|
||||
|
|
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|
|||
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|
||||
<P><B>BSWAP</B> can also be useful for reversing the order of pixel bits from a bitmap so that they can be rotated 32 bits at a time with an instruction such as <B>ROR EAX,1</B>. Intel’s byte ordering for multiword values (least-significant byte first) loads pixels in the wrong order, so far as word rotation is concerned, but <B>BSWAP</B> can take care of that.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/13-02.jpg',409,245 )"> --><IMG SRC="images/13-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/13-02.jpg',409,245)"> --><FONT COLOR="#000077"><B>Figure 13.2</B></FONT></A> <I>BSWAP in operation.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/13-02.jpg',409,245)"> --><B>Figure 13.2</B></A> <I>BSWAP in operation.</I>
|
||||
</P>
|
||||
<P>As it turns out, though, <B>BSWAP</B> is also useful in an unexpected way, having to do with making efficient use of the upper half of 32-bit registers. As any assembly language programmer knows, the x86 register set is too small; or, to phrase that another way, it sure would be nice if the register set were bigger. As any 386/486 assembly language programmer knows, there are many cases in which 16 bits is plenty. For example, a 16-bit scan-line counter generally does the trick nicely in a video driver, because there are <I>very</I> few video devices with more than 65,535 addressable scan lines. Combining these two observations yields the obvious conclusion that it would be great if there were some way to use the upper and lower 16 bits of selected 386 registers as separate 16-bit registers, effectively increasing the available register space.</P>
|
||||
<P>Unfortunately, the x86 instruction set doesn’t provide any way to work directly with only the upper half of a 32-bit register. The next best solution is to rotate the register to give you access in the lower 16 bits to the half you need at any particular time, with code along the lines of that in Listing 13.5. Having to rotate the 16-bit fields into position certainly isn’t as good as having direct access to the upper half, but surely it’s better than having to get the values out of memory, isn’t it?</P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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|
|||
jnz looptop
|
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|
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|
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<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Pushing and Popping Memory</FONT></H3>
|
||||
<H3><A NAME="Heading5"></A>Pushing and Popping Memory</H3>
|
||||
<P>Pushing or popping a memory location, as in <B>PUSH WORD PTR [BX]</B> or <B>POP [MemVar]</B>, is a compact, easy way to get a value onto or off of the stack, especially when pushing parameters for calling a C-compatible function. However, on a 486, these are unattractive instructions from a performance perspective. Pushing a memory location takes four cycles; by contrast, loading a memory location into a register takes only one cycle, and pushing a register takes just 1 more cycle, for a total of two cycles. Therefore,</P>
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||||
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|
|||
<P>Why is it that such a convenient operation as pushing or popping memory is so slow? The rule on the 486 is that simple operations, which can be executed in a single cycle by the 486’s RISC core, are fast; whereas complex operations, which must be carried out in microcode just as they were on the 386, are almost all relatively slow. Slow, complex operations include all the string instructions except <B>REP MOVS,</B> as well as <B>XLAT, LOOP,</B> and, of course, <B>PUSH <I>mem</I></B> and <B>POP <I>mem.</I></B></P>
|
||||
<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Whenever possible, try to use the 486’s 1-cycle instructions, including <B>MOV, ADD, SUB, CMP, ADC, SBB, XOR, AND, OR, TEST, LEA</B>, and <B>PUSH reg</B> and <B>POP reg</B>. These instructions have an added benefit in that it’s often possible to rearrange them for maximum pipeline efficiency, as is the case with Terje’s optimization described earlier in this chapter.</I></SMALL>
|
||||
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||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Optimal 1-Bit Shifts and Rotates</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Optimal 1-Bit Shifts and Rotates</H3>
|
||||
<P>On a 486, the n-bit forms of the shift and rotate instructions—as in <B>ROR AX,2</B> and <B>SHL BX,9</B>—are 2-cycle instructions, but the 1-bit forms—as in <B>ROR AX,1</B> and <B>SHL BX,1—</B>are <I>3-cycle</I> instructions. Go figure.</P>
|
||||
<P>Assemblers default to the 1-bit instruction for 1-bit shifts and rotates. That’s not unreasonable since the 1-bit form is a byte shorter and is just as fast as the n-bit forms on a 386 and faster on a 286, and the n-bit form doesn’t even exist on an 8088. In a really critical loop, however, it might be worth hand-assembling the n-bit form of a single-bit shift or rotate in order to save that cycle. The easiest way to do this is to assemble a 2-bit form of the desired instruction, as in <B>SHL AX,2,</B> then look at the hex codes that the assembler generates and use <B>DB</B> to insert them in your program code, with the value two replaced with the value one. For example, you could determine that <B>SHL AX,2</B> assembles to the bytes 0C1H 0E0H 002H, either by looking at the disassembly in a debugger or by having the assembler generate a listing file. You could then insert the n-bit version of <B>SHL AX,1</B> in your code as follows:</P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<P><BR></P>
|
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<H3><A NAME="Heading7"></A><FONT COLOR="#000077">32-Bit Addressing Modes</FONT></H3>
|
||||
<H3><A NAME="Heading7"></A>32-Bit Addressing Modes</H3>
|
||||
<P>The 386 and 486 both support 32-bit addressing modes, in which any register may serve as the base memory addressing register, and almost any register may serve as the potentially scaled index register. For example,
|
||||
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<P><BR></P>
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 14<BR>Boyer-Moore String Searching
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Optimizing a Pretty Optimum Search Algorithm</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 14<BR>Boyer-Moore String Searching</H2>
|
||||
<H3><A NAME="Heading2"></A>Optimizing a Pretty Optimum Search Algorithm</H3>
|
||||
<P>When you seem to be stumped, stop for a minute and <I>think.</I> All the information you need may be right in front of your nose if you just look at things a little differently. Here’s a case in point:</P>
|
||||
<P>When I was in college, I used to stay around campus for the summer. Oh, I’d take a course or two, but mostly it was an excuse to hang out and have fun. In that spirit, my girlfriend, Adrian (<I>not</I> my future wife, partly for reasons that will soon become apparent), bussed in to spend a week, sharing a less-than-elegant $150 per month apartment with me and, by necessity, my roommate.</P>
|
||||
<P>Our apartment was pretty much standard issue for two male college students; maybe even a cut above. The dishes were usually washed, there was generally food in the refrigerator, and nothing larger than a small dog had taken up permanent residence in the bathroom. However, there was one sticking point (literally): the kitchen floor. This floor—standard tile, with a nice pattern of black lines on an off-white background (or so we thought)—had never been cleaned. By which I mean that I know for a certainty that <I>we</I> had never cleaned it, but I suspect that it had in fact not been cleaned since the Late Jurassic, or possibly earlier. Our feet tended to stick to it; had the apartment suddenly turned upside-down, I think we’d all have been hanging from the ceiling.</P>
|
||||
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@ -47,7 +46,7 @@
|
|||
<P>She stamped her foot (really; the only time I’ve ever seen it happen), and said, “No, you jerks! The kitchen floor! Look at the floor! I cleaned it!”</P>
|
||||
<P>The floor really did look amazing. It was actually all white; the black lines had been grooves filled with dirt. We assured her that it looked terrific, it just wasn’t that obvious until you knew to look for it; anyone would tell you that it wasn’t the kind of thing that jumped out at you, but it really was great, no kidding. We had almost smoothed things over, when a friend walked in, looked around with a start, and said, “Hey! Did you guys put in a new floor?”</P>
|
||||
<P>As I said, sometimes everything you need to know is right in front of your nose. Which brings us to Boyer-Moore string searching.</P>
|
||||
<H3><A NAME="Heading3"></A><FONT COLOR="#000077">String Searching Refresher</FONT></H3>
|
||||
<H3><A NAME="Heading3"></A>String Searching Refresher</H3>
|
||||
<P>I’ve discussed string searching earlier in this book, in Chapters 5 and 9. You may want to refer back to these chapters for some background on string searching in general. I’m also going to use some of the code from that chapter as part of this chapter’s test suite. For further information, you may want to refer to the discussion of string searching in the excellent <I>Algorithms in C,</I> by Robert Sedgewick (Addison-Wesley), which served as the primary reference for this chapter. (If you look at Sedgewick, be aware that in the Boyer-Moore listing on page 288, there is a mistake: “j > 0” in the <B>for</B> loop should be “j >= 0,” unless I’m missing something.)</P>
|
||||
<P>String searching is the simple matter of finding the first occurrence of a particular sequence of bytes (the pattern) within another sequence of bytes (the buffer). The obvious, brute-force approach is to try every possible match location, starting at the beginning of the buffer and advancing one position after each mismatch, until either a match is found or the buffer is exhausted. There’s even a nifty string instruction, <B>REPZ CMPS,</B> that’s perfect for comparing the pattern to the contents of the buffer at each location. What could be simpler?</P>
|
||||
<P>We have some important information that we’re not yet using, though. Typically, the buffer will contain a wide variety of bytes. Let’s assume that the buffer contains text, in which case there will be dozens of different characters; and although the distribution of characters won’t usually be even, neither will any one character constitute half the buffer, or anything close. A reasonable conclusion is that the first character of the pattern will rarely match the first character of the buffer location currently being checked. This allows us to use the speedy <B>REPNZ SCASB</B> to whiz through the buffer, eliminating most potential match locations with single repetitions of <B>SCASB.</B> Only when that first character does (infrequently) match must we drop back to the slower <B>REPZ CMPS</B> approach.</P>
|
||||
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|||
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<hr width="90%" size="1" noshade>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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14
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||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">The Boyer-Moore Algorithm</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>The Boyer-Moore Algorithm</H3>
|
||||
<P>All our <I>a priori</I> knowledge of string searching is stated above, but there’s another sort of knowledge—knowledge that’s generated dynamically. As we search through the buffer, we acquire information each time we check for a match. One sort of information that we acquire is based on partial matches; we can often skip ahead after partial matches because (take a deep breath!) by partially matching, we have already implicitly done a comparison of the partially matched buffer characters with all possible pattern start locations that overlap those partially-matched bytes.</P>
|
||||
<P>If that makes your head hurt, it should—and don’t worry. This line of thinking, which is the basis of the Knuth-Morris-Pratt algorithm and half the basis of the Boyer-Moore algorithm, is what gives Boyer-Moore its reputation for inscrutability. That reputation is well deserved for this aspect (which I will not discuss further in this book), but there’s another part of Boyer-Moore that’s easily understood, easily implemented, and highly effective.</P>
|
||||
<P>Consider this: We’re searching for the pattern “ABC,” beginning the search at the start (offset 0) of a buffer containing “ABZABC.” We match on ‘A,’ we match on ‘B,’ and we mismatch on ‘C’; the buffer contains a ‘Z’ in this position. What have we learned? Why, we’ve learned not only that the pattern doesn’t match the buffer starting at offset 0, but also that it can’t possibly match starting at offset 1 or offset 2, either! After all, there’s a ‘Z’ in the buffer at offset 2; since the pattern doesn’t contain a single ‘Z,’ there’s no way that the pattern can match starting at <I>any</I> location from which it would span the ‘Z’ at offset 2. We can just skip straight from offset 0 to offset 3 and continue, saving ourselves two comparisons.</P>
|
||||
|
|
@ -46,18 +46,18 @@
|
|||
<P>We learn nothing new from a mismatch on the leftmost character, except that the pattern can’t match starting at that location. A mismatch on the rightmost character, however, tells us about the possibilities of the pattern matching starting at every buffer location from which the pattern spans the mismatch location. If the mismatched character in the buffer doesn’t appear in the pattern, then we’ve just eliminated not one potential match, but as many potential matches as there are characters in the pattern; that’s how many locations there are in the buffer that <I>might</I> have matched, but have just been shown not to, because they overlap the mismatched character that doesn’t belong in the pattern. In this case, we can skip ahead by the full pattern length in the buffer! This is how we can outperform even <B>REPNZ SCASB; REPNZ SCASB</B> has to check every byte in the buffer, but Boyer-Moore doesn’t.</P>
|
||||
<P>Figure 14.1 illustrates the operation of a Boyer-Moore search when the rightcharacter of the search pattern (which is the first character that’s compared at each location because we’re comparing backwards) mismatches with a buffer character that appears nowhere in the pattern. Figure 14.2 illustrates the operation of a partial match when the mismatch occurs with a character that’s not a pattern member. In this case, we can only skip ahead past the mismatch location, resulting in an advance of fewer bytes than the pattern length, and potentially as little as the same single byte distance by which the standard search approach advances.</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/14-01.jpg',413,306 )"> --><IMG SRC="images/14-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/14-01.jpg',413,306)"> --><FONT COLOR="#000077"><B>Figure 14.1</B></FONT></A> <I>Mismatch on first character checked.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/14-01.jpg',413,306)"> --><B>Figure 14.1</B></A> <I>Mismatch on first character checked.</I>
|
||||
</P>
|
||||
<P>What if the mismatch occurs with a buffer character that <I>does</I> occur in the pattern? Then we can’t skip past the mismatch location, but we can skip to whatever location aligns the rightmost occurrence of that character in the pattern with the mismatch location, as shown in Figure 14.3.</P>
|
||||
<P>Basically, we exercise our right as members of a free society to compare strings in whichever direction we choose, and we choose to do so right to left, rather than the more intuitive left to right. Whenever we find a mismatch, we see what we can learn from the buffer character that failed to match the pattern. Imagine that we move the pattern to the right across the mismatch location until we find a start location that the mismatch does not eliminate as a possible match for the pattern. If the mismatch character doesn’t appear in the pattern, the pattern can move clear past the mismatch location. Otherwise, the pattern moves until a matching pattern byte lies atop the mismatch. That’s all there is to it!</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/14-02.jpg',406,306 )"> --><IMG SRC="images/14-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/14-02.jpg',406,306)"> --><FONT COLOR="#000077"><B>Figure 14.2</B></FONT></A> <I>Mismatch on third character checked.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/14-02.jpg',406,306)"> --><B>Figure 14.2</B></A> <I>Mismatch on third character checked.</I>
|
||||
</P>
|
||||
<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Boyer-Moore: The Good and the Bad</FONT></H3>
|
||||
<H3><A NAME="Heading5"></A>Boyer-Moore: The Good and the Bad</H3>
|
||||
<P>The worst case for this version of Boyer-Moore is that the pattern mismatches on the leftmost character—the last character compared—every time. Again, not very likely, but it is true that this version of Boyer-Moore performs better as there are fewer and shorter partial matches; ideally, the rightmost character would never match until the full match location was reached. Longer patterns, which make for longer skips, help Boyer-Moore, as does a long distance to the match location, which helps diffuse the overhead of building the table of distances to skip ahead on all the possible mismatch values.
|
||||
</P>
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/14-03.jpg',407,304 )"> --><IMG SRC="images/14-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/14-03.jpg',407,304)"> --><FONT COLOR="#000077"><B>Figure 14.3</B></FONT></A> <I>Mismatch on character that appears in pattern.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/14-03.jpg',407,304)"> --><B>Figure 14.3</B></A> <I>Mismatch on character that appears in pattern.</I>
|
||||
</P>
|
||||
<P>The best case for Boyer-Moore is good indeed: About N/M comparisons are required, where N is the buffer length and M is the pattern length. This reflects the ability of Boyer-Moore to skip ahead by a full pattern length on a complete mismatch.
|
||||
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|
||||
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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@ -214,7 +214,7 @@ _FindString endp
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<P><BR></P>
|
||||
<P>Table 14.1 represents a limited and decidedly unscientific comparison of searching techniques. Nonetheless, the overall trend is clear: For all but the shortest patterns, well-implemented Boyer-Moore is generally as good as or better than—sometimes <I>much</I> better than—brute-force searching. (For short patterns, you might want to use <B>REPNZ SCASB,</B> thereby getting the best of both worlds.)</P>
|
||||
<P>Know your data and use your smarts. Don’t stop thinking just because you’re implementing a big-name algorithm; you know more than it does.</P>
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Further Optimization of Boyer-Moore</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Further Optimization of Boyer-Moore</H3>
|
||||
<P>We can do substantially better yet than Listing 14.3 if we’re willing to accept tighter limits on the data. Limiting the length of the searched-for pattern to a maximum of 255 bytes allows us to use the <B>XLAT</B> instruction and generally tighten the critical loop. (Be aware, however, that <B>XLAT</B> is a relatively expensive instruction on the 486 and Pentium.) Putting a copy of the searched-for string at the end of the search buffer as a sentinel, so that the search never fails, frees us from counting down the buffer length, and makes it easy to unroll the critical loop. Listing 14.4, which implements these optimizations, is about 60 percent faster than Listing 14.3.</P>
|
||||
<P><B>LISTING 14.4 L14-4.ASM</B></P>
|
||||
<!-- CODE //-->
|
||||
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@ -192,7 +192,7 @@ _FindString endp
|
|||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<P>Note that Table 14.1 includes the time required to build the skip table each time <B>FindString</B> is called. This time could be eliminated for all but the first search when repeatedly searching for a particular pattern, by building the skip table externally and passing a pointer to it as a parameter.</P>
|
||||
<H3><A NAME="Heading7"></A><FONT COLOR="#000077">Know What You Know</FONT></H3>
|
||||
<H3><A NAME="Heading7"></A>Know What You Know</H3>
|
||||
<P>Here we’ve turned up our nose at a repeated string instruction, we’ve gone against the grain by comparing backward, and yet we’ve speeded up our code quite a bit. All this without any restrictions or special requirements (excluding Listing 14.4)—and without any new information. Everything we needed was sitting there all along; we just needed to think to look at it.
|
||||
</P>
|
||||
<P>As Yogi Berra might put it, “You don’t know what you know until you know it.”</P><P><BR></P>
|
||||
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@ -208,7 +208,7 @@ _FindString endp
|
|||
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||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
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||||
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13
15-01.html
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||||
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|
|||
</TABLE>
|
||||
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|
||||
<P><BR></P>
|
||||
<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 15<BR>Linked Lists and plain Unintended Challenges
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Unfamiliar Problems with Familiar Data Structures</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 15<BR>Linked Lists and plain Unintended Challenges</H2>
|
||||
<H3><A NAME="Heading2"></A>Unfamiliar Problems with Familiar Data Structures</H3>
|
||||
<P>After 21 years, this story still makes me wince. Oh, the humiliations I suffer for your enlightenment....
|
||||
</P>
|
||||
<P>It wasn’t until ninth grade that I had my first real girlfriend. Okay, maybe I was a little socially challenged as a kid, but hey, show me a good programmer who wasn’t; it goes with the territory. Her name was Jeannie Schweigert, and she was about four feet tall, pretty enough, and female—and willing to go out with me, which made her approximately as attractive as Cheryl Tiegs, in my book.</P>
|
||||
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|
@ -48,7 +47,7 @@
|
|||
<P>I was a pretty mature teenager, so this was only slightly more traumatic than leading the Tournament of Roses parade in my underwear. On the next try, though, I did manage to get the hang of this kissing business, and eventually even went on to have a child. (Not with Jeannie, I might add; the mind boggles at the mess I could have made of <I>that</I> with her.) As it turns out, none of that stuff is particularly difficult; in fact, it’s kind of enjoyable, wink, wink, say no more.</P>
|
||||
<P>When you’re dealing with something new, a little knowledge goes a long way. When it comes to kissing, we have to fumble along the learning curve on our own, but there are all sorts of resources to help speed up the learning process when it comes to programming. The basic mechanisms of programming—searches, sorts, parsing, and the like—are well-understood and superbly well-documented. Treat yourself to a book like <I>Algorithms,</I> by Robert Sedgewick (Addison Wesley), or Knuth’s <I>The Art of Computer Programming</I> series (also from Addison Wesley; and where was Knuth with <I>The Art of Kissing</I> when I needed him?), or practically anything by Jon Bentley, and when you tackle a new area, give yourself a head start. There’s still plenty of room for inventiveness and creativity on your part, but why not apply that energy on top of the knowledge that’s already been gained, instead of reinventing the wheel? I know, reinventing the wheel is just the kind of challenge programmers love—but can you really afford to waste the time? And do you honestly think that you’re so smart that you can out-think Knuth, who’s spent a lifetime at this stuff and happens to be a genius?</P>
|
||||
<P>Maybe you can—but I sure can’t. For example, consider the evolution of my understanding of linked lists.</P>
|
||||
<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Linked Lists</FONT></H3>
|
||||
<H3><A NAME="Heading3"></A>Linked Lists</H3>
|
||||
<P>Linked lists are data structures composed of discrete elements, or nodes, joined together with links. In C, the links are typically pointers. Like all data structures, linked lists have their strengths and their weaknesses. Primary among the strengths are: simplicity; speedy sequential processing; ease and speed of insertion and deletion; the ability to mix nodes of various sizes and types; and the ability to handle variable amounts of data, especially when the total amount of data changes dynamically or is not always known beforehand. Weaknesses include: greater memory requirements than arrays (the pointers take up space); slow non-sequential processing, including finding arbitrary nodes; and an inability to backtrack, unless doubly-linked lists are used. Unfortunately, doubly linked lists need more memory, as well as processing time to maintain the backward links.
|
||||
</P>
|
||||
<P>Linked lists aren’t very good for most types of sorts. Insertion and bubble sorts work fine, but more sophisticated sorts depend on efficient random access, which linked lists don’t provide. Likewise, you wouldn’t want to do a binary search on a linked list. On the other hand, linked lists are ideal for applications where nothing more than sequential access is needed to data that’s always sorted or nearly sorted.</P>
|
||||
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|
@ -58,7 +57,7 @@
|
|||
<P>The basic concept of a linked list—the one I came up with for that <I>DDJ</I> column—is straightforward, as shown in Figure 15.1. A head pointer points to the first node in the list, which points to the next node, which points to the next, and so on, until the last node in the list is reached (typically denoted by a <B>NULL</B> next-node pointer). Conceptually, nothing could be simpler. From an implementation perspective, however, there are serious flaws with this model.</P>
|
||||
<P>The fundamental problem is that the model of Figure 15.1 unnecessarily complicates link manipulation. In order to delete a node, for example, you must change the preceding node’s <B>NextNode</B> pointer to point to the following node, as shown in Listing 15.1. (Listing 15.2 is the header file LLIST.H, which is <B>#include</B>d by all the linked list listings in this chapter.) Easy enough—unless the preceding node happens to be the head pointer, which doesn’t <I>have</I> a <B>NextNode</B> field, because it’s not a node, so Listing 15.1 won’t work. Cumbersome special code and extra information (a pointer to the head of the list) are required to handle the head-pointer case, as shown in Listing 15.3. (I’ll grant you that if you make the next-node pointer the first field in the <B>LinkNode</B> structure, at offset 0, then you could successfully point to the head pointer and pretend it was a <B>LinkNode</B> structure—but that’s an ugly and potentially dangerous trick, and we’ll see a better approach next.)</P>
|
||||
<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/15-01.jpg',405,97 )"> --><IMG SRC="images/15-01.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-01.jpg',405,97)"> --><FONT COLOR="#000077"><B>Figure 15.1</B></FONT></A> <I>The basic concept of a linked list.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-01.jpg',405,97)"> --><B>Figure 15.1</B></A> <I>The basic concept of a linked list.</I>
|
||||
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
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||||
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@ -100,10 +100,10 @@ struct LinkNode *DeleteNodeAfter(struct LinkNode **HeadOfListPtr,
|
|||
<P>However, it is true that if you’re going to store a variety of types of structures in your linked lists, you should start each node with the <B>LinkNode</B> field. That way, the link pointer is in the same place in <I>every</I> structure, and the same linked list code can handle all of the structure types by casting them to the base link-node structure type. This is a less than elegant approach, but it works. C<SMALL>++</SMALL> can handle data mixing more cleanly than C, via derivation from a base link-node class.</P>
|
||||
<P>Note that Listings 15.1 and 15.3 have to specify the linked-list delete operation as “delete the <I>next</I> node,” rather than “delete this node,” because in order to relink it’s necessary to access the <B>NextNode</B> field of the node preceding the node to be deleted, and it’s impossible to backtrack in a singly linked list. For this reason, singly-linked list operations tend to work with the structure preceding the one of interest—and that makes the problem of having to special-case the head pointer all the more acute.</P>
|
||||
<P>Similar problems with the head pointer crop up when you’re inserting nodes, and in fact in all link manipulation code. It’s easy to end up working with either pointers to pointers or lots of special-case code, and while those approaches work, they’re inelegant and inefficient.</P>
|
||||
<H3><A NAME="Heading4"></A><FONT COLOR="#000077">Dummies and Sentinels</FONT></H3>
|
||||
<H3><A NAME="Heading4"></A>Dummies and Sentinels</H3>
|
||||
<P>A far better approach is to use a <I>dummy node</I> for the head of the list, as shown in Figure 15.2. I invented this one for myself the next time I encountered linked lists, while designing a seed fill function for MetaWindows, back during my tenure at Metagraphics Corp. But I could have learned it by spending five minutes with Sedgewick’s book.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/15-02.jpg',407,102 )"> --><IMG SRC="images/15-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-02.jpg',407,102)"> --><FONT COLOR="#000077"><B>Figure 15.2</B></FONT></A> <I>Using a dummy head and tail node with a linked list.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-02.jpg',407,102)"> --><B>Figure 15.2</B></A> <I>Using a dummy head and tail node with a linked list.</I>
|
||||
</P>
|
||||
<TABLE WIDTH="100%">
|
||||
<TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>The next-node pointer of the head node, which points to the first real node, is the only part of the head node that’s actually used. This way the same code works on the head node as on the rest of the list, so there are no special cases.</I></SMALL>
|
||||
|
|
@ -139,7 +139,7 @@ struct LinkNode *FindNodeBeforeValueNotLess(
|
|||
<!-- END CODE //-->
|
||||
<P>Suppose, however, that we make the tail node a <I>sentinel</I> by giving it a value that is guaranteed to terminate the search, as shown in Figure 15.4. The list in Figure 15.4 has a sentinel with a value field of 32,767; since we’re working with integers, that’s the highest possible search value, and is guaranteed to satisfy any search that comes down the pike. The success or failure of the search can then be determined outside the loop, if necessary, by checking for the tail node’s special pointer—but the inside of the loop is streamlined to just one test, as shown in Listing 15.5. Not all linked lists lend themselves to sentinels, but the performance benefits are considerable for those lend themselves to sentinels, but the performance benefits are considerable for those that do.</P>
|
||||
<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/15-03.jpg',407,104 )"> --><IMG SRC="images/15-03.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-03.jpg',407,104)"> --><FONT COLOR="#000077"><B>Figure 15.3</B></FONT></A> <I>Representing an empty list.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-03.jpg',407,104)"> --><B>Figure 15.3</B></A> <I>Representing an empty list.</I>
|
||||
<P><BR></P>
|
||||
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|
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@ -153,7 +153,7 @@ struct LinkNode *FindNodeBeforeValueNotLess(
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
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||||
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||||
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@ -64,16 +64,16 @@ struct LinkNode *FindNodeBeforeValueNotLess(
|
|||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<P><A NAME="Fig4"><!-- </A><A HREF="javascript:displayWindow('images/15-04.jpg',405,105 )"> --><IMG SRC="images/15-04.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-04.jpg',405,105)"> --><FONT COLOR="#000077"><B>Figure 15.4</B></FONT></A> <I>List terminated by a sentinel.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-04.jpg',405,105)"> --><B>Figure 15.4</B></A> <I>List terminated by a sentinel.</I>
|
||||
</P>
|
||||
<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Circular Lists</FONT></H3>
|
||||
<H3><A NAME="Heading5"></A>Circular Lists</H3>
|
||||
<P>One minor but elegant refinement yet remains: Use a single node as both the head <I>and</I> the tail of the list. We can do this by connecting the last node back to the first through the head/tail node in a circular fashion, as shown in Figure 15.5. This head/tail node can also, of course, be a sentinel; when it’s necessary to check for the end of the list explicitly, that can be done by comparing the current node pointer to the head pointer. If they’re equal, you’re at the head/tail node.</P>
|
||||
<P>Why am I so fond of this circular list architecture? For one thing, it saves a node, and most of my linked list programming has been done in severely memory-constrained environments. Mostly, though, it’s just so <I>neat;</I> with this setup, there’s not a single node or inner-loop instruction wasted. Perfect economy of programming, if you ask me.</P>
|
||||
<P>I must admit that I racked my brains for quite a while to come up with the circular list, simple as it may seem. Shortly after coming up with it, I happened to look in Sedgewick’s book, only to find my nifty optimization described plain as day; and a little while after <I>that,</I> I came across a thread in the algorithms/computer.sci topic on BIX that described it in considerable detail. Folks, the information is out there. Look it up <I>before</I> turning on your optimizer afterburners!</P>
|
||||
<P>Listings 15.1 and 15.6 together form a suite of C functions for maintaining a circular linked list sorted by ascending value. (Listing 15.5 requires modification before it will work with circular lists.) Listing 15.7 is an assembly language version of <B>InsertNodeSorted()</B>; note the tremendous efficiency of the scanning loop in <B>InsertNodeSorted()—</B>four instructions per node!—thanks to the dummy head/tail/sentinel node. Listing 15.8 is a simple application that illustrates the use of the linked-list functions in Listings 15.1 and 15.6.</P>
|
||||
<P>Contrast Figure 15.5 with Figure 15.1, and Listings 15.1, 15.5, 15.6, and 15.7 with Listings 15.3 and 15.4. Yes, linked lists are simple, but not so simple that a little knowledge doesn’t make a substantial difference. Make it a habit to read Knuth or Sedgewick or the like before you write a single line of code.</P>
|
||||
<P><A NAME="Fig5"><!-- </A><A HREF="javascript:displayWindow('images/15-05.jpg',410,112 )"> --><IMG SRC="images/15-05.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-05.jpg',410,112)"> --><FONT COLOR="#000077"><B>Figure 15.5</B></FONT></A> <I>Representing a circular list.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/15-05.jpg',410,112)"> --><B>Figure 15.5</B></A> <I>Representing a circular list.</I>
|
||||
</P>
|
||||
<P><B>LISTING 15.6 L15-6.C</B></P>
|
||||
<!-- CODE //-->
|
||||
|
|
@ -158,7 +158,7 @@ struct LinkNode *InsertNodeSorted(struct LinkNode *HeadOfListNode,
|
|||
|
||||
<hr width="90%" size="1" noshade>
|
||||
<div align="center">
|
||||
<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
|
||||
Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
|
||||
<!-- all of the reference materials (books) have the footer and subfoot reveresed -->
|
||||
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||||
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@ -186,7 +186,7 @@ void main()
|
|||
}
|
||||
</PRE>
|
||||
<!-- END CODE //-->
|
||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">Hi/Lo in 24 Bytes</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>Hi/Lo in 24 Bytes</H3>
|
||||
<P>In one of my <I>PC TECHNIQUES</I> “Pushing the Envelope” columns, I passed along one of David Stafford’s fiendish programming puzzles: Write a C-callable function to find the greatest or smallest unsigned <B>int</B>. Not a big deal—except that David had <I>already</I> done it in 24 bytes, so the challenge was to do it in 24 bytes or less.</P>
|
||||
<P>Such routines soon began coming at me from all angles. However (and I hate to say this because some of my correspondents were <I>very</I> pleased with the thought that they had bested David), no one has yet met the challenge—because most of you folks missed a key point. When David said, “Write a function to find the greatest or smallest unsigned <B>int</B> in 24 bytes or less,” he meant, “Write the <B>hi</B> and the <B>lo</B> functions in 24 bytes or less—<I>combined</I>.”</P>
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<P>Oh.</P>
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 16<BR>There Ain’t No Such Thing as the Fastest Code
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<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Lessons Learned in the Pursuit of the Ultimate Word Counter</FONT></H3>
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<H2><A NAME="Heading1"></A>Chapter 16<BR>There Ain’t No Such Thing as the Fastest Code</H2>
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<H3><A NAME="Heading2"></A>Lessons Learned in the Pursuit of the Ultimate Word Counter</H3>
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<P>I remember reading an overview of C<SMALL>++</SMALL> development tools for Windows in a past issue of <I>PC Week</I>. In the lower left corner was the familiar box listing the 10 leading concerns of corporate buyers when it comes to C<SMALL>++</SMALL>. Boiled down, the list looked like this, in order of descending importance to buyers:</P>
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<P>Is something missing here? You bet your maximum <I>gluteus</I> something’s missing—nowhere on that list is there so much as one word about how fast the compiled code runs! I’m not saying that performance is everything, but optimization isn’t even down there at number 10, below online help! Ye gods and little fishes! We are talking here about people who would take a bus from LA to New York instead of a plane because it had a cleaner bathroom; who would choose a painting from a Holiday Inn over a Matisse because it had a fancier frame; who would buy a Yugo instead of—well, hell, anything—because it had a nice owner’s manual and particularly attractive keys. We are talking about people who are focusing on means, and have forgotten about ends. We are talking about people with no programming souls.</P>
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<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Counting Words in a Hurry</FONT></H3>
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<H3><A NAME="Heading3"></A>Counting Words in a Hurry</H3>
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<P>What are we to make of this? At the very least, we can safely guess that very few corporate buyers ever enter optimization contests. Most of my readers do, however; in fact, far more than I thought ever would, but that gladdens me to no end. I issued my first optimization challenge in a “Pushing the Envelope” column in <I>PC TECHNIQUES</I> back in 1991, and was deluged by respondents who, one might also gather, do not live by <I>PC Week</I>.</P>
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<P>That initial challenge was sparked by a column David Gerrold wrote (also in <I>PC TECHNIQUES</I> ) concerning the matter of counting the number of words in a document; David turned up some pretty interesting optimization issues along the way. David did all his coding in Pascal, pointing out that while an assembly language version would probably be faster, his Pascal utility worked properly and was fast enough for him.</P>
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<P>It wasn’t, however, fast enough for me. The logical starting place for speeding up word counting would be David’s original Pascal code, but I’m much more comfortable with C, so Listing 16.1 is a loose approximation of David’s word count program, translated to C. I left out a few details, such as handling comment blocks, partly because I don’t use such blocks myself, and partly so we can focus on optimizing the core word-counting code. As Table 16.1 indicates, Listing 16.1 counts the words in a 104,448-word file in 4.6 seconds. The file was stored on a RAM disk, and Listing 16.1 was compiled with Borland C<SMALL>++</SMALL> with all optimization enabled. A RAM disk was used partly because it returns consistent times—no seek times, rotational latency, or cache to muddy the waters—and partly to highlight word-counting speed rather than disk access speed.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading4"></A><FONT COLOR="#000077">Which Way to Go from Here?</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading4"></A>Which Way to Go from Here?</H4>
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<P>We could rearrange the tests in light of the nature of the data being scanned; for example, we could perform the tests more efficiently by taking advantage of the knowledge that if a byte is less than ‘0,’ it’s either an apostrophe or not a character at all. However, that sort of fine-tuning is typically good for speedups of only 10 to 20 percent, and I’ve intentionally refrained from implementing this in Listing 16.3 to avoid pointing you down the wrong path; what we need is a different tack altogether. Ponder this. What we <I>really</I> want to know is nothing more than whether a byte is a character, not what sort of character it is. For each byte value, we want a yes/no status, and nothing else—and that description practically begs for a lookup table. Listing 16.4 uses a lookup table approach to boost performance another 50 percent, to three times the performance of the original C code. On a 20 MHz 386, this represents a change from 4.6 to 1.6 seconds, which could be significant—who likes to wait? On an 8088, the improvement in word-counting a large file could easily be 10 or 20 seconds, which is <I>definitely</I> significant.</P><P><BR></P>
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<P>So, gosh, Listing 16.4 is the best word-counting code in the universe, right? Not hardly. If there’s one thing my years of toil in this vale of silicon have taught me, it’s that there’s never a lack of potential for further optimization. <I>Never!</I> Off the top of my head, I can think of at least three ways to speed up Listing 16.4; and, since Turbo Profiler reports that even in Listing 16.4, 88 percent of the time is spent scanning the buffer (as opposed to reading the file), there’s potential for those further optimizations to improve performance significantly. (However, it is true that when access is performed to a hard rather than RAM disk, disk access jumps to about half of overall execution time.) One possible optimization is unrolling the loop, although that is truly a last resort because it tends to make further changes extremely difficult.</P>
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<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Exhaust all other optimizations before unrolling loops.</I></SMALL>
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<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Challenges and Hazards</FONT></H3>
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<H3><A NAME="Heading5"></A>Challenges and Hazards</H3>
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<P>The challenge I put to the readers of <I>PC TECHNIQUES</I> was to write a faster module to replace Listing 16.4. The author of the code that counted the words in my secret test file fastest on my 20 MHz cached 386 would be the winner and receive Numerous Valuable Prizes.</P>
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||||
<P>No listings were to be longer than 200 lines. No complete programs were to be accepted; submissions had to be plug-compatible with Listing 16.4. (This was to encourage people not to waste time optimizing outside the inner loop.) Finally, the code had to produce the same results as Listing 16.4; I didn’t want to see functions that approximated the word count by dividing the number of characters by six instead of counting actual words!</P>
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||||
<P>So how did the entrants in this particular challenge stack up? More than one claimed a speed-up over my assembly word-counting code of more than three times. On top of the three-times speedup over the original C code that I had already realized, we’re almost up to an order of magnitude faster. You are, of course, entitled to your own opinion, but <I>I</I> consider an order of magnitude to be significant.</P><P><BR></P>
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<P>Truth to tell, I didn’t expect a three-times speedup; around two times was what I had in mind. Which just goes to show that any code can be made faster than you’d expect, if you think about it long enough and from many different perspectives. (The most potent word-counting technique seems to be a 64K lookup table that allows handling two bytes simultaneously. This is not the sort of technique one comes up with by brute-force optimization.) Thinking (or, worse yet, boasting) that your code is the fastest possible is rollescating on a tightrope in a hurricane; you’re due for a fall, if you catch my drift. Case in point: Terje Mathisen’s word-counting program.
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<H4 ALIGN="LEFT"><A NAME="Heading6"></A><FONT COLOR="#000077">Blinding Yourself to a Better Approach</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading6"></A>Blinding Yourself to a Better Approach</H4>
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||||
<P>Not so long ago, Terje Mathisen, who I introduced earlier in this book, wrote a very fast word-counting program, and posted it on Bix. When I say it was fast, I mean <I>fast;</I> this code was optimized like nobody’s business. We’re talking top-quality code here.</P>
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||||
<P>When the topic of optimizing came up in one of the Bix conferences, Terje’s program was mentioned, and he posted the following message: “I challenge BIXens (and especially <B>mabrash!</B>) to speed it up significantly. I would consider 5 percent a good result.” The clear implication was, “That code is as fast as it can possibly be.”</P>
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||||
<P>Naturally, it wasn’t; there ain’t no such thing as the fastest code (TANSTATFC? I agree, it doesn’t have the ring of TANSTAAFL). I pored over Terje’s 386 native-mode code, and found the critical inner loop, which was indeed as tight as one could imagine, consisting of just a few 386 native-mode instructions. However, one of the instructions was this:</P>
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<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I><B>CMP reg,[mem]</B> takes 6 cycles on the 386, but <B>CMP [ mem ],reg</B> takes only 5 cycles; you should always perform<B>CMP</B> with the memory operand on the left on the 386.</I></SMALL>
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<P>(Granted, <B>CMP [<I>mem</I>],<I>reg</I></B> is 1 cycle slower than <B>CMP <I>reg</I>,[<I>mem</I>]</B> on the 286, and they’re both the same on the 8088; in this case, though, the code was specific to the 386. In case you’re curious, both forms take 2 cycles on the 486; quite a lot faster, eh?)</P>
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<H4 ALIGN="LEFT"><A NAME="Heading7"></A><FONT COLOR="#000077">Watch Out for Luggable Assumptions!</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading7"></A>Watch Out for Luggable Assumptions!</H4>
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||||
<P>The first lesson to be learned here is not to lug assumptions that may no longer be valid from the 8088/286 world into the wonderful new world of 386 native-mode programming. The second lesson is that after you’ve slaved over your code for a while, you’re in no shape to see its flaws, or to be able to get the new perspectives needed to speed it up. I’ll bet Terje looked at that <B>[EBX+EAX]</B> addressing a hundred times while trying to speed up his code, but he didn’t really see what it did; instead, he saw what it was supposed to do. Mental shortcuts like this are what enable us to deal with the complexities of assembly language without overloading after about 20 instructions, but they can be a major problem when looking over familiar code.</P>
|
||||
<P>The third, and most interesting, lesson is that a far more fruitful optimization came of all this, one that nicely illustrates that cycle counting is not the key to happiness, riches, and wondrous performance. After getting my 5 percent speedup, I mentioned to Terje the possibility of using a 64K lookup table. (This predated the arrival of entries for the optimization contest.) He said that he had considered it, but it didn’t seem to him to be worthwhile. He couldn’t shake the thought, though, and started to poke around, and one day, <I>voila,</I> he posted a new version of his word count program, WC50, that was <I>much</I> faster than the old version. I don’t have exact numbers, but Terje’s preliminary estimate was 80 percent faster, and word counting—<I>including</I> disk cache access time—proceeds at more than 3 MB per second on a 33 MHz 486. Even allowing for the speed of the 486, those are very impressive numbers indeed.</P>
|
||||
<P>The point I want to make, though, is that the biggest optimization barrier that Terje faced was that he <I>thought</I> he had the fastest code possible. Once he opened up the possibility that there were faster approaches, and looked beyond the specific approach that he had so carefully optimized, he was able to come up with code that was a <I>lot</I> faster. Consider the incongruity of Terje’s willingness to consider a 5 percent speedup significant in light of his later near-doubling of performance.</P>
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<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Don’t get stuck in the rut of instruction-by-instruction optimization. It’s useful in key loops, but very often, a change in approach will work far greater wonders than any amount of cycle counting can.</I></SMALL>
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<P>By the way, Terje’s WC50 program is a full-fledged counting program; it counts characters, words, and lines, can handle multiple files, and lets you specify the characters that separate words, should you so desire. Source code is provided as part of the archive WC50 comes in. All in all, it’s a nice piece of work, and you might want to take a look at it if you’re interested in really fast assembly code. I wouldn’t call it the <I>fastest</I> word-counting code, though, because I would of course never be so foolish as to call <I>anything</I> the fastest.</P>
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<H3><A NAME="Heading8"></A><FONT COLOR="#000077">The Astonishment of Right-Brain Optimization</FONT></H3>
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||||
<H3><A NAME="Heading8"></A>The Astonishment of Right-Brain Optimization</H3>
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||||
<P>As it happened, the challenge I issued to my <I>PC TECHNIQUES</I> readers was a smashing success, with dozens of good entries. I certainly enjoyed it, even though I did have to look at a <I>lot</I> of tricky assembly code that I didn’t write—hard work under the best of circumstances. It was worth the trouble, though. The winning entry was an astonishing example of what assembly language can do in the right hands; on my 386, it was <I>four times</I> faster at word counting than the nice, tight assembly code I provided as a starting point—and about 13 times faster than the original C implementation. Attention, high-level language chauvinists: Is the speedup getting significant yet? Okay, maybe word counting isn’t the most critical application, but how would you like to have that kind of improvement in your compression software, or in your real-time games—or in Windows graphics?</P>
|
||||
<P>The winner was David Stafford, who at the time was working for Borland International; his entry is shown in Listing 16.5. Dave Methvin, whom some of you may recall as a tech editor of the late, lamented <I>PC Tech Journal,</I> was a close second, and Mick Brown, about whom I know nothing more than that he is obviously an extremely good assembly language programmer, was a close third, as shown in Table 16.2, which precedes Listing 16.5. Those three were out ahead of the pack; the fourth-place entry, good as it was (twice as fast as my original code), was twice as slow as David’s winning entry, so you can see that David, Dave, and Mick attained a rarefied level of optimization indeed.</P><P><BR></P>
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<H3><A NAME="Heading9"></A><FONT COLOR="#000077">Levels of Optimization</FONT></H3>
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<H3><A NAME="Heading9"></A>Levels of Optimization</H3>
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<P>Three levels of optimization were evident in the word-counting entries I received in response to my challenge. I’d briefly describe them as “fine-tuning,” “new perspective,” and “table-driven state machine.” The latter categories produce faster code, but, by the same token, they are harder to design, harder to implement, and more difficult to understand, so they’re suitable for only the most demanding applications. (Heck, I don’t even guarantee that David Stafford’s entry works perfectly, although, knowing him, it probably does; the more complex and cryptic the code, the greater the chance for obscure bugs.)
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<TABLE WIDTH="100%"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="5%"><IMG SRC="images/i.jpg"><TD ALIGN="LEFT" VALIGN="TOP" WIDTH="95%"><SMALL><I>Remember, optimize only when needed, and stop when further optimization will not be noticed. Optimization that’s not perceptible to the user is like buying Telly Savalas a comb; it’s not going to do any harm, but it’s nonetheless a waste of time.</I></SMALL>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">Optimization Level 1: Good Code</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A>Optimization Level 1: Good Code</H4>
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<P>The first level of optimization involves fine-tuning and clever use of the instruction set. The basic framework is still the same as my code (which in turn is basically the same as that of the original C code), but that framework is implemented more efficiently.
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<P>One obvious level 1 optimization is using a <B>word</B> rather than <B>dword</B> counter. <B>ScanBuffer</B> can never be called upon to handle more than 64K bytes at a time, so no more than 32K words can ever be found. Given that, it’s a logical step to use <B>INC</B> rather than <B>ADD/ADC</B> to keep count, adding the tally into the full 32-bit count only upon exiting the function. Another useful optimization is aligning loop tops and other branch destinations to <B>word</B> , or better yet <B>dword</B> , boundaries.</P>
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<H3><A NAME="Heading11"></A><FONT COLOR="#000077">Level 2: A New Perspective</FONT></H3>
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<H3><A NAME="Heading11"></A>Level 2: A New Perspective</H3>
|
||||
<P>The second level of optimization is one of breaking out of the mode of thinking established by my original code. Some entrants clearly did exactly that. They stepped back, thought about what the code actually needed to do, rather than just improving how it already worked, and implemented code that sprang from that new perspective.
|
||||
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|
||||
<P>You can see one example of this in Listing 16.6, where Willem uses <B>CMP AX,0101H</B> to check two bytes at once. While you might think of this as nothing more than a doubling up of tests, it’s a little more than that, especially when taken together with the use of two loops. This is a break with the serial nature of the C code, a recognition that word counting is really nothing more than a state machine that transitions from the “in word” state to the “not in word” state and back, counting a word on one but not both of those transitions. Willem says, in effect, “We’re in a word; if the next two bytes are non-separators, then we’re still in a word, else we’re not in a word, so count and change to the appropriate state.” That’s really quite different from saying, as I originally did, “If the last byte was a non-separator, then if the current byte is a separator, then count a word.” Willem has moved away from the all-in-one approach, splitting the code up into state-specific chunks that are more efficient because each does only the work required in a particular state.</P>
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<P>John later divides the transition count by two to get the word count. (Food for thought: It’s also possible to use <B>CMP</B> and <B>ADC</B> to detect words without branching.)</P>
|
||||
<P>John’s approach makes it clear that word-counting is nothing more than a fairly simple state machine. The interesting part, of course, is building the fastest state machine.</P>
|
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<H4 ALIGN="LEFT"><A NAME="Heading12"></A><FONT COLOR="#000077">Level 3: Breakthrough</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading12"></A>Level 3: Breakthrough</H4>
|
||||
<P>The boundaries between the levels of optimization are not sharply defined. In a sense, level 3 optimization is just like levels 1 and 2, but more so. At level 3, one takes whatever level 2 perspective seems most promising, and implements it as efficiently as possible on the x86. Even more than at level 2, at level 3 this means breaking out of familiar patterns of thinking.
|
||||
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|
||||
<P>In the case of word counting, level 3 means building a table-driven state machine dedicated to processing a buffer of bytes into a count of words with a minimum of branching. This level of optimization strips away many of the abstractions we usually use in coding, such as loops, tests, and named variables—look back to Listing 16.5, and you’ll see what I mean. Only a few people reached this level, and I don’t think any of them did it without long, hard thinking; David Stafford’s final entry (that is, the one I present as Listing 16.5) was <I>at least</I> the fifth entry he sent me.</P>
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<P>The trick, then, is to identify the separator/not statuses of each set of three bytes and turn them into a 1 (count word) or 0 (don’t count word), as quickly as possible. Assuming that the separator/not status for the first byte is in the Carry flag, this is easily accomplished by a lookup in a 64K table, based on the Carry flag and the other two bytes, as shown in Figure 16.2. (Remember that we’re counting 7-bit ASCII here, so the high bit is ignored.) Thus, David is able to add the word/not status for each pair of bytes to the main word count simply by getting the two bytes, working in the carry status from the last byte, and using the resulting value to index into the 64K table, adding in the 1 or 0 value found in that table. A sequence of <B>MOV/ADC/ADD</B> suffices to perform all word-counting tasks for a pair of bytes. Three instructions, no branches—pretty nearly perfect code.</P>
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<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/16-01.jpg',410,122 )"> --><IMG SRC="images/16-01.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/16-01.jpg',410,122)"> --><FONT COLOR="#000077"><B>Figure 16.1</B></FONT></A> <I>The two potential word count locations.</I>
|
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<BR><A HREF="javascript:displayWindow('images/16-01.jpg',410,122)"> --><B>Figure 16.1</B></A> <I>The two potential word count locations.</I>
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||||
<P>One detail remains to be attended to: setting the Carry flag for next time if the last byte was a non-separator. David does this in a bizarre and incredibly effective way: He presets the high bit of the count, and sets the high bit in the lookup table for those entries looked up by non-separators. When a non-separator’s lookup entry is added to the count, it will produce a carry, as desired. The high bit of the count is masked off before being added to the total count, so David is essentially using different parts of the count variables for different purposes (counting, and setting the Carry flag).
|
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|
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<BR><A HREF="javascript:displayWindow('images/16-02.jpg',408,232)"> --><FONT COLOR="#000077"><B>Figure 16.2</B></FONT></A> <I>Looking up a word count status.</I>
|
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<BR><A HREF="javascript:displayWindow('images/16-02.jpg',408,232)"> --><B>Figure 16.2</B></A> <I>Looking up a word count status.</I>
|
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|
||||
<P>There are a number of other interesting details in David’s code, including the unrolling of the loop 64 times, so that 256 bytes in a row are processed without a single branch. Unfortunately, I lack the space to discuss Listing 16.5 any further. Perhaps that’s not so unfortunate, after all; I’d hate to deny you the pleasure of discovering the wonders of this rather remarkable code yourself. I will say one more thing, though. The cycle count for David’s inner loop is 6.5 cycles per byte processed, and the actual measured time for his routine, overhead and all, is 7.9 cycles/byte. The original C code clocked in at around 100 cycles/byte.
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|
||||
<P>Enough said, I trust.</P>
|
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<H4 ALIGN="LEFT"><A NAME="Heading13"></A><FONT COLOR="#000077">Enough Word Counting Already!</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading13"></A>Enough Word Counting Already!</H4>
|
||||
<P>Before I finish up this chapter, I’d like to mention that Terje Mathisen’s WC word-counting program, which I’ve mentioned previously and which is available, with source, on Bix, is in the ballpark with David’s code for performance. What’s more, Terje’s program handles 8-bit ASCII, counts lines as well as words, and supports user-definable separator sets. It’s wonderful code, well worth a look; it also happens to be a great word-counting utility. By the way, Terje builds his 64K table on the fly, at program initialization; this allows for customized tables, shrinks the size of the EXE, and, according to Terje’s calculations, takes less time than loading the table off disk as part of the EXE.
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</P>
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||||
<P>So, has David written the fastest possible word-counting code? Well, maybe—but I have a letter from Terry Holmes, of San Rafael, California, that calculates the theoretical maximum performance of native 386 word-counting code at 5.5 cycles/byte, which would be significantly faster than David’s code. Terry, alas, didn’t bother to implement his design, but maybe I’ll take a shot at it someday. It’d be fun, for sure—but jeez, I’ve got <I>real</I> work to do!</P><P><BR></P>
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 17<BR>The Game of Life
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</FONT></H2>
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<H3><A NAME="Heading2"></A><FONT COLOR="#000077">The Triumph of Algorithmic Optimization in a Cellular Automata Game</FONT></H3>
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<H2><A NAME="Heading1"></A>Chapter 17<BR>The Game of Life</H2>
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<H3><A NAME="Heading2"></A>The Triumph of Algorithmic Optimization in a Cellular Automata Game</H3>
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||||
<P>I’ve spent a lot of my life discussing assembly language optimization, which I consider to be an important and underappreciated topic. However, I’d like to take this opportunity to point out that there is much, much more to optimization than assembly language. Assembly is essential for absolute maximum performance, but it’s not the only ingredient; necessary but not sufficient, if you catch my drift—and not even necessary, if you’re looking for improved but not maximum performance. You’ve heard it a thousand times: Optimize your algorithm first. Devise new approaches. Or, as Knuth said, <I>Premature optimization is the root of all evil.</I></P>
|
||||
<P>This is, of course, old hat, stuff you know like the back of your hand. Or is it? As Jeff Duntemann pointed out to me the other day, performance programmers are made, not born. While I’m merrily gallivanting around in this book optimizing 486 pipelining and turning simple tasks into horribly complicated and terrifyingly fast state machines, many of you are still developing your basic optimization skills. I don’t want to shortchange those of you in the latter category, so in this chapter, we’ll discuss some high-level language optimizations that can be applied by mere mortals within a reasonable period of time. We’re going to examine a complete optimization process, from start to finish, and what we will find is that it’s possible to get a 50-times speed-up without using <I>one byte of assembly!</I> It’s all a matter of perspective—how you look at your code and data.</P>
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<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Conway’s Game</FONT></H3>
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<H3><A NAME="Heading3"></A>Conway’s Game</H3>
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||||
<P>The program that we’re going to optimize is Conway’s famous Game of Life, long-ago favorite of the hackers at MIT’s AI Lab. If you’ve never seen it, let me assure you: Life is <I>neat,</I> and more than a little hypnotic. Fractals have been the hot graphics topic in recent years, but for eye-catching dazzle, Life is hard to beat.</P>
|
||||
<P>Of course, eye-catching dazzle requires real-time performance—lots of pixels help too—and there’s the rub. When there are, say, 40,000 cells to process and display, a simple, straightforward implementation just doesn’t cut it, even on a 33 MHz 486. Happily, though, there are many, many ways to speed up Life, and they illustrate a variety of important optimization principles, as this chapter will show.</P>
|
||||
<P>First, I’ll describe the ground rules of Life, implement a very straightforward version in C<SMALL>++</SMALL>, and then speed that version up by about eight times without using any drastically different approaches or any assembly. This may be a little tame for some of you, but be patient; for after that, we’ll haul out the big guns and move into the 30 to 40 times speed-up range. Then in the next chapter, I’ll show you how several programmers <I>really</I> floored it in taking me up on my second Optimization Challenge, which involved the Game of Life.</P>
|
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<H4 ALIGN="LEFT"><A NAME="Heading4"></A><FONT COLOR="#000077">The Rules of the Game</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading4"></A>The Rules of the Game</H4>
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||||
<P>The Game of Life is ridiculously simple. There is a cellmap, consisting of a rectangular matrix of cells, each of which may initially be either on or off. Each cell has eight neighbors: two horizontally, two vertically, and four diagonally. For each succeeding generation of cells, the game logic determines whether each cell will be on or off according to the following rules:
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<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Where Does the Time Go?</FONT></H3>
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<H3><A NAME="Heading5"></A>Where Does the Time Go?</H3>
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||||
<P>How slow is Listing 17.1? Table 17.1 shows that even on a 486, Listing 17.1 does fewer than three 96x96 generations per second. (The times in Table 17.1 are for 1,000 generations of a 96x96 cell map with <B>seed=1, LIMIT_18_HZ=0, WRAP_EDGES=1,</B> and <B>magnifier=2,</B> running on a 33 MHz 486.) Since my target is 18 generations per second with a 200x200 cellmap on a 20 MHz 386, Listing 17.1 is too slow by a rather wide margin—75 times too slow, in fact. You might say we have a little optimizing to do.</P>
|
||||
<P>The first rule of optimization is: Only optimize where it matters. Use a profiler, or risk making a fool of yourself. Consider Listings 17.1 and 17.2. Where do you think the potential for significant speed-up lies? I’ll tell you one place where I thought there was considerable potential—in <B>draw_pixel()</B>. As a programmer of high-speed graphics, I figured any drawing function that was not only written in C/C<SMALL>++</SMALL> but also recalculated the target address from scratch for each pixel would be among the first optimization targets. I also expected to get major gains out of going to a Ping-Pong arrangement so that I didn’t have to copy the new cellmap back to <B>current_map</B> after calculating the next generation.</P>
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<P>I was wrong. Wrong, wrong, wrong. (But at least I was smart enough to use a profiler before actually writing any new code.) Table 17.1 shows where the time actually goes in Listings 17.1 and 17.2. As you can see, the time taken by <B>draw_pixel(),</B> <B>copy_cells(),</B> and <I>everything</I> other than calculating the next generation is nothing more than noise. We could optimize these routines right down to executing <I>instantaneously,</I> and you know what? It wouldn’t make the slightest perceptible difference in how fast the program runs. Given the present state of our Game of Life implementation, the only areas worth looking at for possible optimizations are <B>cell_state()</B> and <B>next_generation().</B></P>
|
||||
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><I><SMALL>It’s worth noting, though, that one reason <B>draw_pixel()</B> doesn’t much affect performance is that in Listing 17.1, we’re smart enough to redraw pixels only when their states change, rather than during every generation. Detecting and eliminating redundant operations is part of knowing the nature of your data, and is a potent optimization technique that will be extremely useful a little later in this chapter.</SMALL></I>
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||||
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||||
<H3><A NAME="Heading6"></A><FONT COLOR="#000077">The Hazards and Advantages of Abstraction</FONT></H3>
|
||||
<H3><A NAME="Heading6"></A>The Hazards and Advantages of Abstraction</H3>
|
||||
<P>How can we speed up <B>cell_state()</B> and <B>next_generation()</B>? I’ll tell you how <I>not</I> to do it: By writing those member functions in assembly. It’s tempting to say that <B>cell_state()</B> is taking all the time, so we need to speed it up with assembly, but what we really need to do is figure out <I>why</I> <B>cell_state()</B> is taking all the time, then address that aspect of the program directly.</P>
|
||||
<P>Once you know where you need to optimize, the one word to keep in mind isn’t assembly, it’s...plastics. No, actually, it’s <I>abstraction.</I> Well-written C and especially C<SMALL>++</SMALL> programs are highly abstract models. For example, Listing 17.1 essentially creates a new programming language in which cells are tangible things, with built-in manipulation instructions. Given the cellmap member functions, you don’t even need to know the cell storage format! This is a wonderful thing, in general; it saves programming time and bugs, and frees you to work on the application’s needs, rather than implementation details.</P>
|
||||
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><I><SMALL>However, if you never look beneath the surface of the abstract model at the implementation details, you have no idea of what the true performance cost of various operations</I><I> is, and, without that, you have largely surrendered control over performance.</SMALL></I>
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<P>There’s a kicker here, though, and that’s the counting of neighbors for cells at the edge of the cellmap. When cellmap wrapping is enabled (so that the cellmap becomes essentially a toroid, with each edge joined seamlessly to the opposite edge, as opposed to having a border of off-cells), neighbors that reside on the other edge of the cellmap can’t be accessed by the standard fixed offset, as shown in Figure 17.1. So, in general, we could improve performance by hard-wiring our neighbor-counting for the bit-per-cell cellmap format, but it seems we’d need a lot of conditional code to handle wrapping, and that would slow things back down again.
|
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<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/17-01.jpg',408,258 )"> --><IMG SRC="images/17-01.jpg"><BR><!-- </A>
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||||
<BR><A HREF="javascript:displayWindow('images/17-01.jpg',408,258)"> --><FONT COLOR="#000077"><B>Figure 17.1</B></FONT></A> <I>Edge-wrapping complications.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/17-01.jpg',408,258)"> --><B>Figure 17.1</B></A> <I>Edge-wrapping complications.</I>
|
||||
</P>
|
||||
<P>When a problem doesn’t lend itself well to optimization, make it a practice to see if you can change the problem definition to one that allows for greater efficiency. In this case, we’ll change the problem by putting padding bytes around the edge of the cellmap, and duplicating each edge of the cellmap in the padding bytes at the opposite side, as shown in Figure 17.2. That way, a hard-wired neighbor count will find exactly what it should—the opposite edge—without any special code at all.
|
||||
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|
||||
<P>But doesn’t that extra copying of the edges take time? Sure, but only a little; we can build it into the cellmap copying function, and then frankly we won’t even notice it. Avoiding tens or hundreds of thousands of calls to <B>cell_state(),</B> on the other hand, will be <I>very</I> noticeable. Listing 17.3 shows the alterations to Listing 17.1 required to implement a hard-wired neighbor-counting function. This is a minor change, in truth, implemented in about half an hour and not making the code significantly larger—but Listing 17.3 is 3.6 times faster than Listing 17.1, as shown in Table 17.1. We’re up to about 10 generations per second on a 486; not where we want to be, but it is a vast improvement.</P>
|
||||
<P><A NAME="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/17-02.jpg',407,260 )"> --><IMG SRC="images/17-02.jpg"><BR><!-- </A>
|
||||
<BR><A HREF="javascript:displayWindow('images/17-02.jpg',407,260)"> --><FONT COLOR="#000077"><B>Figure 17.2</B></FONT></A> <I>The “padding cells” solution.</I>
|
||||
<BR><A HREF="javascript:displayWindow('images/17-02.jpg',407,260)"> --><B>Figure 17.2</B></A> <I>The “padding cells” solution.</I>
|
||||
</P>
|
||||
<P><B>LISTING 17.3 L17-3.CPP</B></P>
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<P>In Listing 17.3, note the padded cellmap edges, and the alteration of the member functions to compensate for the padding. Also note that the width now has to be a multiple of eight, to facilitate the process of copying the edges to the opposite padding bytes. We have decreased the generality of our Game of Life implementation in exchange for better performance. That’s a very common trade-off, as common as trading memory for performance. As a rule, the more general a program is, the slower it is. A corollary is that often (not always, but often), the more heavily optimized a program is, the more complex and the more difficult to implement it is. You can often improve performance a good deal by implementing only the level of generality you need, but at the same time decreased generality makes it more difficult to change or port the program at some later date. A Game of Life implementation, such as Listing 17.1, that’s built on <B>set_cell()</B>, <B>clear_cell()</B>, and <B>get_cell()</B> is completely general; you can change the cell storage format simply by changing the constructor and those three functions. Listing 17.3 is harder to change because <B>count_neighbors()</B> would also have to be altered, and it’s more complex than any of the other functions.</P>
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<P>So, in Listing 17.3, we’ve gotten under the hood and changed the cellmap format a little, and gotten impressive results. But now <B>count_neighbors()</B> is hard-wired for optimized counting, and it’s still taking up more than half the time. Maybe now it’s time to go to assembly?</P>
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<P>Not hardly.</P>
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<H3><A NAME="Heading7"></A><FONT COLOR="#000077">Heavy-Duty C++ Optimization</FONT></H3>
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<H3><A NAME="Heading7"></A>Heavy-Duty C++ Optimization</H3>
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<P>Before we get to assembly, we still have to perform C<SMALL>++</SMALL> optimization, then see if we can find an alternative approach that better fits the application. It would actually have made much more sense if we had looked for a new approach as our first optimization step, but I decided it would be better to cover straightforward C<SMALL>++</SMALL> optimizations at this point, and the mind-bending stuff a little later. Right now, let’s look at some C<SMALL>++</SMALL> optimizations; Listing 17.4 is a C<SMALL>++</SMALL>-optimized version of Listing 17.3.</P>
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<P><B>LISTING 17.4 L17-4.CPP</B></P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<li>There are many possible cellmap representations other than one bit-per-pixel.</li>
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<li>Cells change state relatively infrequently.</li>
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</ul>
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<H3><A NAME="Heading8"></A><FONT COLOR="#000077">Bringing In the Right Brain</FONT></H3>
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<H3><A NAME="Heading8"></A>Bringing In the Right Brain</H3>
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<P>In the previous section, we saw how a C<SMALL>++</SMALL> program could be sped up about eight times simply by rearranging the data and code in straightforward ways. Now we’re going to see how right-brain non-linear optimization can speed things up by another four times—and make the code <I>simpler.</I></P>
|
||||
<P>Now <I>that’s</I> Zen code optimization.</P>
|
||||
<P>I have two objectives to achieve in the remainder of this chapter. First, I want to show that optimization consists of many levels, from assembly language up to conceptual design, and that assembly language kicks in pretty late in the optimization process. Second, I want to encourage you to saturate your brain with everything you know about any particular optimization problem, then make space for your right brain to solve the problem.</P>
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<H4 ALIGN="LEFT"><A NAME="Heading9"></A><FONT COLOR="#000077">Re-Examining the Task</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading9"></A>Re-Examining the Task</H4>
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<P>Earlier in this chapter, we looked at a straightforward Game of Life implementation, then increased performance considerably by making the implementation a little less abstract and a little less general. We made a small change to the cellmap format, adding padding bytes off the edges so that pointer arithmetic would always work, but the major optimizations were moving the critical code into a single loop and using pointers rather than member functions whenever possible. In other words, we took what we already knew and made it more efficient.
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</P>
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||||
<P>Now it’s time to re-examine the nature of this programming task from the ground up, looking for things that we <I>don’t</I> yet know. Let’s take a moment to review what the Game of Life consists of. The basic task is evolving a new generation, and that’s done by looking at the number of “on” neighbors a cell has and the cell’s own state. If a cell is on, and two or three neighbors are on, then the cell stays on; otherwise, an on-cell is turned off. If a cell is off and exactly three neighbors are on, then the cell is turned on; otherwise, an off-cell stays off. That’s all there is to it. As any fool can see, the trick is to arrange things so that we can count neighbors and check the cell state as quickly as possible. Large lookup tables, oddly encoded cellmaps, and lots of bit-twiddling assembly code spring to mind as possible approaches. Can’t you just feel your adrenaline start to pump?</P>
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|||
<P>But what about the overhead needed to maintain the neighbor counts? Well, each time a cell changes state, eight operations would be needed to update the counts in the eight neighboring cells. But this happens only once every ten cells, on average—so the cost of this approach is only one-tenth that of the original approach!</P>
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||||
<P><I>Know your data.</I></P>
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<P><A NAME="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/17-03.jpg',405,113 )"> --><IMG SRC="images/17-03.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/17-03.jpg',405,113)"> --><FONT COLOR="#000077"><B>Figure 17.3</B></FONT></A> <I>New cell format.</I>
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<BR><A HREF="javascript:displayWindow('images/17-03.jpg',405,113)"> --><B>Figure 17.3</B></A> <I>New cell format.</I>
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</P>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A><FONT COLOR="#000077">Acting on What We Know</FONT></H4>
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<H4 ALIGN="LEFT"><A NAME="Heading10"></A>Acting on What We Know</H4>
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||||
<P>Once we’ve changed the cellmap format to store neighbor counts as well as states, with a byte for each cell, we can get another performance boost by again examining what we know about our data. I said earlier that most cells are off during any given generation. This means that most cells have no neighbors that are on. Since the cell map representation for an off-cell that has no neighbors is a zero byte, we can skip over scads of unchanged cells at a pop simply by scanning for non-zero bytes. This is much faster than explicitly testing cell states and neighbor counts, and lends itself beautifully to assembly language implementation as <B>REPZ SCASB</B> or (with a little cleverness) <B>REPZ SCASW.</B> (Unfortunately, there’s no C library function that can scan memory for the next byte that’s non-zero.)</P>
|
||||
<P>Listing 17.5 is a Game of Life implementation that uses the neighbor-count cell map format and scans for non-zero bytes. On a 20 MHz 386, Listing 17.5 is about 4.5 times faster at calculating generations (that is, the generation engine is 4.5 times faster; I’m ignoring the time consumed by drawing and text display) than Listing 17.4, which is no slouch. On a 33 MHz 486, Listing 17.5 is about 3.5 times faster than Listing 17.4. This is true even though Listing 17.5 must be compiled using the large model. Imagine that—getting a four times speed-up while switching from the small model to the large model!</P><P><BR></P>
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<hr width="90%" size="1" noshade>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
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<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><I><SMALL>We’ve gotten more than a 30-times speedup simply by removing a little of the abstraction that C<SMALL>++</SMALL> encourages, and by storing and processing the data in a manner appropriate for the typical nature of the data itself. In other words, we’ve done some linear, left-brained optimization (using pointers and reducing calls) and some non-linear, right-brained optimization (understanding the real problem and listening for the creative whisper of non-obvious solutions).</SMALL></I>
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</TABLE>
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<P>No doubt we could get another two to five times improvement with good assembly code—but that’s dwarfed by a 30-times improvement, so optimization at a conceptual level <I>must</I> come first.</P>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading11"></A><FONT COLOR="#000077">The Challenge That Ate My Life</FONT></H4>
|
||||
<H4 ALIGN="LEFT"><A NAME="Heading11"></A>The Challenge That Ate My Life</H4>
|
||||
<P>The most recent optimization challenge I laid my community of readers was to write the fastest possible Game of Life generation engine. By “engine” I meant that I didn’t care about time spent in input or output, only time consumed by the call to <B>next-generation.</B> The time spent updating the cellmap was what I wanted people to concentrate on.</P>
|
||||
<P>Here are the rules I laid down for the challenge:</P>
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||||
<ul>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
||||
</div>
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11
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<P><BR></P>
|
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<H2><A NAME="Heading1"></A><FONT COLOR="#000077">Chapter 18<BR>It’s a plain Wonderful Life
|
||||
</FONT></H2>
|
||||
<H3><A NAME="Heading2"></A><FONT COLOR="#000077">Optimization beyond the Pale</FONT></H3>
|
||||
<H2><A NAME="Heading1"></A>Chapter 18<BR>It’s a plain Wonderful Life</H2>
|
||||
<H3><A NAME="Heading2"></A>Optimization beyond the Pale</H3>
|
||||
<P>When I was in high school, my gym teacher had us run a race around the soccer field, or rather, around a course marked with cones that roughly outlined the shape of the field. I quickly settled into second place behind Dwight Chamberlin. We cruised around the field, and when we came to the far corner, Dwight cut across the corner, inside a cone placed awkwardly far out from the others. I followed, and everyone else cut inside the cone too—except the pear-shaped kid bringing up the rear, who plodded his way around every single cone on his way to finishing about half a lap behind. When the laggard finally crossed the finish line, the coach named him the winner, to my considerable irritation. After all, the object was to see who could run the fastest, wasn’t it?
|
||||
</P>
|
||||
<P>Actually, it wasn’t. The object was to see who could run the fastest according to the limitations placed upon the contest. This is a crucial distinction, although usually taken for granted. Would it have been legitimate if I had cut across the middle of the field? If I had ridden a bike? If I had broken the world record for the 100 meters by dropping 100 meters from a plane? Competition has meaning only within a carefully circumscribed arena.</P>
|
||||
<P>Why am I telling you this? First, because it is a useful lesson for programming.</P>
|
||||
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>All programming is performed within limitations, some of which can be bent or changed, but many of which cannot. You cannot change the maximum memory bandwidth of a VGA, or the maximum instruction execution rate of a 486. That is why the stunning 3D demos you see at SIGGRAPH have only passing relevance to everyday life on the desktop. A rule that Intel’s chip designers cannot break is 8086 compatibility, much as I’m sure they’d like to, but of course the flip side is that although RISC chips are technically superior, they command but a small fraction of the market; raw performance is not the arena of competition. Similarly, you will often be unable to change the specifications for the software you implement.</I></SMALL>
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</TABLE>
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<H3><A NAME="Heading3"></A><FONT COLOR="#000077">Breaking the Rules</FONT></H3>
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||||
<H3><A NAME="Heading3"></A>Breaking the Rules</H3>
|
||||
<P>The other reason for the anecdote has to do with the way my second Optimization Challenge worked itself out. If you’ll recall from the last chapter, the challenge I made to the readers of <I>PC TECHNIQUES</I> was to devise the fastest possible version of the Game of Life cellular automata simulation game. I gave an example, laid out the rules, and stood aside. Good thing, too. <I>Apres moi, le deluge....</I></P>
|
||||
<P>And when the dust had settled, I was left with the uneasy realization that every submitted entry broke the rules. <I>Every single entry</I>. The rules clearly stated that submitted code must produce <I>exactly the same output</I> as my example implementation under all circumstances in order to be eligible to win. I do not think that there can be any question about what “exactly the same output” means. It means the same pixels, in the same colors, at the same places on the screen at the same points in all the Life simulations that the original code was capable of running. Period. And not one of the entries met that standard. Some submitted listings were more than 400 lines long. Some didn’t display the generation number at the right side of the screen, didn’t draw the same pixel colors, or didn’t bother with magnification. Some had bugs. Some didn’t support all possible cellmap widths and heights up to 200x200, requiring widths and heights that were specific multiples of a number of cells that lent itself to a particular implementation.</P>
|
||||
<P>This last mission is, in a way, a brilliant approach, as evidenced by the fact that it yielded the two fastest submissions, but it is not within the rules of the contest. Some of the rule-breaking was major, some very minor, and some had nothing to do with the Life engine itself, but the rules were clear; where was I to draw the line if not with exact compliance? And I was fully prepared to draw that line rigorously, disqualifying some mind-bending submissions in order to let lesser but fully compliant entries win—until I realized that there <I>were</I> no fully compliant entries.</P>
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<font face="Verdana,sans-serif" size="1">Graphics Programming Black Book © 2001 Michael Abrash</font>
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Graphics Programming Black Book © 2001 Michael Abrash
|
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