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Retidy, removing align=left from headings and empty paragraphs

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James Gregory 2013-12-30 15:37:13 +11:00
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@ -1,5 +1,4 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
@ -19,17 +18,21 @@
<center>
<table border="1">
<tr>
<td><a href="63-01.html">Previous</a></td>
<td>
<a href="63-01.html">Previous</a>
</td>
<td><a href="index.html">Table of Contents</a></td>
<td>
<a href="index.html">Table of Contents</a>
</td>
<td><a href="63-03.html">Next</a></td>
<td>
<a href="63-03.html">Next</a>
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<p><br /></p>
<p>FDIV is a painfully slow instruction, taking 39 cycles at full precision and 33 cycles at double precision, which is the default precision for Visual C<small>++</small> 2.0. While FDIV executes, the FPU is occupied, and can&rsquo;t process subsequent FP instructions until FDIV finishes. However, during the cycles while FDIV is executing (with the exception of the one cycle during which FDIV starts), the integer unit can simultaneously execute instructions other than IMUL. (IMUL uses the FPU, and can only overlap with FDIV for a few cycles.) Since the integer unit can execute two instructions per cycle, this means it&rsquo;s possible to have three instructions, an FDIV and two integer instructions, executing at the same time. That&rsquo;s exactly what happens, for example, during the second cycle of this code:</p>
<pre>
FDIV ST(0),ST(1)
@ -47,7 +50,7 @@ FST [temp]
<p>takes 6 cycles in all.) Again, it&rsquo;s possible to execute integer-unit instructions during the 2 (or 3, for FST) cycles after one of these FP instructions starts. There&rsquo;s a more exciting possibility here, though: Given properly structured code, the FPU is capable of averaging 1 cycle per FADD, FSUB, or FMUL. The secret is pipelining.</p>
<h4 align="left" id="Heading5">Pipelining, Latency, and Throughput</h4>
<h4 id="Heading5">Pipelining, Latency, and Throughput</h4>
<p>The Pentium&rsquo;s FPU is the first pipelined x86 FPU. <i>Pipelining</i> means that the FPU is capable of starting an instruction every cycle, and can simultaneously handle several instructions in various stages of completion. Only certain x86 FP instructions allow another instruction to start on the next cycle, though: FADD, FSUB, and FMUL are pipelined, but FST and FDIV are not. (FLD executes in a single cycle, so pipelining is not an issue.) Thus, in the code sequence</p>
<pre>
@ -85,7 +88,7 @@ FSUB ST(0),ST(1)
<p>where the ST(0) operand to FSUB is calculated by FADD. Here, FSUB can&rsquo;t start until FADD has completed, so there are 2 stall cycles between the two instructions. When dependencies like this occur, the FPU runs at latency rather than throughput speeds, and performance can drop by as much as two-thirds.</p>
<h4 align="left" id="Heading6">FXCH</h4>
<h4 id="Heading6">FXCH</h4>
<p>One piece of the puzzle is still missing. Clearly, to get maximum throughput, we need to interleave FP instructions, such that at any one time ideally three instructions are in the pipeline at once. Further, these instructions must not depend on one another for operands. But ST(0) must always be one of the operands; worse, FLD can only push into ST(0), and FST can only store from ST(0). How, then, can we keep three independent instructions going?</p>
@ -110,16 +113,20 @@ FSUB ST(0),ST(1)
<p>Listing 63.2 shows a straightforward dot product implementation. This version loses 7 cycles to stalls. Listing 63.3 cuts the loss to 5 cycles by doing all three FMULs first, then using FXCH to set the third FXCH aside to complete while the results of the first two FMULs, which have completed, are added. Listing 43.3 still loses 50 percent to stalls, but unless some other code is available to be interleaved with the dot product code, that&rsquo;s all we can do to speed things up. Fortunately, dot products are often used in contexts where there&rsquo;s plenty of interleaving potential, as we&rsquo;ll see when we discuss transformation.</p>
<p><br /></p>
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<table border="1">
<tr>
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<td>
<a href="63-01.html">Previous</a>
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<td><a href="index.html">Table of Contents</a></td>
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<a href="index.html">Table of Contents</a>
</td>
<td><a href="63-03.html">Next</a></td>
<td>
<a href="63-03.html">Next</a>
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</table>
</center>