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Retidy, removing align=left from headings and empty paragraphs

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James Gregory 2013-12-30 15:37:13 +11:00
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml">
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<center>
<table border="1">
<tr>
<td><a href="04-05.html">Previous</a></td>
<td>
<a href="04-05.html">Previous</a>
</td>
<td><a href="index.html">Table of Contents</a></td>
<td>
<a href="index.html">Table of Contents</a>
</td>
<td><a href="04-07.html">Next</a></td>
<td>
<a href="04-07.html">Next</a>
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<p><br /></p>
<p>More than anything, the above rules mean using the registers as heavily as possible, both because register-only instructions are short and because they don&rsquo;t perform memory accesses to read or write operands. However, using the registers is a rule of thumb, not a commandment. In some circumstances, it may actually be <i>faster</i> to access memory. (The look-up table technique is one such case.) What&rsquo;s more, the performance of the prefetch queue (and hence the performance of each instruction) differs from one code sequence to the next, and can even differ during different executions of the <i>same</i> code sequence.</p>
<p>All in all, writing good assembler code is as much an art as a science. As a result, you should follow the rules of thumb described here&mdash;and then time your code to see how fast it really is. You should experiment freely, but always remember that actual, measured performance is the bottom line.</p>
<h4 align="left" id="Heading14">Holding Up the 8088</h4>
<h4 id="Heading14">Holding Up the 8088</h4>
<p>In this chapter I&rsquo;ve taken you further and further into the depths of the PC, telling you again and again that you must understand the computer at the lowest possible level in order to write good code. At this point, you may well wonder, &ldquo;Have we gotten low enough?&rdquo;</p>
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<p>All of the PC&rsquo;s system memory consists of DRAM chips. Each DRAM chip in the PC must be completely refreshed about once every four milliseconds in order to ensure the integrity of the data it stores. Obviously, it&rsquo;s highly desirable that the memory in the PC retain the correct data indefinitely, so each DRAM chip in the PC <i>must</i> always be refreshed within 4 &micro;s of the last refresh. Since there&rsquo;s no guarantee that a given program will access each and every DRAM block once every 4 &micro;s, the PC contains special circuitry and programming for providing DRAM refresh.</p>
<h4 align="left" id="Heading16">How DRAM Refresh Works in the PC</h4>
<h4 id="Heading16">How DRAM Refresh Works in the PC</h4>
<p>On the original 8088-based IBM PC, timer 1 of the 8253 timer chip is programmed at power-up to generate a signal once every 72 cycles, or once every 15.08&micro;s. That signal goes to channel 0 of the 8237 DMA controller, which requests the bus from the 8088 upon receiving the signal. (DMA stands for <i>direct memory access,</i> the ability of a device other than the 8088 to control the bus and access memory directly, without any help from the 8088.) As soon as the 8088 is between memory accesses, it gives control of the bus to the 8237, which in conjunction with special circuitry on the PC&rsquo;s motherboard then performs a single 4-cycle read access to 1 of 256 possible addresses, advancing to the next address on each successive access. (The read access is only for the purpose of refreshing the DRAM; the data that is read isn&rsquo;t used.)</p>
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<p><a id="Fig5"><img src="images/04-05.jpg" /><br />
<b>Figure 4.5</b></a>&nbsp;&nbsp;<i>The PC bus dynamic RAM (DRAM) refresh.</i></p>
<p><br /></p>
<center>
<table border="1">
<tr>
<td><a href="04-05.html">Previous</a></td>
<td>
<a href="04-05.html">Previous</a>
</td>
<td><a href="index.html">Table of Contents</a></td>
<td>
<a href="index.html">Table of Contents</a>
</td>
<td><a href="04-07.html">Next</a></td>
<td>
<a href="04-07.html">Next</a>
</td>
</tr>
</table>
</center>