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James Gregory 2013-12-30 12:25:34 +11:00
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<H3><A NAME="Heading5"></A><FONT COLOR="#000077">Lockstep Execution</FONT></H3>
<P>You may wonder why anyone would bother breaking <B>ADD [MemVar],EAX</B> into three instructions, given that this instruction can go through either pipe with equal ease. The answer is that while the memory-accessing instructions other than <B>MOV, PUSH</B>, and <B>POP</B> listed in Table 20.1 (that is, <B>INC/DEC [<I>mem</I>], ADD/SUB/XOR/AND/OR/CMP/ADC/SBB <I>reg</I>,[<I>mem</I>]</B>, and <B>ADD/SUB/XOR/AND/OR/CMP/ADC/SBB [<I>mem</I>],<I>reg/immed</I></B>) can be paired, they do not provide the 100 percent overlap that we seek. If you look at Tables 20.1 and 20.2, you will see that instructions taking from 1 to 3 cycles can pair. However, any pair of instructions goes through the two pipes in lockstep. This means, for example, that if <B>ADD [EBX],EDX</B> is going through the U-pipe, and <B>INC EAX</B> is going through the V-pipe, the V-pipe will be idle for 2 of the 3 cycles that the U-pipe takes to execute its instruction, as shown in Figure 20.4. Out of the theoretical 6 cycles of work that can be done during this time, we actually get only 4 cycles of work, or 67 percent utilization. Even though these instructions pair, then, this sequence fails to make maximum use of the Pentium&#146;s horsepower.</P>
<P>The key here is that when two instructions pair, both execution units are tied up until both instructions have finished (which means at least for the amount of time required for the longer of the two to execute, plus possibly some extra cycles for pairable instructions that can&#146;t fully overlap, as described below). The logical conclusion would seem to be that we should strive to pair instructions of the same lengths, but that is often not correct.</P>
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/20-04i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>The actual rule is that we should strive to pair one-cycle instructions (or, at most, two-cycle instructions, but not three-cycle instructions), which in turn leads to the corollary that we should, in general, use mostly one-cycle instructions when optimizing.</I></SMALL>
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>The actual rule is that we should strive to pair one-cycle instructions (or, at most, two-cycle instructions, but not three-cycle instructions), which in turn leads to the corollary that we should, in general, use mostly one-cycle instructions when optimizing.</I></SMALL>
</TABLE>
<P><A NAME="Fig4"><!-- </A><A HREF="javascript:displayWindow('images/20-04.jpg',411,224 )"> --><IMG SRC="images/20-04.jpg"><BR><!-- </A>
<BR><A HREF="javascript:displayWindow('images/20-04.jpg',411,224)"> --><FONT COLOR="#000077"><B>Figure 20.4</B></FONT></A>&nbsp;&nbsp;<I>Lockstep execution and idle time in the V-pipe.</I>