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James Gregory 2013-12-30 12:25:34 +11:00
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<BR><A HREF="javascript:displayWindow('images/20-01.jpg',407,335)"> --><FONT COLOR="#000077"><B>Figure 20.1</B></FONT></A>&nbsp;&nbsp;<I>The Pentium&#146;s two pipes.</I>
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<P>Getting two instructions executing simultaneously in the two pipes is trickier than it sounds, not only because the V-pipe can handle only a relatively small subset of the Pentium&#146;s instruction set, but also because those instructions that the V-pipe can handle are able to pair only with certain U-pipe instructions. For example, <B>MOVSD</B> uses both pipes, so no instruction can be executed in parallel with <B>MOVSD</B>.</P>
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/20-01i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>The use of both pipes does make <B>MOVSD</B> nearly twice as fast on the Pentium as on the 486, but it&#146;s nonetheless slower than using equivalent simpler instructions that allow for superscalar execution. Stick to the Pentium&#146;s RISC-like instructions&#151;the pairable instructions I&#146;ll discuss next&#151;when you&#146;re seeking maximum performance, with just a few exceptions such as <B>REP MOVS</B> and <B>REP STOS</B>.</I></SMALL>
<TABLE WIDTH="100%"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="5%"><IMG SRC="images/i.jpg"><TD VALIGN="TOP" ALIGN="LEFT" WIDTH="95%"><SMALL><I>The use of both pipes does make <B>MOVSD</B> nearly twice as fast on the Pentium as on the 486, but it&#146;s nonetheless slower than using equivalent simpler instructions that allow for superscalar execution. Stick to the Pentium&#146;s RISC-like instructions&#151;the pairable instructions I&#146;ll discuss next&#151;when you&#146;re seeking maximum performance, with just a few exceptions such as <B>REP MOVS</B> and <B>REP STOS</B>.</I></SMALL>
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<P>Trickier yet, register contention can shut down the V-pipe on any given cycle, and Address Generation Interlocks (AGIs) can stall either pipe at any time, as we&#146;ll see in the next chapter.
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