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Convert notes into blockquotes

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James Gregory 2013-12-31 11:06:31 +11:00
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@ -140,9 +140,14 @@ in Figure 20.3—a full cycle *faster* than **PUSH [*mem*]**, which takes
V-pipe-executable instructions to execute simultaneously (pair) in the
V-pipe.**
------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
![](images/i.jpg) *A fundamental rule of Pentium optimization is that it pays to break complex instructions into equivalent simple instructions, then shuffle the simple instructions for maximum use of the V-pipe. This is true partly because most of the pairable instructions are simple instructions, and partly because breaking instructions into pieces allows more freedom to rearrange code to avoid the AGIs and register contention I'll discuss in the next chapter.*
------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ![](images/i.jpg)
> A fundamental rule of Pentium optimization is that it pays to break
> complex instructions into equivalent simple instructions, then shuffle
> the simple instructions for maximum use of the V-pipe. This is true
> partly because most of the pairable instructions are simple
> instructions, and partly because breaking instructions into pieces
> allows more freedom to rearrange code to avoid the AGIs and register
> contention I'll discuss in the next chapter.
![**Figure 20.2**  *Instruction flow through the two pipes.*](images/20-02.jpg)
@ -175,6 +180,8 @@ proper sequencing, interleaving the simple instructions with other
instructions that don't use EDX or **Mem Var**, the three-instruction
sequence can be reduced to 1.5 cycles, but it is *14* bytes long.
------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
![](images/i.jpg) *It's not unusual for Pentium optimization to approximately double both performance and code size at the same time. In an important loop, go for performance and ignore the size, but on a program-wide basis, the size bears watching.*
------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> ![](images/i.jpg)
> It's not unusual for Pentium optimization to approximately double both
> performance and code size at the same time. In an important loop, go for
> performance and ignore the size, but on a program-wide basis, the size
> bears watching.