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04-04.md
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04-04.md
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@ -38,9 +38,12 @@ depending on the code mix preceding that instruction.* Similarly, the
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state in which a given instruction leaves the prefetch queue affects the
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overall execution time of the following instructions.
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------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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 *In other words, while the execution time for a given instruction is constant, the fetch time for that instruction depends heavily on the context in which the instruction is executing—the amount of prefetching the preceding instructions allowed—and can vary from a full 4 cycles per instruction byte to no time at all.*
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------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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> 
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> In other words, while the execution time for a given instruction is
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> constant, the fetch time for that instruction depends heavily on the
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> context in which the instruction is executing—the amount of prefetching
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> the preceding instructions allowed—and can vary from a full 4 cycles per
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> instruction byte to no time at all.
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As we'll see later, other cycle-eaters, such as DRAM refresh and display
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memory wait states, can cause prefetching variations even during
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