diff --git a/20-02.md b/20-02.md
index aed722d..d66f329 100644
--- a/20-02.md
+++ b/20-02.md
@@ -40,8 +40,6 @@ waits until the first instruction is done, then executes in the U-pipe,
 possibly pairing with the next instruction in line if all pairing
 conditions are met.
 
-* * * * *
-
     MOV      reg,reg          (1 cycle)
              mem,reg          (1 cycle)
              reg,mem          (1 cycle)
@@ -82,8 +80,6 @@ conditions are met.
 
 **Table 20.1 Instructions that can execute in the V-pipe.**
 
-* * * * *
-
 The list of instructions the V-pipe can handle is not very long, and the
 list of U-pipe pairable instructions is not much longer, but these
 actually constitute the bulk of the instructions used in PC software. As
@@ -104,8 +100,6 @@ each of 2 cycles, for 2\*0.5 = 1 cycle total execution time), as shown
 in Figure 20.3—a full cycle *faster* than **PUSH [*mem*]**, which takes
 2 cycles.
 
-* * * * *
-
     MOV      reg,reg           (1 cycle)
              mem,reg           (1 cycle)
              reg,mem           (1 cycle)
@@ -146,8 +140,6 @@ in Figure 20.3—a full cycle *faster* than **PUSH [*mem*]**, which takes
 V-pipe-executable instructions to execute simultaneously (pair) in the
 V-pipe.**
 
-* * * * *
-
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   ![](images/i.jpg)   *A fundamental rule of Pentium optimization is that it pays to break complex instructions into equivalent simple instructions, then shuffle the simple instructions for maximum use of the V-pipe. This is true partly because most of the pairable instructions are simple instructions, and partly because breaking instructions into pieces allows more freedom to rearrange code to avoid the AGIs and register contention I'll discuss in the next chapter.*
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