Convert figure images to markdown
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27-01.md
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@ -92,8 +92,7 @@ the latch byte. Finally, the byte from the bit mask circuitry for each
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plane is written to that plane if the corresponding bit in the Map Mask
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register is set to 1.
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\
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**Figure 27.1** *VGA data flow in write mode 2.*
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------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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 *It's worth noting two differences between write mode 2 and write mode 0, the standard write mode of the VGA. First, rotation of the CPU data byte does not take place in write mode 2. Second, the Set/Reset and Enable Set/Reset registers have no effect in write mode 2.*
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