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12-02.md
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@ -102,8 +102,7 @@ improvement in the performance of the entire loop. But wait, there's
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more. If a register is loaded 2 cycles (which generally means 2
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instructions, but, because some 486 instructions take more than 1 cycle,
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\
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**Figure 12.1** *One-cycle-ahead address pipelining.*
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the 2 are not always equivalent) before it's used to point to memory, 1
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cycle is lost. Therefore, whereas this code
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@ -143,8 +142,7 @@ Figure 12.2 will do just fine for optimization purposes.)
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Clearly, there's considerable optimization potential in careful
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rearrangement of 486 code.
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\
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**Figure 12.2** *Two-cycle-ahead address pipelining.*
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### Caveat Programmor {#Heading7}
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