Initial conversion to markdown

28-01.md

@@ -0,0 +1,76 @@
+  ------------------------ --------------------------------- --------------------
+  [Previous](27-05.html)   [Table of Contents](index.html)   [Next](28-02.html)
+  ------------------------ --------------------------------- --------------------
+
+Chapter 28\
+ Reading VGA Memory {#Heading1}
+-------------------
+
+### Read Modes 0 and 1, and the Color Don’t Care Register {#Heading2}
+
+Well, it’s taken five chapters, but we’ve finally covered the data write
+path and all four write modes of the VGA. Now it’s time to tackle the
+VGA’s two read modes. While the read modes aren’t as complex as the
+write modes, they’re nothing to sneeze at. In particular, read mode 1
+(also known as color compare mode) is rather unusual and not at all
+intuitive.
+
+You may well ask, isn’t *anything* about programming the VGA
+straightforward? Well...no. But then, clearing up the mysteries of VGA
+programming is what this part of the book is all about, so let’s get
+started.
+
+### Read Mode 0 {#Heading3}
+
+Read mode 0 is actually relatively uncomplicated, given that you
+understand the four-plane nature of the VGA. (If you don’t understand
+the four-plane nature of the VGA, I strongly urge you to read Chapters
+23-27 before continuing with this chapter.) Read mode 0, the read mode
+counterpart of write mode 0, lets you read from one (and only one) plane
+of VGA memory at any one time.
+
+Read mode 0 is selected by setting bit 3 of the Graphics Mode register
+(Graphics Controller register 5) to 0. When read mode 0 is active, the
+plane that supplies the data when the CPU reads VGA memory is the plane
+selected by bits 1 and 0 of the Read Map register (Graphics Controller
+register 4). When the Read Map register is set to 0, CPU reads come from
+plane 0 (the plane that normally contains blue pixel data). When the
+Read Map register is set to 1, CPU reads come from plane 1; when the
+Read Map register is 2, CPU reads come from plane 2; and when the Read
+Map register is 3, CPU reads come from plane 3.
+
+That all seems simple enough; in read mode 0, the Read Map register acts
+as a selector among the four planes, determining which one of the planes
+will supply the value returned to the CPU. There is a slight
+complication, however, in that the value written to the Read Map
+register in order to read from a given plane is not the same as the
+value written to the Map Mask register (Sequence Controller register 2)
+in order to write to that plane.
+
+Why is that? Well, in read mode 0, one and only one plane can be read at
+a time, so there are only four possible settings of the Read Map
+register: 0, 1, 2, or 3, to select reads from plane 0, 1, 2, or 3. In
+write mode 0, by contrast (in fact, in any write mode), any or all
+planes may be written to at once, since the byte written by the CPU can
+“fan out” to multiple planes. Consequently, there are not four but
+sixteen possible settings of the Map Mask register. The setting of the
+Map Mask register to write only to plane 0 is 1; to write only to plane
+1 is 2; to write only to plane 2 is 4; and to write only to plane 3 is
+8.
+
+As you can see, the settings of the Read Map and Map Mask registers for
+accessing a given plane don’t match. The code in Listing 28.1
+illustrates this. Listing 28.1 simply copies a sixteen-color image from
+system memory to VGA memory, one plane at a time, then animates by
+repeatedly copying the image back to system memory, again one plane at a
+time, clearing the old image, and copying the image to a new location in
+VGA memory. Note the differing settings of the Read Map and Map Mask
+registers.
+
+  ------------------------ --------------------------------- --------------------
+  [Previous](27-05.html)   [Table of Contents](index.html)   [Next](28-02.html)
+  ------------------------ --------------------------------- --------------------
+
+* * * * *
+
+Graphics Programming Black Book © 2001 Michael Abrash