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[Previous](20-04.html) [Table of Contents](index.html) [Next](21-02.html)
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Chapter 21\
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Unleashing the Pentium’s V-Pipe {#Heading1}
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--------------------------------
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### Focusing on Keeping Both Pentium Pipes Full {#Heading2}
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The other day, my daughter suggested that we each draw the prettiest
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picture we could, then see whose was prettier. I won’t comment on who
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won, except to note that apparently a bolt of lightning zipping toward a
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moose with antlers that bear an unfortunate resemblance to a propeller
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beanie isn’t going to win me any scholarships to art school, if you
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catch my drift. Anyway, my drawing happened to feature the word
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“chartreuse” (because it rhymed with “moose” and “Zeus”—hence the
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lightning; more than that I am not at liberty to divulge), and she
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wanted to know if the moose was actually chartreuse. I had to admit that
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I didn’t know, so we went to the dictionary, whereupon we learned that
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chartreuse is a pale apple-green color. Then she brought up the Windows
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Control Panel, pointed to the selection of predefined colors, and asked,
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“Which of those is chartreuse?”—and I realized that I *still* didn’t
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know.
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Some things can be described perfectly with words, but others just have
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to be experienced. Color is one such category, and Pentium optimization
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is another. I’ve spent the last two chapters detailing the rules for
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Pentium optimization, and I’ll spend half of this one doing so, as well.
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That’s good; without understanding the fundamentals, we have no chance
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of optimizing well. It’s not enough, though. We also need to look at a
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real-world example of Pentium optimization in action, and we’ll do that
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later in this chapter; after which, you should go out and do some
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Pentium optimization on your own. Optimization is one of those things
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that you can learn a lot about from reading, but ultimately it has to
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sink into your pores as you do it—especially Pentium optimization
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because the Pentium is perhaps the most complex (and rewarding) chip to
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optimize for that I’ve ever seen.
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In the last chapter, we explored the dual-execution-pipe nature of the
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Pentium, and learned which instructions could pair (execute
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simultaneously) in which pipes. Now we’re ready to look at AGIs and
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register contention—two hazards that can prevent otherwise properly
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written code from taking full advantage of the Pentium’s two pipes, and
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can thereby keep your code from pushing the Pentium to maximum
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performance.
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### Address Generation Interlocks {#Heading3}
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The Pentium is advertised as having a five-stage pipeline for each of
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its execution units. All this means is that at any given time, up to
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five instructions are in various stages of execution in each pipe; this
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overlapping of execution is done for speed, so each instruction doesn’t
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have to wait until the previous one has finished. The only way that the
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Pentium’s pipelining directly affects the way you program is in the
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areas of AGIs and register dependencies.
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AGIs are *Address Generation Interlocks*, a fancy way of saying that if
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a register is used to address memory, as is EBX in this instruction
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mov [ebx],eax
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and the value of the register is not set far enough ahead for the
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Pentium to perform the addressing calculations before the instruction
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needs the address, then the Pentium will stall the pipe in which the
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instruction is executing until the value becomes available and the
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addressing calculations have been performed. Remember, also, that
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instructions execute in lockstep on the Pentium, so if one pipe stalls
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for a cycle, making its instruction take one cycle longer, that extends
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by one cycle the time until the other pipe can begin its next
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instruction, as well.
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The rule for AGIs is simple: If you modify any part of a register during
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a cycle, you cannot use that register to address memory during either
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that cycle or the next cycle. If you try to do this, the Pentium will
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simply stall the instruction that tries to use that register to address
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memory until two cycles after the register was modified. This was true
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on the 486 as well, but the Pentium’s new twist is that since more than
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one instruction can execute in a single cycle, an AGI can stall an
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instruction that’s as many as three instructions away from the changing
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of the addressing register, as shown in Figure 21.1, and an AGI can also
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cause a stall that costs as many as three instructions, as shown in
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Figure 21.2. This means that AGIs are both much easier to cause and
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potentially more expensive than on the 486, and you must keep a sharp
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eye out for them. It also means that it’s often worth calculating a
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memory pointer several instructions ahead of its actual use.
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Unfortunately, this tends to extend the lifetimes of pointer registers
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to span a greater number of instructions, making the Pentium’s
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relatively small register set seem even smaller.
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\
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**Figure 21.1** *An AGI can stall up to three instructions later.*
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As an example of a sort of AGI that’s new to the Pentium, consider the
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following test for a NULL pointer, followed by the use of the pointer if
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it’s not NULL:
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push ebx ;U-pipe cycle 1
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mov ebx,[Ptr] ;V-pipe cycle 1
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and ebx,ebx ;U-pipe cycle 2
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jz short IsNull ;V-pipe cycle 2
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mov eax,[ebx] ;U-pipe cycle 3 AGI stall
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mov edx,[ebp-8] ;V-pipe cycle 3 lockstep idle
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;U-pipe cycle 4 mov eax,[ebx]
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;V-pipe cycle 4 mov edx,[ebp-8]
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This commonplace code loses a U-pipe cycle to the AGI caused by **AND
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EBX,EBX**, followed by the attempt two instructions later to use EBX to
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point to memory. The code loses a V-pipe cycle as well, because lockstep
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execution won’t let the next V-pipe instruction execute until the paired
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U-pipe instruction that suffered the AGI finishes. The solution is to
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use **TEST EBX,EBX** instead of **AND; TEST** can’t modify EBX, so no
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AGI occurs. Sure, **AND EBX,EBX** doesn’t modify EBX either, but the
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Pentium doesn’t know that, so it has to insert the AGI.
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\
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**Figure 21.2** *An AGI can cost as many as 3 cycles.*
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------------------------ --------------------------------- --------------------
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[Previous](20-04.html) [Table of Contents](index.html) [Next](21-02.html)
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------------------------ --------------------------------- --------------------
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* * * * *
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Graphics Programming Black Book © 2001 Michael Abrash
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