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[Previous](19-01.html) [Table of Contents](index.html) [Next](19-03.html)
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 *The Pentium, on the other hand, has two separate 8K caches, one for code and one for data, so code prefetches can never collide with data fetches; the prefetch queue can stall only when the code being fetched isn’t in the internal code cache.*
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------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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(And yes, self-modifying code still works; as with all Pentium changes,
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the dual caches introduce no incompatibilities with 386/486 code.) Also,
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because the code and data caches are separate, code can’t be driven out
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of the cache in a tight loop that accesses a lot of data, unlike the
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486. In addition, the Pentium expands the 486’s 32-byte prefetch queue
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to 128 bytes. In conjunction with the branch prediction feature
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(described next), which allows the Pentium to prefetch properly at most
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branches, this larger prefetch queue means that the Pentium’s two pipes
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should be better fed than those of any previous x86 processor.
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#### Crossing Cache Lines {#Heading5}
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There are three other characteristics of the Pentium that make for a
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healthy supply of instruction bytes. One is that the Pentium can
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prefetch instructions across cache lines. Unlike the 486, where there is
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a 3-cycle penalty for branching to an instruction that spans a cache
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line, there’s no such penalty on the Pentium. The second is that the
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cache line size (the number of bytes fetched from the external cache or
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main memory on a cache miss) on the Pentium is 32 bytes, twice the size
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of the 486’s cache line, so a cache miss causes a longer run of
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instructions to be placed in the cache than on the 486. The third is
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that the Pentium’s external bus is twice as wide as the 486’s, at 64
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bits, and runs twice as fast, at 66 MHz, so the Pentium can fetch both
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instruction and data bytes from the external cache four times as fast as
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the 486.
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------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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 *Even when the Pentium is running flat-out with both pipes in use, it can generally consume only about twice as many bytes as the 486; so the ratio of external memory bandwidth to processing power is much improved, although real-world performance is heavily dependent on the size and speed of the external cache.*
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------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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The upshot of all this is that at the same clock speed, with code and
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data that are mostly in the internal caches, the Pentium maxes out
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somewhere around twice as fast as a 486. (When the caches are missed a
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lot, the Pentium can get as much as three to four times faster, due to
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the superior external bus and bigger caches.) Most of this won’t affect
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how you program, but it is useful to know that you don’t have to worry
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about instruction fetching. It’s also useful to know the sizes of the
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caches because a high cache hit rate is crucial to Pentium performance.
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Cache misses are vastly slower than cache hits (anywhere from two to 50
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or more times as slow, depending on the speed of the external cache and
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whether the external cache misses as well), and the Pentium can’t use
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the V-pipe on code that hasn’t already been executed out of the cache at
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least once. This means that it is *very* important to get the working
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sets of critical loops to fit in the internal caches.
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One change in the Pentium that you definitely do have to worry about is
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superscalar execution. Utilization of the V-pipe can range from near
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zero percent to 100 percent, depending on the code being executed, and
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careful rearrangement of code can have amazing effects. Maxing out
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V-pipe use is not a trivial task; I’ll spend all of the next chapter
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discussing it so as to have time to cover it properly. In the meantime,
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two good references for superscalar programming and other Pentium
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information are Intel’s *Pentium Processor User’s Manual: Volume 3:
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Architecture and Programming Manual* (ISBN 1-55512-195-0; Intel order
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number 241430-001), and the article “Optimizing Pentium Code” by Mike
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Schmidt, in *Dr. Dobb’s Journal* for January 1994.
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#### Cache Organization {#Heading6}
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There are two other interesting changes in the Pentium’s cache
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organization. First, the cache is two-way set-associative, whereas the
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486 is four-way set-associative. The details of this don’t matter, but
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simply put, this, combined with the 32-byte cache line size, means that
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the Pentium has somewhat coarser granularity in both space and time than
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the 486 in terms of packing bytes into the cache, although the total
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cache space is now bigger. There’s nothing you can do about this, but it
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may make it a little harder to get a loop’s working set into the cache.
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Second, the internal cache can now be configured (by the BIOS or OS; you
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won’t have to worry about it) for write-back rather than write-through
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operation. This means that writes to the internal data cache don’t
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necessarily get propagated to the external bus until other demands for
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cache space force the data out of the cache, making repeated writes to
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memory variables such as loop counters cheaper on average than on the
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486, although not as cheap as registers.
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As a final note on Pentium architecture for this chapter, the pipeline
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stalls (what Intel calls AGIs, for *Address Generation Interlocks*) that
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I discussed earlier in this book (see Chapter 12) are still present in
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the Pentium. In fact, they’re there in spades on the Pentium; the two
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pipelines mean that an AGI can now slow down execution of an instruction
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that’s *three* instructions away from the AGI (because four instructions
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can execute in two cycles). So, for example, the code sequence
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add edx,4 ;U-pipe cycle 1
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mov ecx,[ebx] ;V-pipe cycle 1
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add ebx,4 ;U-pipe cycle 2
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mov [edx],ecx ;V-pipe cycle 3
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; due to AGI
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; (would have been
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; V-pipe cycle 2)
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takes three cycles rather than the two cycles it should take, because
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EDX was modified on cycle 1 and an attempt was made to use it on cycle
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two, before the AGI had time to clear—even though there are two
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instructions between the instructions that are actually involved in the
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AGI. Rearranging the code like
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mov ecx,[ebx] ;U-pipe cycle 1
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add ebx,4 ;V-pipe cycle 1
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mov [edx+4],ecx ;U-pipe cycle 2
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add edx,4 ;V-pipe cycle 2
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makes it functionally identical, but cuts the cycles to 2—a 50 percent
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improvement. Clearly, avoiding AGIs becomes a much more challenging and
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rewarding game in a superscalar world, one to which I’ll return in the
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next chapter.
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------------------------ --------------------------------- --------------------
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[Previous](19-01.html) [Table of Contents](index.html) [Next](19-03.html)
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------------------------ --------------------------------- --------------------
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* * * * *
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Graphics Programming Black Book © 2001 Michael Abrash
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