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This commit is contained in:
James Gregory
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47-03.html
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47-03.html
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@ -36,11 +36,11 @@
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</TABLE>
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</CENTER>
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<P><BR></P>
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<P>After setting up mode 13H, Listing 47.1 alters the vertical counts and timings to select 480 visible scan lines. (There’s no need to alter any horizontal values, because mode 13H and Mode X both have 320-pixel horizontal resolutions.) The Maximum Scan Line register is programmed to double scan each line (that is, repeat each scan line twice), however, so we get an effective vertical resolution of 240 scan lines. It is, in fact, possible to get 400 or 480 independent scan lines in 256-color mode, as discussed in Chapter 31 and 32; however, 400-scan-line modes lack square pixels and can’t support simultaneous off-screen memory and page flipping. Furthermore, 480-scan-line modes lack page flipping altogether, due to memory constraints.
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<P>After setting up mode 13H, Listing 47.1 alters the vertical counts and timings to select 480 visible scan lines. (There’s no need to alter any horizontal values, because mode 13H and Mode X both have 320-pixel horizontal resolutions.) The Maximum Scan Line register is programmed to double scan each line (that is, repeat each scan line twice), however, so we get an effective vertical resolution of 240 scan lines. It is, in fact, possible to get 400 or 480 independent scan lines in 256-color mode, as discussed in Chapter 31 and 32; however, 400-scan-line modes lack square pixels and can’t support simultaneous off-screen memory and page flipping. Furthermore, 480-scan-line modes lack page flipping altogether, due to memory constraints.
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</P>
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<P>At the same time, Listing 47.1 programs the VGA’s bitmap to a planar organization that is similar to that used by the 16-color modes, and utterly different from the linear bitmap of mode 13H. The bizarre bitmap organization of Mode X is shown in Figure 47.1. The first pixel (the pixel at the upper left corner of the screen) is controlled by the byte at offset 0 in plane 0. (The one thing that Mode X blessedly has in common with mode 13H is that each pixel is controlled by a single byte, eliminating the need to mask out individual bits of display memory.) The second pixel, immediately to the right of the first pixel, is controlled by the byte at offset 0 in plane 1. The third pixel comes from offset 0 in plane 2, and the fourth pixel from offset 0 in plane 3. Then, the fifth pixel is controlled by the byte at offset 1 in plane 0, and that cycle continues, with each group of four pixels spread across the four planes at the same address. The offset M of pixel N in display memory is M = N/4, and the plane P of pixel N is P = N mod 4. For display memory writes, the plane is selected by setting bit P of the Map Mask register (Sequence Controller register 2) to 1 and all other bits to 0; for display memory reads, the plane is selected by setting the Read Map register (Graphics Controller register 4) to P.</P>
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<P>At the same time, Listing 47.1 programs the VGA’s bitmap to a planar organization that is similar to that used by the 16-color modes, and utterly different from the linear bitmap of mode 13H. The bizarre bitmap organization of Mode X is shown in Figure 47.1. The first pixel (the pixel at the upper left corner of the screen) is controlled by the byte at offset 0 in plane 0. (The one thing that Mode X blessedly has in common with mode 13H is that each pixel is controlled by a single byte, eliminating the need to mask out individual bits of display memory.) The second pixel, immediately to the right of the first pixel, is controlled by the byte at offset 0 in plane 1. The third pixel comes from offset 0 in plane 2, and the fourth pixel from offset 0 in plane 3. Then, the fifth pixel is controlled by the byte at offset 1 in plane 0, and that cycle continues, with each group of four pixels spread across the four planes at the same address. The offset M of pixel N in display memory is M = N/4, and the plane P of pixel N is P = N mod 4. For display memory writes, the plane is selected by setting bit P of the Map Mask register (Sequence Controller register 2) to 1 and all other bits to 0; for display memory reads, the plane is selected by setting the Read Map register (Graphics Controller register 4) to P.</P>
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<P>It goes without saying that this is one ugly bitmap organization, requiring a lot of overhead to manipulate a single pixel. The write pixel code shown in Listing 47.2 must determine the appropriate plane and perform a 16-bit <B>OUT</B> to select that plane for each pixel written, and likewise for the read pixel code shown in Listing 47.3. Calculating and mapping in a plane once for each pixel written is scarcely a recipe for performance.</P>
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<P>That’s all right, though, because most graphics software spends little time drawing individual pixels. I’ve provided the write and read pixel routines as basic primitives, and so you’ll understand how the bitmap is organized, but the building blocks of high-performance graphics software are fills, copies, and bitblts, and it’s there that Mode X shines.</P>
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<P>That’s all right, though, because most graphics software spends little time drawing individual pixels. I’ve provided the write and read pixel routines as basic primitives, and so you’ll understand how the bitmap is organized, but the building blocks of high-performance graphics software are fills, copies, and bitblts, and it’s there that Mode X shines.</P>
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<P><A NAME="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/47-01.jpg',408,263 )"> --><IMG SRC="images/47-01.jpg"><BR><!-- </A>
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<BR><A HREF="javascript:displayWindow('images/47-01.jpg',408,263)"> --><FONT COLOR="#000077"><B>Figure 47.1</B></FONT></A> <I>Mode X display memory organization.</I>
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</P>
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@ -72,30 +72,30 @@ parms ends
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.code
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public _WritePixelX
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_WritePixelX proc near
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push bp ;preserve caller’s stack frame
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push bp ;preserve caller’s stack frame
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mov bp,sp ;point to local stack frame
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mov ax,SCREEN_WIDTH
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mul [bp+Y] ;offset of pixel’s scan line in page
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mov bx,[bp+X]
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mul [bp+Y] ;offset of pixel’s scan line in page
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mov bx,[bp+X]
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shr bx,1
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shr bx,1 ;X/4 = offset of pixel in scan line
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add bx,ax ;offset of pixel in page
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add bx,[bp+PageBase] ;offset of pixel in display memory
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add bx,[bp+PageBase] ;offset of pixel in display memory
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mov ax,SCREEN_SEG
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mov es,ax ;point ES:BX to the pixel’s address
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mov es,ax ;point ES:BX to the pixel’s address
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mov cl,byte ptr [bp+X]
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and cl,011b ;CL = pixel’s plane
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mov ax,0100h + MAP_MASK ;AL = index in SC of Map Mask reg
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shl ah,cl ;set only the bit for the pixel’s plane to 1
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mov cl,byte ptr [bp+X]
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and cl,011b ;CL = pixel’s plane
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mov ax,0100h + MAP_MASK ;AL = index in SC of Map Mask reg
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shl ah,cl ;set only the bit for the pixel’s plane to 1
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mov dx,SC_INDEX ;set the Map Mask to enable only the
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out dx,ax ; pixel’s plane
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out dx,ax ; pixel’s plane
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mov al,byte ptr [bp+Color]
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mov al,byte ptr [bp+Color]
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mov es:[bx],al ;draw the pixel in the desired color
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pop bp ;restore caller’s stack frame
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pop bp ;restore caller’s stack frame
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ret
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_WritePixelX endp
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end
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@ -127,29 +127,29 @@ parms ends
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.code
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public _ReadPixelX
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_ReadPixelX proc near
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push bp ;preserve caller’s stack frame
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push bp ;preserve caller’s stack frame
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mov bp,sp ;point to local stack frame
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mov ax,SCREEN_WIDTH
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mul [bp+Y] ;offset of pixel’s scan line in page
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mov bx,[bp+X]
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mul [bp+Y] ;offset of pixel’s scan line in page
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mov bx,[bp+X]
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shr bx,1
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shr bx,1 ;X/4 = offset of pixel in scan line
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add bx,ax ;offset of pixel in page
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add bx,[bp+PageBase] ;offset of pixel in display memory
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add bx,[bp+PageBase] ;offset of pixel in display memory
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mov ax,SCREEN_SEG
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mov es,ax ;point ES:BX to the pixel’s address
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mov es,ax ;point ES:BX to the pixel’s address
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mov ah,byte ptr [bp+X]
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and ah,011b ;AH = pixel’s plane
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mov ah,byte ptr [bp+X]
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and ah,011b ;AH = pixel’s plane
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mov al,READ_MAP ;AL = index in GC of the Read Map reg
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mov dx,GC_INDEX ;set the Read Map to read the pixel’s
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mov dx,GC_INDEX ;set the Read Map to read the pixel’s
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out dx,ax ; plane
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mov al,es:[bx] ;read the pixel’s color
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mov al,es:[bx] ;read the pixel’s color
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sub ah,ah ;convert it to an unsigned int
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pop bp ;restore caller’s stack frame
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pop bp ;restore caller’s stack frame
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ret
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_ReadPixelX endp
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end
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