Change bold code snippets to inline code blocks
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28-05.md
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28-05.md
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@ -14,12 +14,12 @@ Listing 28.3 illustrates an efficient use of write mode 3 in conjunction
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with read mode 1 and a Color Don't Care register setting of 0. The mask
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in AL is passed directly to the VGA's bit mask (that's how write mode 3
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works—see Chapter 4 for details). Because the VGA always returns 0FFH,
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the single **AND** instruction loads the latches, and writes the value
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the single `AND` instruction loads the latches, and writes the value
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in AL, unmodified, to the VGA, where it is used to generate the bit
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mask. This is more compact and register-efficient than using separate
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instructions to read and write, although it is not necessarily faster by
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cycle count, because on a 486 or a Pentium **MOV** is a 1-cycle
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instruction, but **AND** with memory is a 3-cycle instruction. However,
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cycle count, because on a 486 or a Pentium `MOV` is a 1-cycle
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instruction, but `AND` with memory is a 3-cycle instruction. However,
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given display memory wait states, it is often the case that the two
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approaches run at the same speed, and the register that the above
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approach frees up can frequently be used to save one or more cycles in
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