Change bold code snippets to inline code blocks

21-04.md

@@ -10,19 +10,19 @@ chapter: '21'
 pages: 407-409
 ---
 
-The first, obvious thing we can do to Listing 21.1 is change **ADC
-AX,0** to **ADC EAX,0**, eliminating a prefix byte and saving a full
-cycle. Now we're down from five to four cycles. What next?
+The first, obvious thing we can do to Listing 21.1 is change `ADC AX,0` to
+`ADC EAX,0`, eliminating a prefix byte and saving a full cycle. Now we're
+down from five to four cycles. What next?
 
 Listing 21.2 shows one interesting alternative that doesn't really buy
 us anything. Here, we've eliminated all size prefixes by doing
-byte-sized **MOVs** and **ADDs**, but because the size prefix on **ADD
-AX,[ESI]**, for whatever reason, didn't cost anything in Listing 21.1,
+byte-sized `MOVs` and `ADDs`, but because the size prefix on `ADD 
+AX,[ESI]`, for whatever reason, didn't cost anything in Listing 21.1,
 our efforts are to no avail—Listing 21.2 still takes 4 cycles per
 checksummed word. What's worth noting about Listing 21.2 is the extent
 to which the code is broken into simple instructions and reordered so as
 to avoid size prefixes, register contention, AGIs, and data bank
-conflicts (the latter because both **[ESI]** and **[ESI+1]** are in the
+conflicts (the latter because both `[ESI]` and `[ESI+1]` are in the
 same cache data bank, as discussed in the last chapter).
 
 **LISTING 21.2 L21-2.ASM**
@@ -66,7 +66,7 @@ instructions than 486-optimized code. Again, note the careful mixing of
 byte-sized reads to avoid AGIs, register contention, and cache bank
 collisions, in particular the way in which the byte reads of memory are
 interspersed with the additions to avoid register contention, and the
-placement of **ADD ESI,4** to avoid an AGI.
+placement of `ADD ESI,4` to avoid an AGI.
 
 **LISTING 21.3 L21-3.ASM**