Change bold code snippets to inline code blocks

21-02.md

@@ -11,7 +11,7 @@ pages: 402-405
 ---
 
 As on the 486, you should keep a careful eye out for AGIs involving the
-stack pointer. Implicit modifiers of ESP, such as **PUSH** and **POP**,
+stack pointer. Implicit modifiers of ESP, such as `PUSH` and `POP`,
 are special-cased so you don't have to worry about AGIs. However, if you
 explicitly modify ESP with this instruction
 
@@ -32,7 +32,7 @@ either explicitly with instructions like this one
 moveax,[esp+20h]
 ```
 
-or via **PUSH**, **POP**, or other instructions that implicitly use ESP
+or via `PUSH`, `POP`, or other instructions that implicitly use ESP
 as an addressing register.
 
 On the 486, any instruction that had both a constant value and an
@@ -44,7 +44,7 @@ mov dword ptr [ebp+16],1
 
 suffered a 1-cycle penalty, taking a total of 2 cycles. Such
 instructions take only one cycle on the Pentium, but they cannot pair,
-so they're still the most expensive sort of **MOV**. Knowing this can
+so they're still the most expensive sort of `MOV`. Knowing this can
 speed up something as simple as zeroing two memory variables, as in
 
 ```nasm
@@ -67,7 +67,7 @@ mov [MemVar2],0 ;U-pipe 2
 Note, however, that my experiments thus far indicate that the two writes
 in the first case don't actually pair (possibly because the memory
 variables have never been read into the internal cache), so you might
-want to insert an instruction between the two **MOV**s—and, of course,
+want to insert an instruction between the two `MOV`s—and, of course,
 this is yet another reason why you should always measure your code's
 actual performance.
 
@@ -85,9 +85,9 @@ inc eax     ;U-pipe cycle 1
 and ebx,eax ;U-pipe cycle 2
 ```
 
-in a single cycle; **AND EBX,EAX** can't execute until the value in EAX
-is known, and that can't happen until **INC EAX** is done. Consequently,
-the V-pipe idles while **INC EAX** executes in the U-pipe. We saw this
+in a single cycle; `AND EBX,EAX` can't execute until the value in EAX
+is known, and that can't happen until `INC EAX` is done. Consequently,
+the V-pipe idles while `INC EAX` executes in the U-pipe. We saw this
 in the last chapter when we discussed splitting instructions into simple
 instructions, and it is by far the most common sort of register
 contention, known as read-after-write register contention.
@@ -109,8 +109,8 @@ mov al,[Var]  ;U-pipe cycle 2
 
 where an attempt is made to set both EAX and its AL subregister on the
 same cycle. Write-after-write contention implies that the two
-instructions comprising the above substitute for **MOVZX** should have
-at least one unrelated instruction between them when **SUB EAX,EAX**
+instructions comprising the above substitute for `MOVZX` should have
+at least one unrelated instruction between them when `SUB EAX,EAX`
 executes in the V-pipe.
 
 #### Exceptions to Register Contention {#Heading5}
@@ -129,10 +129,10 @@ are free of charge.
 Also, stack-related instructions that modify ESP only implicitly
 (without ESP as part of any explicit operand) do not cause AGIs, and
 neither do they cause register contention with other instructions that
-use ESP only implicitly; such instructions include **PUSH *reg/immed*,
-POP *reg***, and **CALL**. (However, these instructions do cause
+use ESP only implicitly; such instructions include `PUSH *reg/immed*,
+POP *reg*`, and `CALL`. (However, these instructions do cause
 register contention on ESP—but not AGIs—with instructions that use ESP
-explicitly, such as **MOV EAX,[ESP+4]**.) Without this special case, the
+explicitly, such as `MOV EAX,[ESP+4]`.) Without this special case, the
 following sequence would hardly use the V-pipe at all:
 
 ```nasm
@@ -167,7 +167,7 @@ predicted by the Pentium's branch prediction circuitry (as discussed in
 the last chapter), it executes in a single cycle, pairing if it runs in
 the V-pipe; if mispredicted, conditional jumps take 4 cycles in the
 U-pipe and 5 cycles in the V-pipe, and mispredicted calls and
-unconditional jumps take 3 cycles in either pipe. Note that **RET**
+unconditional jumps take 3 cycles in either pipe. Note that `RET`
 can't pair.
 
 ### Who's in First? {#Heading6}