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Change bold code snippets to inline code blocks

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James Gregory 2013-12-31 17:12:29 +11:00
commit 3c76d884ef
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18
20-04.md
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@ -10,7 +10,7 @@ chapter: '20'
pages: 393-396
---
However, this beneficial pairing does not extend to non-**MOV**
However, this beneficial pairing does not extend to non-`MOV`
instructions with explicit memory destination operands, such as **ADD
[EBX],EAX**. The Pentium executes only one such memory instruction at a
time; if two memory-destination complex instructions get paired, first
@ -18,7 +18,7 @@ the U-pipe instruction is executed, and then the V-pipe instruction,
with only one cycle of overlap, as shown in Figure 20.6. I don't know
for sure, but I'd guess that this is to guarantee that the two pipes
will never perform out-of-order access to any given memory location.
Thus, even though **AND [EBX],AL** pairs with **AND [ECX],DL**, the two
Thus, even though `AND [EBX],AL` pairs with `AND [ECX],DL`, the two
instructions take 5 cycles in all to execute, and 4 cycles of idle
time—2 in the U-pipe and 2 in the V-pipe, out of 10 cycles in all—are
incurred in the process.
@ -54,14 +54,14 @@ mov [ebx],dl
```
and be done with it. The problem here is one of dependency. Before the
Pentium can execute **AND DL,AL,**, it must first know what is in DL,
Pentium can execute `AND DL,AL,`, it must first know what is in DL,
and it can't know that until it loads DL from the address pointed to by
EBX. Therefore, **AND DL,AL** can't happen until the cycle after **MOV
DL,[EBX]** executes. Likewise, the result can't be stored until the
cycle after **AND DL,AL** has finished. This means that these
EBX. Therefore, `AND DL,AL` can't happen until the cycle after `MOV
DL,[EBX]` executes. Likewise, the result can't be stored until the
cycle after `AND DL,AL` has finished. This means that these
instructions, as written, can't possibly pair, so the sequence takes the
same three cycles as **AND [EBX],AL**. (Now it should be clear why **AND
[EBX]**, AL takes 3 cycles.) Consequently, it's necessary to interleave
same three cycles as `AND [EBX],AL`. (Now it should be clear why `AND
[EBX]`, AL takes 3 cycles.) Consequently, it's necessary to interleave
these instructions with instructions that use other registers, so this
set of operations can execute in one pipe while the other, unrelated set
executes in the other pipe, as is done in Figure 20.7.
@ -110,7 +110,7 @@ Finally, bear in mind that if the instructions being executed have not
already been executed at least once since they were loaded into the
internal cache, they can pair only if the first (U-pipe) instruction is
not only pairable but also exactly 1 byte long, a category that includes
only **INC *reg*, DEC *reg*, PUSH *reg***, and **POP *reg***. Knowing
only `INC *reg*, DEC *reg*, PUSH *reg*`, and `POP *reg*`. Knowing
this can help you understand why sometimes, timing reveals that your
code runs slower than it seems it should, although this will generally
occur only when the cache working set for the code you're timing is on