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Change bold code snippets to inline code blocks

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James Gregory 2013-12-31 17:12:29 +11:00
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18
20-03.md
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@ -12,18 +12,18 @@ pages: 390-393
### Lockstep Execution {#Heading5}
You may wonder why anyone would bother breaking **ADD [MemVar],EAX**
You may wonder why anyone would bother breaking `ADD [MemVar],EAX`
into three instructions, given that this instruction can go through
either pipe with equal ease. The answer is that while the
memory-accessing instructions other than **MOV, PUSH**, and **POP**
listed in Table 20.1 (that is, **INC/DEC [*mem*],
ADD/SUB/XOR/AND/OR/CMP/ADC/SBB *reg*,[*mem*]**, and
**ADD/SUB/XOR/AND/OR/CMP/ADC/SBB [*mem*],*reg/immed***) can be paired,
memory-accessing instructions other than `MOV, PUSH`, and `POP`
listed in Table 20.1 (that is, `INC/DEC [*mem*],
ADD/SUB/XOR/AND/OR/CMP/ADC/SBB *reg*,[*mem*]`, and
`ADD/SUB/XOR/AND/OR/CMP/ADC/SBB [*mem*],*reg/immed*`) can be paired,
they do not provide the 100 percent overlap that we seek. If you look at
Tables 20.1 and 20.2, you will see that instructions taking from 1 to 3
cycles can pair. However, any pair of instructions goes through the two
pipes in lockstep. This means, for example, that if **ADD [EBX],EDX** is
going through the U-pipe, and **INC EAX** is going through the V-pipe,
pipes in lockstep. This means, for example, that if `ADD [EBX],EDX` is
going through the U-pipe, and `INC EAX` is going through the V-pipe,
the V-pipe will be idle for 2 of the 3 cycles that the U-pipe takes to
execute its instruction, as shown in Figure 20.4. Out of the theoretical
6 cycles of work that can be done during this time, we actually get only
@ -108,12 +108,12 @@ below. This is yet another example of how different Pentium optimization
can be from everything we've learned about its predecessors.
The problem with pairing non-single-cycle instructions arises when a
pipe executes an instruction other than **MOV** that has an explicit
pipe executes an instruction other than `MOV` that has an explicit
memory operand. (I'll call these *complex memory instructions*. They're
the only pairable instructions, other than branches, that take more than
one cycle.) We've already seen that, because instructions go through the
pipes in lockstep, if one pipe executes a complex memory instruction
such as **ADD EAX,[EBX]** while the other pipe executes a single-cycle
such as `ADD EAX,[EBX]` while the other pipe executes a single-cycle
instruction, the pipe with the faster instruction will sit idle for part
of the time, wasting cycles. You might think that if both pipes execute
complex instructions of the same length, then neither would lie idle,