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Change bold code snippets to inline code blocks

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James Gregory 2013-12-31 17:12:29 +11:00
commit 3c76d884ef
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12
20-02.md
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@ -21,9 +21,9 @@ in Table 20.1 can go through the V-pipe. In addition, the V-pipe can
execute a separate instruction only when one of the instructions listed
in Table 20.2 is executing in the U-pipe; superscalar execution is not
possible while any instruction not listed in Table 20.2 is executing in
the U-pipe. So, for example, if you use **SHR EDX,CL**, which takes 4
the U-pipe. So, for example, if you use `SHR EDX,CL`, which takes 4
cycles to execute, no other instructions can execute during those 4
cycles; if, on the other hand, you use **SHR EDX,10**, it will take 1
cycles; if, on the other hand, you use `SHR EDX,10`, it will take 1
cycle to execute in the U-pipe, and another instruction can potentially
execute concurrently in the V-pipe. (As you can see, similar instruction
sequences can have vastly different performance characteristics on the
@ -93,13 +93,13 @@ same clock speed, even without Pentium-specific optimization, contrary
to some reports.
Besides, almost all operations can be performed by combinations of
pairable instructions. For example, **PUSH [*mem*]** is not on either
list, but both **MOV *reg*,[*mem*]** and **PUSH *reg*** are, and those
pairable instructions. For example, `PUSH [*mem*]` is not on either
list, but both `MOV *reg*,[*mem*]` and `PUSH *reg*` are, and those
two instructions can be used to push a value stored in memory. In fact,
given the proper instruction stream, the discrete instructions can
perform this operation effectively in just 1 cycle (taking one-half of
each of 2 cycles, for 2\*0.5 = 1 cycle total execution time), as shown
in Figure 20.3—a full cycle *faster* than **PUSH [*mem*]**, which takes
in Figure 20.3—a full cycle *faster* than `PUSH [*mem*]`, which takes
2 cycles.
```nasm
@ -189,7 +189,7 @@ mov [MemVar],edx
The single complex instruction takes 3 cycles and is 6 bytes long; with
proper sequencing, interleaving the simple instructions with other
instructions that don't use EDX or **Mem Var**, the three-instruction
instructions that don't use EDX or `Mem Var`, the three-instruction
sequence can be reduced to 1.5 cycles, but it is *14* bytes long.
> ![](images/i.jpg)