Misc/abrash-black-book
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Change bold code snippets to inline code blocks

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James Gregory 2013-12-31 17:12:29 +11:00
commit 3c76d884ef
185 changed files with 1772 additions and 1772 deletions
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04-03.md
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@ -47,7 +47,7 @@ accesses must be. (Remember that the Bus Interface Unit must perform two
byte-sized memory accesses in order to handle a word-sized memory
operand.) However, Listing 4.3 is considerably faster because it expends
only 4 additional cycles to read the second byte of each word, while
Listing 4.4 performs a second **LODSB,** requiring 13 cycles, to read
Listing 4.4 performs a second `LODSB`, requiring 13 cycles, to read
the second byte of each word.
**LISTING 4.3 LST4-3.ASM**
@ -166,7 +166,7 @@ shr ax,1
shr ax,1
```
should execute in 10 cycles, since each **SHR** takes 2 cycles to
should execute in 10 cycles, since each `SHR` takes 2 cycles to
execute, according to Intel's specifications. Those specifications
contain Intel's official instruction execution times, but in this
case—and in many others—the specifications are drastically wrong. Why?